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[61.68.137.140]) by smtp.gmail.com with ESMTPSA id fk10-20020a056a003a8a00b0068718f6a035sm6979207pfb.33.2023.08.07.21.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 21:21:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691468467; x=1692073267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UCnCdFj9EuliCkE/oMkl/TySBNxO/JoW1C8ZeaibWDg=; b=iXECEEG+QZVy5rAtkW/kmbtBGE15pkDa2nDAO2WOqQR+cTK4skh8bnKBodBAYK+ac1 LD++KTt7VDb1wMWNXaGoJ0RRBuz+x75cmhp7EP+grbnvZBZ2QHrrtj/hNRIkaHQ+CqZd wMa1cjtXrixqVgS2TRepaKJkHB1bhxTQBBWheKAYCa2IgsRw6rHB0Qe2Xc5wr8/ndqHW OJBOnxCirNUEmnSE2yssPPP+Bj57ISMqP7yiJfShsUb9OlvIyY/PmZSOavm8tIS+EAJM /eh55uPTNGtHJuUyH+F/5EzG5nSGM5+2dJuS6hSGRXCnXZBrF50euv/KBzF5wuvUc5jj lnWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691468467; x=1692073267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UCnCdFj9EuliCkE/oMkl/TySBNxO/JoW1C8ZeaibWDg=; b=BVNbK2VBWgW1TD0vn7nU5o5bIcOrVh6pHL7dlin/fSvOJ1av17nJZdc7Td2PjruIp/ letbCYLE7q7f6e091VuTeQNzlbqHFXqbah2lVw/2lCO1NBSUXzYbbZ9t2uqKSPbWWQ5s pOPaFYNFMUK8Xad/5vPXbmvcISPhFQwj1SFd5jmqlgXdPWLMO41cZkOcsGqtwpjl9wsu mCPSyBl/QVz45gmDre0QJnmzdstvXyWelVSagKjJPmDLUyLuIaTgl6tVI74UBltvjPwe ZtCXG3B/TbBAvM6FjGhRGXk1jtia2OL0F2KmmbllgjghU7xN5fU328/F5B2r2D/AyZiU alkg== X-Gm-Message-State: AOJu0YxZ/LMzsqS3whOn/LSjwDqQYqZ26xi3m7ORKP2MTOCtJlMaHweP 7ET7qZQnnluhCmpkGpN1M40= X-Google-Smtp-Source: AGHT+IFzAfKVf2yM7fO5eJWk4udIsyh6rXjOdPzaDJFrSbp/bq9k9BngCcZ9yjAOPI7hS32ErM6L0w== X-Received: by 2002:a05:6808:bd5:b0:3a7:3ce0:1ae5 with SMTP id o21-20020a0568080bd500b003a73ce01ae5mr15162867oik.47.1691468467467; Mon, 07 Aug 2023 21:21:07 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , Pavel Dovgalyuk , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/19] hw/ppc: Read time only once to perform decrementer write Date: Tue, 8 Aug 2023 14:19:54 +1000 Message-Id: <20230808042001.411094-13-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808042001.411094-1-npiggin@gmail.com> References: <20230808042001.411094-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=npiggin@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1691468558766100003 Content-Type: text/plain; charset="utf-8" Reading the time more than once to perform an operation always increases complexity and fragility due to introduced deltas. Simplify the decrementer write by reading the clock once for the operation. Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 84 +++++++++++++++++++++++++++++++++------------------- 1 file changed, 53 insertions(+), 31 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index f391acc39e..a0ee064b1d 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -708,13 +708,13 @@ bool ppc_decr_clear_on_delivery(CPUPPCState *env) return ((tb_env->flags & flags) =3D=3D PPC_DECR_UNDERFLOW_TRIGGERED); } =20 -static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) +static inline int64_t __cpu_ppc_load_decr(CPUPPCState *env, int64_t now, + uint64_t next) { ppc_tb_t *tb_env =3D env->tb_env; - uint64_t now, n; + uint64_t n; int64_t decr; =20 - now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); n =3D ns_to_tb(tb_env->decr_freq, now); if (next > n && tb_env->flags & PPC_TIMER_BOOKE) { decr =3D 0; @@ -727,16 +727,12 @@ static inline int64_t _cpu_ppc_load_decr(CPUPPCState = *env, uint64_t next) return decr; } =20 -target_ulong cpu_ppc_load_decr(CPUPPCState *env) +static target_ulong _cpu_ppc_load_decr(CPUPPCState *env, int64_t now) { ppc_tb_t *tb_env =3D env->tb_env; uint64_t decr; =20 - if (kvm_enabled()) { - return env->spr[SPR_DECR]; - } - - decr =3D _cpu_ppc_load_decr(env, tb_env->decr_next); + decr =3D __cpu_ppc_load_decr(env, now, tb_env->decr_next); =20 /* * If large decrementer is enabled then the decrementer is signed exte= ned @@ -750,14 +746,23 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env) return (uint32_t) decr; } =20 -target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) +target_ulong cpu_ppc_load_decr(CPUPPCState *env) +{ + if (kvm_enabled()) { + return env->spr[SPR_DECR]; + } else { + return _cpu_ppc_load_decr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUA= L)); + } +} + +static target_ulong _cpu_ppc_load_hdecr(CPUPPCState *env, int64_t now) { PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); ppc_tb_t *tb_env =3D env->tb_env; uint64_t hdecr; =20 - hdecr =3D _cpu_ppc_load_decr(env, tb_env->hdecr_next); + hdecr =3D __cpu_ppc_load_decr(env, now, tb_env->hdecr_next); =20 /* * If we have a large decrementer (POWER9 or later) then hdecr is sign @@ -771,6 +776,11 @@ target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) return (uint32_t) hdecr; } =20 +target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) +{ + return _cpu_ppc_load_hdecr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); +} + uint64_t cpu_ppc_load_purr (CPUPPCState *env) { ppc_tb_t *tb_env =3D env->tb_env; @@ -815,7 +825,7 @@ static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); } =20 -static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, +static void __cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now, uint64_t *n= extp, QEMUTimer *timer, void (*raise_excp)(void *), void (*lower_excp)(PowerPCCPU *), @@ -824,7 +834,7 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint6= 4_t *nextp, { CPUPPCState *env =3D &cpu->env; ppc_tb_t *tb_env =3D env->tb_env; - uint64_t now, next; + uint64_t next; int64_t signed_value; int64_t signed_decr; =20 @@ -836,18 +846,12 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uin= t64_t *nextp, =20 trace_ppc_decr_store(nr_bits, decr, value); =20 - if (kvm_enabled()) { - /* KVM handles decrementer exceptions, we don't need our own timer= */ - return; - } - /* * Calculate the next decrementer event and set a timer. * decr_next is in timebase units to keep rounding simple. Note it is * not adjusted by tb_offset because if TB changes via tb_offset chang= ing, * decrementer does not change, so not directly comparable with TB. */ - now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); next =3D ns_to_tb(tb_env->decr_freq, now) + value; *nextp =3D next; /* nextp is in timebase units */ =20 @@ -876,12 +880,13 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uin= t64_t *nextp, timer_mod(timer, tb_to_ns_round_up(tb_env->decr_freq, next)); } =20 -static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, - target_ulong value, int nr_bits) +static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now, + target_ulong decr, target_ulong val= ue, + int nr_bits) { ppc_tb_t *tb_env =3D cpu->env.tb_env; =20 - __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, + __cpu_ppc_store_decr(cpu, now, &tb_env->decr_next, tb_env->decr_timer, tb_env->decr_timer->cb, &cpu_ppc_decr_lower, tb_env->flags, decr, value, nr_bits); } @@ -890,13 +895,22 @@ void cpu_ppc_store_decr(CPUPPCState *env, target_ulon= g value) { PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + int64_t now; + target_ulong decr; int nr_bits =3D 32; =20 + if (kvm_enabled()) { + /* KVM handles decrementer exceptions, we don't need our own timer= */ + return; + } + if (env->spr[SPR_LPCR] & LPCR_LD) { nr_bits =3D pcc->lrg_decr_bits; } =20 - _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + decr =3D _cpu_ppc_load_decr(env, now); + _cpu_ppc_store_decr(cpu, now, decr, value, nr_bits); } =20 static void cpu_ppc_decr_cb(void *opaque) @@ -906,14 +920,15 @@ static void cpu_ppc_decr_cb(void *opaque) cpu_ppc_decr_excp(cpu); } =20 -static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdec= r, - target_ulong value, int nr_bits) +static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, int64_t now, + target_ulong hdecr, target_ulong v= alue, + int nr_bits) { ppc_tb_t *tb_env =3D cpu->env.tb_env; =20 if (tb_env->hdecr_timer !=3D NULL) { /* HDECR (Book3S 64bit) is edge-based, not level like DECR */ - __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, + __cpu_ppc_store_decr(cpu, now, &tb_env->hdecr_next, tb_env->hdecr_= timer, tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, PPC_DECR_UNDERFLOW_TRIGGERED, hdecr, value, nr_bits); @@ -924,9 +939,12 @@ void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulon= g value) { PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + int64_t now; + target_ulong hdecr; =20 - _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, - pcc->lrg_decr_bits); + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + hdecr =3D _cpu_ppc_load_hdecr(env, now); + _cpu_ppc_store_hdecr(cpu, now, hdecr, value, pcc->lrg_decr_bits); } =20 static void cpu_ppc_hdecr_cb(void *opaque) @@ -936,12 +954,16 @@ static void cpu_ppc_hdecr_cb(void *opaque) cpu_ppc_hdecr_excp(cpu); } =20 -void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) +static void _cpu_ppc_store_purr(CPUPPCState *env, int64_t now, uint64_t va= lue) { ppc_tb_t *tb_env =3D env->tb_env; =20 - cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - &tb_env->purr_offset, value); + cpu_ppc_store_tb(tb_env, now, &tb_env->purr_offset, value); +} + +void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) +{ + _cpu_ppc_store_purr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), value); } =20 static void timebase_save(PPCTimebase *tb) --=20 2.40.1