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([2602:47:d490:6901:9454:a46f:1c22:a7c6]) by smtp.gmail.com with ESMTPSA id a5-20020a17090a740500b00262e604724dsm6306451pjg.50.2023.08.05.20.37.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Aug 2023 20:37:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691293038; x=1691897838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+ogyDL6MEqk+X9fxmfimDp67js4GEaptZ9YAfaG485E=; b=HfgWji213wDej8djNt2WWlGLTkXoU7rrxJuFVplq8NdHgJr5ehLo9wghTjEgBd5XkK OM+fzTIu0Wx+NThffBKxS3048/t03oSQr2Hq0bxfciwO2oK2DyRJo5k+/uDNliXqEOzd 6ACrwtZHlr7nAQVGlcH+N9Gs2FFQkct0IbMrDzHSzbpmcsBFRLqDIdHwwLCxZg7I1g99 IbVH3tIgKm6G/LNCInaWb94nh+GxlXhWdstrKFb0BxAFN9H7h5NSKXPX8krjM/T6FkZz O6WdKb38uCv638FLPdyd8yyij6Y84YUFMWlnEgZFuc3S3foVOghCze+hWojabYy/+0Qj 1xAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691293038; x=1691897838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+ogyDL6MEqk+X9fxmfimDp67js4GEaptZ9YAfaG485E=; b=a/oY2rKFiQ6r8jOe2eXZz3Jcev+cKkHkXnrM2r9njdDzHK7HMgh+oK/PrZL/Uhbkwf cI57W7+xCt69XS4DydKT02CByDSeHMhnz8PZDRowbiu2c9GpET6rQTJxiug3gfFjO3Od WqDZOTgX5zp5+7fn9Mcb1a9O+Erwl39cUb34SxUBfwwXf6OJk5CY+sPkxZft9lxdRUci kAnGNRpk9ys/rEnaWUdEucoQnbyNDmJZRjaBx5FERS+SB04yXaKs6Q1dmmIiuMB4wxZp bQOs36oUi/cOQYz8kBH9oYaIRNkK2y4gASBV/weV6u5PyRga01W4tE4mr39dteskAyn0 miMA== X-Gm-Message-State: AOJu0YxD6v08ud+2YhmaK/EANZQB7m4Cpq2k+NF+n1YW7pOdr9cJ0lyn SSn8BkAI1YeUBI+YnZfSBg70VAIUxXwe4Af98Mg= X-Google-Smtp-Source: AGHT+IF+2IyYmuN3xbpNERkHyuN7/ZWttO97WWoWAaLPBPQSIGTFA/lwJUTPZC/74ifuHBBp0TOlbg== X-Received: by 2002:a17:90a:1bc6:b0:267:e011:3e9a with SMTP id r6-20020a17090a1bc600b00267e0113e9amr4029993pjr.3.1691293038530; Sat, 05 Aug 2023 20:37:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 03/24] accel/tcg: Do not issue misaligned i/o Date: Sat, 5 Aug 2023 20:36:54 -0700 Message-Id: <20230806033715.244648-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230806033715.244648-1-richard.henderson@linaro.org> References: <20230806033715.244648-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1691293136894100001 In the single-page case we were issuing misaligned i/o to the memory subsystem, which does not handle it properly. Split such accesses via do_{ld,st}_mmio_*. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1800 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 118 +++++++++++++++++++++++++++------------------ 1 file changed, 72 insertions(+), 46 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a308cb7534..4b1bfaa53d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2370,16 +2370,20 @@ static uint8_t do_ld_1(CPUArchState *env, MMULookup= PageData *p, int mmu_idx, static uint16_t do_ld_2(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, MMUAccessType type, MemOp memop, uintptr_t ra) { - uint64_t ret; + uint16_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { - return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); - } - - /* Perform the load host endian, then swap if necessary. */ - ret =3D load_atom_2(env, ra, p->haddr, memop); - if (memop & MO_BSWAP) { - ret =3D bswap16(ret); + QEMU_IOTHREAD_LOCK_GUARD(); + ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 2, mmu_idx, type,= ra); + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D bswap16(ret); + } + } else { + /* Perform the load host endian, then swap if necessary. */ + ret =3D load_atom_2(env, ra, p->haddr, memop); + if (memop & MO_BSWAP) { + ret =3D bswap16(ret); + } } return ret; } @@ -2390,13 +2394,17 @@ static uint32_t do_ld_4(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, uint32_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { - return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); - } - - /* Perform the load host endian. */ - ret =3D load_atom_4(env, ra, p->haddr, memop); - if (memop & MO_BSWAP) { - ret =3D bswap32(ret); + QEMU_IOTHREAD_LOCK_GUARD(); + ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 4, mmu_idx, type,= ra); + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D bswap32(ret); + } + } else { + /* Perform the load host endian. */ + ret =3D load_atom_4(env, ra, p->haddr, memop); + if (memop & MO_BSWAP) { + ret =3D bswap32(ret); + } } return ret; } @@ -2407,13 +2415,17 @@ static uint64_t do_ld_8(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, uint64_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { - return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); - } - - /* Perform the load host endian. */ - ret =3D load_atom_8(env, ra, p->haddr, memop); - if (memop & MO_BSWAP) { - ret =3D bswap64(ret); + QEMU_IOTHREAD_LOCK_GUARD(); + ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 8, mmu_idx, type,= ra); + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D bswap64(ret); + } + } else { + /* Perform the load host endian. */ + ret =3D load_atom_8(env, ra, p->haddr, memop); + if (memop & MO_BSWAP) { + ret =3D bswap64(ret); + } } return ret; } @@ -2561,20 +2573,22 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr = addr, cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { - /* Perform the load host endian. */ if (unlikely(l.page[0].flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - a =3D io_readx(env, l.page[0].full, l.mmu_idx, addr, - ra, MMU_DATA_LOAD, MO_64); - b =3D io_readx(env, l.page[0].full, l.mmu_idx, addr + 8, - ra, MMU_DATA_LOAD, MO_64); - ret =3D int128_make128(HOST_BIG_ENDIAN ? b : a, - HOST_BIG_ENDIAN ? a : b); + a =3D do_ld_mmio_beN(env, l.page[0].full, 0, addr, 8, + l.mmu_idx, MMU_DATA_LOAD, ra); + b =3D do_ld_mmio_beN(env, l.page[0].full, 0, addr + 8, 8, + l.mmu_idx, MMU_DATA_LOAD, ra); + ret =3D int128_make128(b, a); + if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D bswap128(ret); + } } else { + /* Perform the load host endian. */ ret =3D load_atom_16(env, ra, l.page[0].haddr, l.memop); - } - if (l.memop & MO_BSWAP) { - ret =3D bswap128(ret); + if (l.memop & MO_BSWAP) { + ret =3D bswap128(ret); + } } return ret; } @@ -2874,7 +2888,11 @@ static void do_st_2(CPUArchState *env, MMULookupPage= Data *p, uint16_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { - io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); + if ((memop & MO_BSWAP) !=3D MO_LE) { + val =3D bswap16(val); + } + QEMU_IOTHREAD_LOCK_GUARD(); + do_st_mmio_leN(env, p->full, val, p->addr, 2, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2890,7 +2908,11 @@ static void do_st_4(CPUArchState *env, MMULookupPage= Data *p, uint32_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { - io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); + if ((memop & MO_BSWAP) !=3D MO_LE) { + val =3D bswap32(val); + } + QEMU_IOTHREAD_LOCK_GUARD(); + do_st_mmio_leN(env, p->full, val, p->addr, 4, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2906,7 +2928,11 @@ static void do_st_8(CPUArchState *env, MMULookupPage= Data *p, uint64_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { - io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); + if ((memop & MO_BSWAP) !=3D MO_LE) { + val =3D bswap64(val); + } + QEMU_IOTHREAD_LOCK_GUARD(); + do_st_mmio_leN(env, p->full, val, p->addr, 8, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -3029,22 +3055,22 @@ static void do_st16_mmu(CPUArchState *env, vaddr ad= dr, Int128 val, cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { - /* Swap to host endian if necessary, then store. */ - if (l.memop & MO_BSWAP) { - val =3D bswap128(val); - } if (unlikely(l.page[0].flags & TLB_MMIO)) { - QEMU_IOTHREAD_LOCK_GUARD(); - if (HOST_BIG_ENDIAN) { - b =3D int128_getlo(val), a =3D int128_gethi(val); - } else { - a =3D int128_getlo(val), b =3D int128_gethi(val); + if ((l.memop & MO_BSWAP) !=3D MO_LE) { + val =3D bswap128(val); } - io_writex(env, l.page[0].full, l.mmu_idx, a, addr, ra, MO_64); - io_writex(env, l.page[0].full, l.mmu_idx, b, addr + 8, ra, MO_= 64); + a =3D int128_getlo(val); + b =3D int128_gethi(val); + QEMU_IOTHREAD_LOCK_GUARD(); + do_st_mmio_leN(env, l.page[0].full, a, addr, 8, l.mmu_idx, ra); + do_st_mmio_leN(env, l.page[0].full, b, addr + 8, 8, l.mmu_idx,= ra); } else if (unlikely(l.page[0].flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { + /* Swap to host endian if necessary, then store. */ + if (l.memop & MO_BSWAP) { + val =3D bswap128(val); + } store_atom_16(env, ra, l.page[0].haddr, l.memop, val); } return; --=20 2.34.1