From nobody Sat May 18 15:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1691162035; cv=none; d=zohomail.com; s=zohoarc; b=mN4CmcG7K6hueq2HNLpHcC4+nB4m/Nc2QB2CsfBO4zY8VJFPsIYCloB9aPeGxxTT8CiX3/XYI58UZJq8SseuQPlLMUzGlm9pXC0Cu5K4e1IM7Y0sI+3CpeLg7JgWpGSst+hDAHu4WowV01FmtDufnCV9Ov+y4TIqEy8at/Tu3o4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1691162035; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=GCVl8zUDpczZnc+TFfUIxMXu3DiI2oN6XNnU4nWDf5I=; b=hoQATBTL+mg5agO5GqYDB4sA8aqb+GrkOpxIKYwqufW5VtoPIUPtjy3Ba2e8AGNlBFq23yvYD9x0W2+bR5N0JCgkv/pOimun9WWUNdmyX36Mmbz7b/f8ZquSRChVxBOJDWAtkNltRGNS4FF5O4JMs814gTGWtXWlGFTj1JBnajA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1691162035888302.86446866616166; Fri, 4 Aug 2023 08:13:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qRwUo-0007WH-Sa; Fri, 04 Aug 2023 11:13:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qRpv4-00069V-Cy; Fri, 04 Aug 2023 04:12:22 -0400 Received: from [2401:b180:8000:2:9109:19ec:a055:9652] (helo=B-L8MBMD6R-2342.local) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qRpv1-0002sj-3F; Fri, 04 Aug 2023 04:12:22 -0400 Received: by B-L8MBMD6R-2342.local (Postfix, from userid 502) id A63C7343C41; Fri, 4 Aug 2023 15:50:54 +0800 (CST) To: qemu-devel@nongnu.org Cc: =?UTF-8?q?=E4=BA=8E=E8=88=AA?= <1339236493@qq.com>, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org (open list:ASPEED BMCs) Subject: [PATCH] Aspeed: i2c: Fixed Tx and Rx error in BUFF Mode Date: Fri, 4 Aug 2023 15:50:42 +0800 Message-Id: <20230804075042.51204-1-1339236493@qq.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2401:b180:8000:2:9109:19ec:a055:9652 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2401:b180:8000:2:9109:19ec:a055:9652; envelope-from=francisyuu@B-L8MBMD6R-2342.local; helo=B-L8MBMD6R-2342.local X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NO_DNS_FOR_FROM=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, SPOOFED_FREEMAIL=0.001, SPOOFED_FREEMAIL_NO_RDNS=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 04 Aug 2023 11:13:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?UTF-8?q?=E4=BA=8E=E8=88=AA?= <1339236493@qq.com> From: =?UTF-8?q?=E4=BA=8E=E8=88=AA?= via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1691162038455100003 1. Fixed inconsistency between the bit field definition in register I2CD_POOL_CTRL and the ast2600 datasheet 2. Fixed issue of confusing RXSIZE and RXCOUNT, as well as forgetting to add one to TXCOUNT and RXSIZE in buff mode 3. Fixed issue with TXBUF transmission start position error in buff mode 4. Added support for the BUFFER ORGANIZATION option in reg I2CC_POOL_CTRL After adding these changes, QEMU can support driver code: https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v5.15 /drivers/i2c/busses/i2c-ast2600.c Signed-off-by:=E4=BA=8E=E8=88=AA<1339236493@qq.com> --- hw/i2c/aspeed_i2c.c | 21 ++++++--------------- include/hw/i2c/aspeed_i2c.h | 5 +++-- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 1f071a3811..0e380d0bba 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -236,7 +236,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8= _t pool_start) uint32_t reg_byte_buf =3D aspeed_i2c_bus_byte_buf_offset(bus); uint32_t reg_dma_len =3D aspeed_i2c_bus_dma_len_offset(bus); int pool_tx_count =3D SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, - TX_COUNT); + TX_COUNT)+1; =20 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { for (i =3D pool_start; i < pool_tx_count; i++) { @@ -293,10 +293,12 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) uint32_t reg_dma_len =3D aspeed_i2c_bus_dma_len_offset(bus); uint32_t reg_dma_addr =3D aspeed_i2c_bus_dma_addr_offset(bus); int pool_rx_count =3D SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, - RX_COUNT); + RX_SIZE)+1; =20 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { - uint8_t *pool_base =3D aic->bus_pool_base(bus); + uint8_t *pool_base ; + if(ARRAY_FIELD_EX32(bus->regs,I2CC_POOL_CTRL,BUF_ORGANIZATION))poo= l_base=3Daic->bus_pool_base(bus)+16; + else pool_base=3D aic->bus_pool_base(bus); =20 for (i =3D 0; i < pool_rx_count; i++) { pool_base[i] =3D i2c_recv(bus->bus); @@ -418,7 +420,7 @@ static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) uint32_t reg_intr_sts =3D aspeed_i2c_bus_intr_sts_offset(bus); uint32_t reg_dma_len =3D aspeed_i2c_bus_dma_len_offset(bus); if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { - count =3D SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COU= NT); + count =3D SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COU= NT)+1; } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { count =3D bus->regs[reg_dma_len]; } else { /* BYTE mode */ @@ -449,7 +451,6 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus= , uint64_t value) uint8_t pool_start =3D 0; uint32_t reg_intr_sts =3D aspeed_i2c_bus_intr_sts_offset(bus); uint32_t reg_cmd =3D aspeed_i2c_bus_cmd_offset(bus); - uint32_t reg_pool_ctrl =3D aspeed_i2c_bus_pool_ctrl_offset(bus); uint32_t reg_dma_len =3D aspeed_i2c_bus_dma_len_offset(bus); =20 if (!aspeed_i2c_check_sram(bus)) { @@ -489,16 +490,6 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bu= s, uint64_t value) * else needs to be sent in this sequence. */ if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { - if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) - =3D=3D 1) { - SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); - } else { - /* - * Increase the start index in the TX pool buffer to - * skip the address byte. - */ - pool_start++; - } } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN))= { if (bus->regs[reg_dma_len] =3D=3D 0) { SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 51c944efea..88b144a599 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -139,9 +139,9 @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */ REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */ SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7) REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */ - SHARED_FIELD(RX_COUNT, 24, 5) + SHARED_FIELD(RX_COUNT, 24, 6) SHARED_FIELD(RX_SIZE, 16, 5) - SHARED_FIELD(TX_COUNT, 9, 5) + SHARED_FIELD(TX_COUNT, 8, 5) FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */ REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */ SHARED_FIELD(RX_BUF, 8, 8) @@ -162,6 +162,7 @@ REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08) /* 15:0 shared with I2CD_BYTE_BUF[15:0] */ REG32(I2CC_POOL_CTRL, 0x0c) /* 31:0 shared with I2CD_POOL_CTRL[31:0] */ + FIELD(I2CC_POOL_CTRL, BUF_ORGANIZATION, 0, 1) /* AST2600 */ REG32(I2CM_INTR_CTRL, 0x10) REG32(I2CM_INTR_STS, 0x14) FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4) --=20 2.39.2 (Apple Git-143)