From nobody Sat May 18 16:46:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1691068538244782.1029921778211; Thu, 3 Aug 2023 06:15:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qRYAL-0000bH-3b; Thu, 03 Aug 2023 09:14:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qRYAI-0000ae-J1; Thu, 03 Aug 2023 09:14:54 -0400 Received: from mailfish.xiph.org ([2001:470:eb26:42:5054:ff:fe09:a40c]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qRYAG-0007Cl-GR; Thu, 03 Aug 2023 09:14:54 -0400 Received: from localhost.localdomain (c-24-126-94-29.hsd1.wv.comcast.net [24.126.94.29]) by mailfish.xiph.org (Postfix) with ESMTPSA id 4E6D69F86E; Thu, 3 Aug 2023 13:14:46 +0000 (UTC) From: Nathan Egge To: Palmer Dabbelt , Alistair Francis , Bin Meng Cc: Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, "Nathan Egge" Subject: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V Date: Thu, 3 Aug 2023 09:14:24 -0400 Message-Id: <20230803131424.40744-1-negge@xiph.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:470:eb26:42:5054:ff:fe09:a40c; envelope-from=negge@xiph.org; helo=mailfish.xiph.org X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1691068586969100001 Content-Type: text/plain; charset="utf-8" From: "Nathan Egge" Set V bit for hwcap if misa is set. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 Signed-off-by: Nathan Egge Reviewed-by: Daniel Henrique Barboza Tested-by: Daniel Henrique Barboza --- linux-user/elfload.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 861ec07abc..a299ba7300 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) #define MISA_BIT(EXT) (1 << (EXT - 'A')) RISCVCPU *cpu =3D RISCV_CPU(thread_cpu); uint32_t mask =3D MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') + | MISA_BIT('V'); =20 return cpu->env.misa_ext & mask; #undef MISA_BIT --=20 2.35.1