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a=rsa-sha256; c=simple/simple; d=keithp.com; s=mail; t=1691034753; bh=+PFad+rM1gQuZ2QRDjMzKlcU/a7QQVLGQStbX01gdOY=; h=From:To:Cc:Subject:Date:From; b=ZmJrPBaBhKTnZLvrv6RKYCvfnUhyZ8HRsXgOfbFlx44I41WmMYu120iiO6GmuCS0N Iv6ValJCdDhXUxG8br1lkyNdf9fhJBiKwxPAzmTak1CjzJmhReIW8tdif9ereLJyIp 1ua0c4gvWvWDwyiXfUK2YYBT8vSl5/SAbv9eDA9roJTHyOCqp4sg41N5cwpoABl017 dM6nbVHazTTUsWxeItSmUAR6Oom1x8D7/jWNCXd+ypJb1as6VhRdXt8lHuCSE16tto Nqzi/BrcOfGFHr3XeqslVvtQ6o8jCgKiXNaR3JNANOR+KUgfFENtbA7Tamcgx8j7Ue ZourD34ecco+Q== To: qemu-devel@nongnu.org Cc: Laurent Vivier , Keith Packard Subject: [PATCH] target/m68k: Map FPU exceptions to FPSR register Date: Wed, 2 Aug 2023 20:52:31 -0700 Message-Id: <20230803035231.429697-1-keithp@keithp.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.227.221.253; envelope-from=keithp@keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Keith Packard From: Keith Packard via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZM-MESSAGEID: 1691034810879100001 Content-Type: text/plain; charset="utf-8" Add helpers for reading/writing the 68881 FPSR register so that changes in floating point exception state can be seen by the application. Call these helpers in pre_load/post_load hooks to synchronize exception state. Signed-off-by: Keith Packard Reviewed-by: Richard Henderson --- target/m68k/cpu.c | 12 +++++++ target/m68k/cpu.h | 2 ++ target/m68k/fpu_helper.c | 72 ++++++++++++++++++++++++++++++++++++++++ target/m68k/helper.c | 4 +-- target/m68k/helper.h | 2 ++ target/m68k/translate.c | 4 +-- 6 files changed, 92 insertions(+), 4 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 70d58471dc..a0e9b723a5 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -404,12 +404,23 @@ static const VMStateDescription vmstate_freg =3D { } }; =20 +static int fpu_pre_load(void *opaque) +{ + M68kCPU *s =3D opaque; + + s->env.fpsr =3D cpu_m68k_get_fpsr(&s->env); + + return 0; +} + static int fpu_post_load(void *opaque, int version) { M68kCPU *s =3D opaque; =20 cpu_m68k_restore_fp_status(&s->env); =20 + cpu_m68k_set_fpsr(&s->env, s->env.fpsr); + return 0; } =20 @@ -418,6 +429,7 @@ const VMStateDescription vmmstate_fpu =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D fpu_needed, + .pre_load =3D fpu_pre_load, .post_load =3D fpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.fpcr, M68kCPU), diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b741c50a8f..1e491fda77 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -173,6 +173,8 @@ struct ArchCPU { CPUM68KState env; }; =20 +uint32_t cpu_m68k_get_fpsr(CPUM68KState *env); +void cpu_m68k_set_fpsr(CPUM68KState *env, uint32_t val); =20 #ifndef CONFIG_USER_ONLY void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index ab120b5f59..8314791f50 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -164,6 +164,78 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val) cpu_m68k_set_fpcr(env, val); } =20 +/* Convert host exception flags to cpu_m68k form. */ +static int cpu_m68k_exceptbits_from_host(int host_bits) +{ + int target_bits =3D 0; + + if (host_bits & float_flag_invalid) { + target_bits |=3D 0x80; + } + if (host_bits & float_flag_overflow) { + target_bits |=3D 0x40; + } + if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { + target_bits |=3D 0x20; + } + if (host_bits & float_flag_divbyzero) { + target_bits |=3D 0x10; + } + if (host_bits & float_flag_inexact) { + target_bits |=3D 0x08; + } + return target_bits; +} + +/* Convert cpu_m68k exception flags to target form. */ +static int cpu_m68k_exceptbits_to_host(int target_bits) +{ + int host_bits =3D 0; + + if (target_bits & 0x80) { + host_bits |=3D float_flag_invalid; + } + if (target_bits & 0x40) { + host_bits |=3D float_flag_overflow; + } + if (target_bits & 0x20) { + host_bits |=3D float_flag_underflow; + } + if (target_bits & 0x10) { + host_bits |=3D float_flag_divbyzero; + } + if (target_bits & 0x08) { + host_bits |=3D float_flag_inexact; + } + return host_bits; +} + +uint32_t cpu_m68k_get_fpsr(CPUM68KState *env) +{ + int host_flags =3D get_float_exception_flags(&env->fp_status); + int target_flags =3D cpu_m68k_exceptbits_from_host(host_flags); + int except =3D (env->fpsr & ~(0xf8)) | target_flags; + return except; +} + +uint32_t HELPER(get_fpsr)(CPUM68KState *env) +{ + return cpu_m68k_get_fpsr(env); +} + +void cpu_m68k_set_fpsr(CPUM68KState *env, uint32_t val) +{ + env->fpsr =3D val; + + int host_flags =3D cpu_m68k_exceptbits_to_host((int) env->fpsr); + set_float_exception_flags(host_flags, &env->fp_status); +} + +void HELPER(set_fpsr)(CPUM68KState *env, uint32_t val) +{ + cpu_m68k_set_fpsr(env, val); +} + #define PREC_BEGIN(prec) \ do { \ FloatX80RoundPrec old =3D \ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 0a1544cd68..beab4b96bc 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -118,7 +118,7 @@ static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByt= eArray *mem_buf, int n) case 8: /* fpcontrol */ return gdb_get_reg32(mem_buf, env->fpcr); case 9: /* fpstatus */ - return gdb_get_reg32(mem_buf, env->fpsr); + return gdb_get_reg32(mem_buf, cpu_m68k_get_fpsr(env)); case 10: /* fpiar, not implemented */ return gdb_get_reg32(mem_buf, 0); } @@ -137,7 +137,7 @@ static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint= 8_t *mem_buf, int n) cpu_m68k_set_fpcr(env, ldl_p(mem_buf)); return 4; case 9: /* fpstatus */ - env->fpsr =3D ldl_p(mem_buf); + cpu_m68k_set_fpsr(env, ldl_p(mem_buf)); return 4; case 10: /* fpiar, not implemented */ return 4; diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 2bbe0dc032..95aa5e53bb 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -54,6 +54,8 @@ DEF_HELPER_4(fsdiv, void, env, fp, fp, fp) DEF_HELPER_4(fddiv, void, env, fp, fp, fp) DEF_HELPER_4(fsgldiv, void, env, fp, fp, fp) DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_RWG, void, env, fp, fp) +DEF_HELPER_2(set_fpsr, void, env, i32) +DEF_HELPER_1(get_fpsr, i32, env) DEF_HELPER_FLAGS_2(set_fpcr, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(ftst, TCG_CALL_NO_RWG, void, env, fp) DEF_HELPER_3(fconst, void, env, fp, i32) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d037c57453..360d054162 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4718,7 +4718,7 @@ static void gen_load_fcr(DisasContext *s, TCGv res, i= nt reg) tcg_gen_movi_i32(res, 0); break; case M68K_FPSR: - tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr)); + gen_helper_get_fpsr(res, cpu_env); break; case M68K_FPCR: tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr)); @@ -4732,7 +4732,7 @@ static void gen_store_fcr(DisasContext *s, TCGv val, = int reg) case M68K_FPIAR: break; case M68K_FPSR: - tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr)); + gen_helper_set_fpsr(cpu_env, val); break; case M68K_FPCR: gen_helper_set_fpcr(cpu_env, val); --=20 2.40.1