From nobody Sun May 19 10:01:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=deller@gmx.de; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmx.de ARC-Seal: i=1; a=rsa-sha256; t=1690917081; cv=none; d=zohomail.com; s=zohoarc; b=GpRZ5O30yP1U6nJtJLN3TEjnQcvv6m+B5YJ76YnlcQfehbYQtHIFblccog3O+VKQ3LFdSpiSjWULfVtGgQ9t4kENc8VTdaNR+WRmcVfvedPY811x/FkXXKsHcYGrz8+xt5JCka/X1aQu5gBs8hCGABC8Fq0h2CR7wsFfkD6iieg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690917081; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dN/dgMhkDgLJha2j6RXZjsw1lBwj+7VI/5m1maWpPpY=; b=PFHaS+h9HZ/RUduVgnJ7kUSFTfeh+c/5TQTfcJJGx4+bdO214/OjUa7Yl8JNisJUclV+31xVixpGqWW/dYq5S59MUup2fkMG5q8DU30La1eV3C9/kOmSk0AIfH+DlKOWcjcXBTP4MILmxp+NwlLf+yvKN/k5Tx1ZpwDKRh7/Th4= ARC-Authentication-Results: i=1; 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Tue, 01 Aug 2023 21:10:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.de; s=s31663417; t=1690917037; x=1691521837; i=deller@gmx.de; bh=x2WCk90r3kqILwUNojPe8GNq/6l5cw5ovlA7R/f2IzU=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=HLG7KUrUOlX6EiLTny+/V2iKCPTxX6+xBNTs8pReTpdkkWOx9n/0p9tkTGOQN9lvNpXLrtd ZWx7+5cFbtNhpVheG0JPcH2YlX3v6qtwQkgLxG8BBBlALg9CuJoa3b1jLb2RO7DwPbaVLHSzf /kTwlD2x2Xjk6amOxV1gFclJnr9LKXl3lvprLv8SfoJLiZ6mx+yW50DPPnW4mH4eqJyn5bqKZ JqePzIxrWqKEXORcQ6bfZUleMqPmBgcwIpSDTnMpEQT8rik6i9TbMvXNz9vIwTduyiYyBtGiY XXR59nVTGz4Yo/TrLmdjBEyIaMD78gkW92Da/G+SkNw0qyc3Mmww== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a From: Helge Deller To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , Laurent Vivier , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , qemu-arm@nongnu.org, Helge Deller Subject: [PATCH 1/2] linux-user: Fix openat() emulation to correctly detect accesses to /proc Date: Tue, 1 Aug 2023 21:10:34 +0200 Message-ID: <20230801191035.374120-2-deller@gmx.de> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801191035.374120-1-deller@gmx.de> References: <20230801191035.374120-1-deller@gmx.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:t2Qxvy/8uIfWsppEqM5abCnaRoULrkykz2ZZeXCLGXfQJOOPBAP J27DaF0PPCWxDac6ygd3ozCHVLG5VyovwcyXD5SOyPxkXT9/KQedMBvsIr3666V1ljzzSP+ UK4plnoZgiQGmOvv6amqPweeqYQBGnHxUpxLFd+/G9P3mu72AAM7Rt31tLwuFj0Ppq/FelH /aFyBLFlbACObr4uJw3/w== UI-OutboundReport: notjunk:1;M01:P0:zBl5iumgsRU=;vRj4BaMYLi2Ah55QRXZv1dNAIYC MeDzHyAVn0i/6xLMETkxIbIPAKMEezsex/L9BnYGl9ALQvn6lxl968TFm0dHu3iyj0ZRsohk/ Gk4VJr2D9+pRfPNAwj5IulZ2OJmm4pxVlr1EweSdF1DtPOdSfWfiK1vDprkt6bwMxFtV8qvel UFqHLU7keLrhW4tTFncKvb8q0DNqIbrzESDyUUM6xbP/xVYRuWZsaIoAkUxb+4V6g0N6bFeeP azonhVqN9oF0HUliOprdxvTGRRtl8D/9qVhmWTzpBwLwo501VYcsKiBvzgAUphsXJE6KMbDhx TMjvbmRUEDPpgt8/p1f2khIVLdZLyxI6HKzlQV3hWqiPQsJRRkuMWdM+Kp3G1sB4emj9JEyZK cUqTVpxuVycwhFv7/6XsnuyCgYjXxXL31ly5fyBTSqzxQX2iP7HQwGvqhBEpelbRyPoOBx+23 eGFmC7M59id9B8TkIH+yLVYvhpk3TUMZGLSyl6r1dVpfBfWLhCjVCc77h+dLpQr6u4bHujCGb anZm6J8uoZjNY9EFg6mmoYdeTjqvBhLqS9dpaNB3nLnNC6rjBdnRdCqG5FBO1HIEe6y5K97U3 2cxptu6zO6HLqrMUEbfeIhzC556AtdcbrPMz5Grj62LBCa/tOzCallnHRFXh1cDAVSr0dc8da if0chTETwORqRN2NB+1zb1Wgn85oxXYgE8E/xQsy6Qc46Ny5iLMeip78xqcDkPazcgfvQKW/q OVsDjozgab5gNbYqFJ9LNaCuGJ4CcQV6bJCEoZzHPaklNlL0GvujeDVikTgGZcbD+szZKQMi0 PpovMEoA8yIJnrNq6YTQMpo78rfrvmzVoM2qJFr8zGwLUfTfKW1vE4DR/lNtr220BbT8nQWSi mi2DW3SNioPDXhGXcvSsM3gBcRnysZSd/VeIISyeEnAcg//bSbAHCJkBrRdO8kPElt/z4rTQF HedYIIlznfIkZqeuAMZeETt6x5k= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.227.17.22; envelope-from=deller@gmx.de; helo=mout.gmx.net X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity deller@gmx.de) X-ZM-MESSAGEID: 1690917083638100006 Content-Type: text/plain; charset="utf-8" In qemu we catch accesses to files like /proc/cpuinfo or /proc/net/route and return to the guest contents which would be visible on a real system (instead what the host would show). This patch fixes a bug, where for example the accesses cat /proc////cpuinfo or cd /proc && cat cpuinfo will not be recognized by qemu and where qemu will wrongly show the contents of the host's /proc/cpuinfo file. Signed-off-by: Helge Deller -- v2: - use g_autofree instead of pathname on stack Daniel P. Berrang=C3=A9 requested to not put buffers on stack. Using g_autofree keeps code much cleaner than using extended semantics of realpath(), unless I can use g_autofree on malloced area from realpath(). --- linux-user/syscall.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 95727a816a..a089463969 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8539,9 +8539,12 @@ static int open_hardware(CPUArchState *cpu_env, int = fd) } #endif -int do_guest_openat(CPUArchState *cpu_env, int dirfd, const char *pathname, + +int do_guest_openat(CPUArchState *cpu_env, int dirfd, const char *fname, int flags, mode_t mode, bool safe) { + g_autofree char *proc_name =3D g_new(char, PATH_MAX); + const char *pathname; struct fake_open { const char *filename; int (*fill)(CPUArchState *cpu_env, int fd); @@ -8567,6 +8570,13 @@ int do_guest_openat(CPUArchState *cpu_env, int dirfd= , const char *pathname, { NULL, NULL, NULL } }; + /* if this is a file from /proc/ filesystem, expand full name */ + if (realpath(fname, proc_name) && strncmp(proc_name, "/proc/", 6) =3D= =3D 0) { + pathname =3D proc_name; + } else { + pathname =3D fname; + } + if (is_proc_myself(pathname, "exe")) { if (safe) { return safe_openat(dirfd, exec_path, flags, mode); -- 2.41.0 From nobody Sun May 19 10:01:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=deller@gmx.de; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmx.de ARC-Seal: i=1; a=rsa-sha256; t=1690917084; cv=none; d=zohomail.com; s=zohoarc; b=hlsRPerNzAC79vNQL0t0lRBToFXBnwTJnxk6eHoSSs1IXXJRPbzE7UI48V33r86ReI41Wu0f9SX2kmqewV7JCh5VqsbRqVI8OHsIz+DFhKsNHlNG2YAvseRrj5X57OuXcFJelzTdyRQQej60Y3X4lyczeKKvpwV5ee+SDQVbfiM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690917084; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.227.17.21; envelope-from=deller@gmx.de; helo=mout.gmx.net X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity deller@gmx.de) X-ZM-MESSAGEID: 1690917085097100009 Content-Type: text/plain; charset="utf-8" Add emulation for /proc/cpuinfo for arm architecture. The output below mimics output as seen on debian porterboxes. aarch64 output example: processor : 0 BogoMIPS : 100.00 Features : fp asimd aes pmull sha1 sha2 crc32 atomics fphp asimdhp c= puid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdf= hm ilrcpc flagm sb paca pacg dcpodp sve2 sveaes svepmull svebitperm svesha3= svesm4 flagm2 frint svei8mm svef32mm svef64mm svebf16 i8mm bf16 rng bti mt= e sme sme_i16i64 sme_f64f64 sme_i8i32 sme_f16f32 sme_b16f32 sme_f32f32 sme_= fa64 CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x0 CPU revision : 1 arm output example: processor : 0 model name : ARMv7 Processor rev 2 (v7l) BogoMIPS : 50.00 Features : swp half thumb fast_mult vfp edsp neon vfpv3 tls vfpv4 id= iva idivt vfpd32 lpae aes pmull sha1 sha2 crc32 CPU implementer : 0x56 CPU architecture: 7 CPU variant : 0x2 CPU part : 0x584 CPU revision : 2 Hardware : Marvell Armada 370/XP (Device Tree) Revision : 0000 Serial : 0000000000000000 Signed-off-by: Helge Deller v2: - show features of CPU which is actually being emulated by qemu (suggested by Peter Maydell) --- linux-user/elfload.c | 130 +++++++++++++++++++++++++++++++++++++++++-- linux-user/loader.h | 6 +- linux-user/syscall.c | 58 ++++++++++++++++++- 3 files changed, 187 insertions(+), 7 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 861ec07abc..99804e477d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static bool init_guest_commpage(void) #define ELF_HWCAP get_elf_hwcap() #define ELF_HWCAP2 get_elf_hwcap2() -static uint32_t get_elf_hwcap(void) +uint32_t get_elf_hwcap(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -508,7 +508,7 @@ static uint32_t get_elf_hwcap(void) return hwcaps; } -static uint32_t get_elf_hwcap2(void) +uint32_t get_elf_hwcap2(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -521,6 +521,49 @@ static uint32_t get_elf_hwcap2(void) return hwcaps; } +const char *elf_hwcap_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP_ARM_SWP )] =3D "swp", + [__builtin_ctz(ARM_HWCAP_ARM_HALF )] =3D "half", + [__builtin_ctz(ARM_HWCAP_ARM_THUMB )] =3D "thumb", + [__builtin_ctz(ARM_HWCAP_ARM_26BIT )] =3D "26bit", + [__builtin_ctz(ARM_HWCAP_ARM_FAST_MULT)] =3D "fast_mult", + [__builtin_ctz(ARM_HWCAP_ARM_FPA )] =3D "fpa", + [__builtin_ctz(ARM_HWCAP_ARM_VFP )] =3D "vfp", + [__builtin_ctz(ARM_HWCAP_ARM_EDSP )] =3D "edsp", + [__builtin_ctz(ARM_HWCAP_ARM_JAVA )] =3D "java", + [__builtin_ctz(ARM_HWCAP_ARM_IWMMXT )] =3D "iwmmxt", + [__builtin_ctz(ARM_HWCAP_ARM_CRUNCH )] =3D "crunch", + [__builtin_ctz(ARM_HWCAP_ARM_THUMBEE )] =3D "thumbee", + [__builtin_ctz(ARM_HWCAP_ARM_NEON )] =3D "neon", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3 )] =3D "vfpv3", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3D16 )] =3D "vfpv3d16", + [__builtin_ctz(ARM_HWCAP_ARM_TLS )] =3D "tls", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv4 )] =3D "vfpv4", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVA )] =3D "idiva", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVT )] =3D "idivt", + [__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] =3D "vfpd32", + [__builtin_ctz(ARM_HWCAP_ARM_LPAE )] =3D "lpae", + [__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] =3D "evtstrm", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP2_ARM_AES )] =3D "aes", + [__builtin_ctz(ARM_HWCAP2_ARM_PMULL)] =3D "pmull", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] =3D "sha1", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] =3D "sha2", + [__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] =3D "crc32", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + #undef GET_FEATURE #undef GET_FEATURE_ID @@ -668,7 +711,7 @@ enum { #define GET_FEATURE_ID(feat, hwcap) \ do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) -static uint32_t get_elf_hwcap(void) +uint32_t get_elf_hwcap(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -706,7 +749,7 @@ static uint32_t get_elf_hwcap(void) return hwcaps; } -static uint32_t get_elf_hwcap2(void) +uint32_t get_elf_hwcap2(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -741,6 +784,85 @@ static uint32_t get_elf_hwcap2(void) return hwcaps; } +const char *elf_hwcap_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP_A64_FP )] =3D "fp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMD )] =3D "asimd", + [__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] =3D "evtstrm", + [__builtin_ctz(ARM_HWCAP_A64_AES )] =3D "aes", + [__builtin_ctz(ARM_HWCAP_A64_PMULL )] =3D "pmull", + [__builtin_ctz(ARM_HWCAP_A64_SHA1 )] =3D "sha1", + [__builtin_ctz(ARM_HWCAP_A64_SHA2 )] =3D "sha2", + [__builtin_ctz(ARM_HWCAP_A64_CRC32 )] =3D "crc32", + [__builtin_ctz(ARM_HWCAP_A64_ATOMICS )] =3D "atomics", + [__builtin_ctz(ARM_HWCAP_A64_FPHP )] =3D "fphp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDHP )] =3D "asimdhp", + [__builtin_ctz(ARM_HWCAP_A64_CPUID )] =3D "cpuid", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDRDM)] =3D "asimdrdm", + [__builtin_ctz(ARM_HWCAP_A64_JSCVT )] =3D "jscvt", + [__builtin_ctz(ARM_HWCAP_A64_FCMA )] =3D "fcma", + [__builtin_ctz(ARM_HWCAP_A64_LRCPC )] =3D "lrcpc", + [__builtin_ctz(ARM_HWCAP_A64_DCPOP )] =3D "dcpop", + [__builtin_ctz(ARM_HWCAP_A64_SHA3 )] =3D "sha3", + [__builtin_ctz(ARM_HWCAP_A64_SM3 )] =3D "sm3", + [__builtin_ctz(ARM_HWCAP_A64_SM4 )] =3D "sm4", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDDP )] =3D "asimddp", + [__builtin_ctz(ARM_HWCAP_A64_SHA512 )] =3D "sha512", + [__builtin_ctz(ARM_HWCAP_A64_SVE )] =3D "sve", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDFHM)] =3D "asimdfhm", + [__builtin_ctz(ARM_HWCAP_A64_DIT )] =3D "dit", + [__builtin_ctz(ARM_HWCAP_A64_USCAT )] =3D "uscat", + [__builtin_ctz(ARM_HWCAP_A64_ILRCPC )] =3D "ilrcpc", + [__builtin_ctz(ARM_HWCAP_A64_FLAGM )] =3D "flagm", + [__builtin_ctz(ARM_HWCAP_A64_SSBS )] =3D "ssbs", + [__builtin_ctz(ARM_HWCAP_A64_SB )] =3D "sb", + [__builtin_ctz(ARM_HWCAP_A64_PACA )] =3D "paca", + [__builtin_ctz(ARM_HWCAP_A64_PACG )] =3D "pacg", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] =3D "dcpodp", + [__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] =3D "sve2", + [__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] =3D "sveaes", + [__builtin_ctz(ARM_HWCAP2_A64_SVEPMULL )] =3D "svepmull", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBITPERM )] =3D "svebitperm", + [__builtin_ctz(ARM_HWCAP2_A64_SVESHA3 )] =3D "svesha3", + [__builtin_ctz(ARM_HWCAP2_A64_SVESM4 )] =3D "svesm4", + [__builtin_ctz(ARM_HWCAP2_A64_FLAGM2 )] =3D "flagm2", + [__builtin_ctz(ARM_HWCAP2_A64_FRINT )] =3D "frint", + [__builtin_ctz(ARM_HWCAP2_A64_SVEI8MM )] =3D "svei8mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF32MM )] =3D "svef32mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF64MM )] =3D "svef64mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBF16 )] =3D "svebf16", + [__builtin_ctz(ARM_HWCAP2_A64_I8MM )] =3D "i8mm", + [__builtin_ctz(ARM_HWCAP2_A64_BF16 )] =3D "bf16", + [__builtin_ctz(ARM_HWCAP2_A64_DGH )] =3D "dgh", + [__builtin_ctz(ARM_HWCAP2_A64_RNG )] =3D "rng", + [__builtin_ctz(ARM_HWCAP2_A64_BTI )] =3D "bti", + [__builtin_ctz(ARM_HWCAP2_A64_MTE )] =3D "mte", + [__builtin_ctz(ARM_HWCAP2_A64_ECV )] =3D "ecv", + [__builtin_ctz(ARM_HWCAP2_A64_AFP )] =3D "afp", + [__builtin_ctz(ARM_HWCAP2_A64_RPRES )] =3D "rpres", + [__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] =3D "mte3", + [__builtin_ctz(ARM_HWCAP2_A64_SME )] =3D "sme", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] =3D "sme_i16i64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] =3D "sme_f64f64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] =3D "sme_i8i32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] =3D "sme_f16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] =3D "sme_b16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] =3D "sme_f32f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] =3D "sme_fa64", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + #undef GET_FEATURE_ID #endif /* not TARGET_AARCH64 */ diff --git a/linux-user/loader.h b/linux-user/loader.h index 59cbeacf24..324e5c872a 100644 --- a/linux-user/loader.h +++ b/linux-user/loader.h @@ -56,9 +56,13 @@ abi_long memcpy_to_target(abi_ulong dest, const void *sr= c, extern unsigned long guest_stack_size; -#ifdef TARGET_S390X +#if defined(TARGET_S390X) || defined(TARGET_AARCH64) || defined(TARGET_ARM) uint32_t get_elf_hwcap(void); const char *elf_hwcap_str(uint32_t bit); #endif +#if defined(TARGET_AARCH64) || defined(TARGET_ARM) +uint32_t get_elf_hwcap2(void); +const char *elf_hwcap2_str(uint32_t bit); +#endif #endif /* LINUX_USER_LOADER_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a089463969..8d11c459cc 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8323,7 +8323,8 @@ void target_exception_dump(CPUArchState *env, const c= har *fmt, int code) #if HOST_BIG_ENDIAN !=3D TARGET_BIG_ENDIAN || \ defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) = || \ - defined(TARGET_RISCV) || defined(TARGET_S390X) + defined(TARGET_RISCV) || defined(TARGET_S390X) || defined(TARGET_ARM) = || \ + defined(TARGET_AARCH64) static int is_proc(const char *filename, const char *entry) { return strcmp(filename, entry) =3D=3D 0; @@ -8539,6 +8540,58 @@ static int open_hardware(CPUArchState *cpu_env, int = fd) } #endif +#if defined(TARGET_AARCH64) || defined(TARGET_ARM) +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + const int is64 =3D TARGET_ABI_BITS =3D=3D 64; + uint32_t elf_hwcap =3D get_elf_hwcap(); + uint32_t elf_hwcap2 =3D get_elf_hwcap2(); + const char *hwcap_str; + int i, j, num_cpus; + + num_cpus =3D sysconf(_SC_NPROCESSORS_ONLN); + for (i =3D 0; i < num_cpus; i++) { + dprintf(fd, "processor\t: %d\n", i); + if (!is64) { + dprintf(fd, "model name\t: ARMv7 Processor rev 2 (v7l)\n"); + } + dprintf(fd, "BogoMIPS\t: %d.00\n", is64 ? 100 : 50); + dprintf(fd, "Features\t:"); + for (j =3D 0; j < sizeof(elf_hwcap) * 8; j++) { + if (!(elf_hwcap & (1 << j))) { + continue; + } + hwcap_str =3D elf_hwcap_str(j); + if (hwcap_str) { + dprintf(fd, " %s", hwcap_str); + } + } + for (j =3D 0; j < sizeof(elf_hwcap2) * 8; j++) { + if (!(elf_hwcap2 & (1 << j))) { + continue; + } + hwcap_str =3D elf_hwcap2_str(j); + if (hwcap_str) { + dprintf(fd, " %s", hwcap_str); + } + } + dprintf(fd, "\n"); + dprintf(fd, "CPU implementer\t: 0x%d\n", is64 ? 50 : 56); + dprintf(fd, "CPU architecture: %d\n", is64 ? 8 : 7); + dprintf(fd, "CPU variant\t: 0x%d\n", is64 ? 0 : 2); + dprintf(fd, "CPU part\t: 0x%d\n", is64 ? 0 : 584); + dprintf(fd, "CPU revision\t: %d\n\n", is64 ? 1 : 2); + } + + if (!is64) { + dprintf(fd, "Hardware\t: %s\n", is64 ? "??" : "Marvell Armada 370/= XP (Device Tree)"); + dprintf(fd, "Revision\t: 0000\n"); + dprintf(fd, "Serial\t\t: 0000000000000000\n"); + } + + return 0; +} +#endif int do_guest_openat(CPUArchState *cpu_env, int dirfd, const char *fname, int flags, mode_t mode, bool safe) @@ -8561,7 +8614,8 @@ int do_guest_openat(CPUArchState *cpu_env, int dirfd,= const char *fname, { "/proc/net/route", open_net_route, is_proc }, #endif #if defined(TARGET_SPARC) || defined(TARGET_HPPA) || \ - defined(TARGET_RISCV) || defined(TARGET_S390X) + defined(TARGET_RISCV) || defined(TARGET_S390X) || \ + defined(TARGET_ARM) || defined(TARGET_AARCH64) { "/proc/cpuinfo", open_cpuinfo, is_proc }, #endif #if defined(TARGET_M68K) -- 2.41.0