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([157.82.204.253]) by smtp.gmail.com with ESMTPSA id u19-20020aa78493000000b00666e649ca46sm7075563pfn.101.2023.07.31.01.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 01:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20221208.gappssmtp.com; s=20221208; t=1690793136; x=1691397936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UroyotoWH93LMRAYzk+jFEmO3Lkc/QezRKtbBAIRdSQ=; b=ndFNlVP1Oseovmo4Onh09EjdRmVe9n8ooDptnTyN9WMIorGrh2zddhysLDBdzqR8S2 cd+UUaBVgwFJq4YjGJtc4TeW1eZggL9TicD8RjlcK5BJkQJIY+Rdjx3i5M/y3Q9/HaKP CFXkcAWAiitXj33lUWcSir0PLvlfv0DqWkOAVWXT4T/em8pEqL5d514mBxgig7/eWzzE yZ5Jtu8EiG4FoYKshg/icNcD+xyziaYii3LygS1aMuuBYWalUn1GyQVSe334SUzDAIrs EBtYQPWfPI0BVyzjqok4Y7QDYe3jHEW0vTR1qRy2dP4mUh6mhYbfnTWqhmQF5LuYuF1g YbYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690793136; x=1691397936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UroyotoWH93LMRAYzk+jFEmO3Lkc/QezRKtbBAIRdSQ=; b=S0cdPArebQiT7jTcFsT5ETGpzYsNU6tHC1HLvXHx0jy8WYnMdhyHwFwZ046N4dbG1B IDk8SrU6aT4Zvp6k6k83BJGDdViVCPynDKz99jOSx37lhjZZVfitcdT8W7lmO2exLULl C5Cgpf+BJfAOhGYO5kmWQE6QW4IySWKRSn66mC7FFWPW/9xXL4xjce//XMR8zLMxbNo8 smkueIrS/CHhvhw8K3yl+H7m/4EJfygyQ6/C3F1jcIpJDGAszuLWY4dX8J9hDNksPg5N 4mV1fjfJZbzUJPS7XBHI2LwyUXx2iItfgeDsKmjM4Dho5tNEsj0MQu8OzcUFeeIkOSft Kwew== X-Gm-Message-State: ABy/qLZ/RTTqh0mmk0dubv++5EKvrC2FwI4rdsxeGU/OMVEoCPg6EHz8 lv8yXfPFTDTxGuhdfR6V0fzEOA== X-Google-Smtp-Source: APBJJlE2cCnFvnW+SATj2mGdDUIaxvAcWVYgvebFHl+oLYZXGSWELvqKormbsZGZHW/0jNvMXcMG2Q== X-Received: by 2002:aa7:88c3:0:b0:687:20d6:faea with SMTP id k3-20020aa788c3000000b0068720d6faeamr6259176pff.15.1690793136092; Mon, 31 Jul 2023 01:45:36 -0700 (PDT) From: Akihiko Odaki To: Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Thomas Huth , Alexandre Iooss , Mahmoud Mandour , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , John Snow , Cleber Rosa , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Brian Cain , Song Gao , Xiaojuan Yang , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Nicholas Piggin , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Akihiko Odaki Subject: [RFC PATCH 09/24] target/riscv: Use GDBFeature for dynamic XML Date: Mon, 31 Jul 2023 17:43:36 +0900 Message-ID: <20230731084354.115015-10-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731084354.115015-1-akihiko.odaki@daynix.com> References: <20230731084354.115015-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42b; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1690793150792100001 Content-Type: text/plain; charset="utf-8" In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu.c | 4 ++-- target/riscv/gdbstub.c | 25 ++++++++++++++----------- 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..f67751d5b7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -391,8 +391,8 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPURISCVState env; =20 - char *dyn_csr_xml; - char *dyn_vreg_xml; + GDBFeature dyn_csr_feature; + GDBFeature dyn_vreg_feature; =20 /* Configuration Settings */ RISCVCPUConfig cfg; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 36de35270d..ceca40cdd9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1962,9 +1962,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState= *cs, const char *xmlname) RISCVCPU *cpu =3D RISCV_CPU(cs); =20 if (strcmp(xmlname, "riscv-csr.xml") =3D=3D 0) { - return cpu->dyn_csr_xml; + return cpu->dyn_csr_feature.xml; } else if (strcmp(xmlname, "riscv-vector.xml") =3D=3D 0) { - return cpu->dyn_vreg_xml; + return cpu->dyn_vreg_feature.xml; } =20 return NULL; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 524bede865..70c60ad8b1 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -212,7 +212,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uin= t8_t *mem_buf, int n) return 0; } =20 -static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) +static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_re= g) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -252,24 +252,27 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, in= t base_reg) =20 g_string_append_printf(s, ""); =20 - cpu->dyn_csr_xml =3D g_string_free(s, false); + cpu->dyn_csr_feature.num_regs =3D CSR_TABLE_SIZE; + cpu->dyn_csr_feature.xmlname =3D "riscv-csr.xml"; + cpu->dyn_csr_feature.xml =3D g_string_free(s, false); =20 #if !defined(CONFIG_USER_ONLY) env->debugger =3D false; #endif =20 - return CSR_TABLE_SIZE; + return &cpu->dyn_csr_feature; } =20 -static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base= _reg) { RISCVCPU *cpu =3D RISCV_CPU(cs); GString *s =3D g_string_new(NULL); g_autoptr(GString) ts =3D g_string_new(""); int reg_width =3D cpu->cfg.vlen; - int num_regs =3D 0; int i; =20 + cpu->dyn_vreg_feature.num_regs =3D 32; + g_string_printf(s, ""); g_string_append_printf(s, "= "); g_string_append_printf(s, ""); @@ -293,19 +296,19 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs,= int base_reg) g_string_append(s, ""); =20 /* Define vector registers */ - for (i =3D 0; i < 32; i++) { + for (i =3D 0; i < cpu->dyn_vreg_feature.num_regs; i++) { g_string_append_printf(s, "", i, reg_width, base_reg++); - num_regs++; } =20 g_string_append_printf(s, ""); =20 - cpu->dyn_vreg_xml =3D g_string_free(s, false); - return num_regs; + cpu->dyn_vreg_feature.xmlname =3D "riscv-vector.xml"; + cpu->dyn_vreg_feature.xml =3D g_string_free(s, false); + return &cpu->dyn_vreg_feature; } =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) @@ -323,7 +326,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, base_reg= ), + ricsv_gen_dynamic_vector_feature(cs, base= _reg)->num_regs, "riscv-vector.xml", 0); } switch (env->misa_mxl_max) { @@ -345,7 +348,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) if (cpu->cfg.ext_icsr) { int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_xml(cs, base_reg), + riscv_gen_dynamic_csr_feature(cs, base_re= g)->num_regs, "riscv-csr.xml", 0); } } --=20 2.41.0