From nobody Sat May 18 12:47:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1690552633; cv=none; d=zohomail.com; s=zohoarc; b=hB7IEtdzTu3L/keirO20ZuxgLN4GqviM5pJ+UG8XG/lwtEo6B9kJ2IRxZkr4SnZSrfx58bf8k3stI9aaFWPMu0WyxHDBdjasOkQqkPIoXK07pw4CyOFCFKG1SAGCM3ZmRjzg+WpMzcWe3iuoY6UCganMCWfb61Oma1kiYBS0Q8U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690552633; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Cl7FFi0tdXS+CwJDAdsPTGNt99E7saecu9cxqSEj+54=; b=dUsVtTjl0q1Dnz+/uKa+14/eaJyc4MtUDL7PVQ1UdYKvePHyKLYL6i78fF2g5kTZBvEJMs1V617InTM+is81GjgTCAqIeQPL4xjK27p++9LIE5y+KOVmugzSyazyDDUdpXU7qz7aopRPwCne5P+cFQl8jD0GvXwtUNNFh0faOCI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690552633976793.9000849311686; Fri, 28 Jul 2023 06:57:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qPNK9-0006eb-Bm; Fri, 28 Jul 2023 09:16:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qPNJu-0006Qd-4E for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:51 -0400 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qPNJo-0003Kl-7P for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:49 -0400 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-1bb7297c505so1656313fac.1 for ; Fri, 28 Jul 2023 06:15:30 -0700 (PDT) Received: from grind.. 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550128; x=1691154928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cl7FFi0tdXS+CwJDAdsPTGNt99E7saecu9cxqSEj+54=; b=RB70xI2Y5NGJY1C28FKCXn8FCvjdcmvTsoTzoBwul4WbJbeWmyznUnkcS3N3Xi9ev/ CDwh/UPFc8ph2inDoAE1OQcTnFOiMSxKQlvMZVq2cnANQUmYbN5FsPzuvrN6NaPtEuXV +5542FYdyAVnOlum2UF4l70nrLXnxzkIGuxzbVde4Js+QkJEvjNf3lnNLHvHJBcnl/ez 6IjRtxUMOw5dockg/sB53oUrdAZ+jP6fPdPUUK1AAc40GeZoUEYU8DZO2mqxmD7KTYho R2y5lZepgWS42Lf8wUmATbgQ2dtA+rbi2bWFPSaHZtH5dezlOETndZrHr0gFZ16rUgo1 LE+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550128; x=1691154928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cl7FFi0tdXS+CwJDAdsPTGNt99E7saecu9cxqSEj+54=; b=XLzy3joPIMyNr+viKwU4yOkld9zQxZGGIMrOnCZCp2VmTcaAaq97XHXRDBIk23oz4r MBEuLY8zOZ5mMMHTQCt6iLrC6vZcz5r+DAZPZmXI6At1DsTaeeeCrhiGkCF35awoAIIT hQv4+na8aEeGe+KFtVcqjxJWdr4Hr1vl87x77/7JN2+z23nTeDaCY8xnbS6AGXKFPBVC NQCS0PwDNrQWlaIBwFi6AknHe0OIhwuwKPmDVUiInZdlYEgZWnXr+ccf4iWmqoWSYhBQ VDft75Y0TyfNUT19LGfbgk5Ca+OH27XCUr2Ip14Migp2oe5/rYW61DIpnP7dVo5x03p3 Qf+Q== X-Gm-Message-State: ABy/qLYjgzeRQEYt3pIvtqfPmwQ97Zwoc3pEqyb6AYI2r+FrACboWXFN nOSg/ycVumiKgCngkgE/Us5N1bgxQn7BCk8IgCFrPQ== X-Google-Smtp-Source: APBJJlG2LVeqsdT9eDX3p3j2zxNQvFrHxS7Zx+Gd4Uj1wsiy0sWHs2IKYjRMSeWFAK+NsOLH0EAqrQ== X-Received: by 2002:a05:6870:c69d:b0:1bc:3f6:579b with SMTP id cv29-20020a056870c69d00b001bc03f6579bmr1663605oab.22.1690550128732; Fri, 28 Jul 2023 06:15:28 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 1/8] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Date: Fri, 28 Jul 2023 10:15:13 -0300 Message-ID: <20230728131520.110394-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690552635214100003 Content-Type: text/plain; charset="utf-8" We'll have future usage for a function where, given an offset of the struct RISCVCPUConfig, the flag is updated to a certain val. Change all existing callers to use edata->ext_enable_offset instead of 'edata'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b5a2266eef..644ce7a018 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,18 +153,17 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 -static bool isa_ext_is_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata) +static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { - bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 return *ext_enabled; } =20 -static void isa_ext_update_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata, bool = en) +static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, + bool en) { - bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 *ext_enabled =3D en; } @@ -1025,9 +1024,10 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RIS= CVCPU *cpu) =20 /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); + isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, + false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", @@ -2271,7 +2271,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.41.0 From nobody Sat May 18 12:47:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1690550482; cv=none; d=zohomail.com; s=zohoarc; b=SGd5d430ZhJPnpfo+1kNCpEYkKzrHUOQ4YpNY7dwPofK3ZLNG/Jffjb2TTURzK2DWEWEWYvt+IB9mXUBTiVGxXdhTBB37eXXhMOFMgv2TXD32vnqRxYxLwPyUkJa/E4jTxzgH5tqCEbMXlPiV5h8HdfkRRXGGZaMNER+HcdNi0k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690550482; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XFuP7PaPRBJxoHUtdhdAxyN5WwLUi/EV/+uL9Zmq2Jk=; b=WSY10M7lbXkkFkuUBvC5cjyfDTZ9SL/Pb0RWtZRoP1SqoqgtzLnJD56H9j/z20Ciwb7o2Bx/gOQWwJwZdSYHBSaSn2JgnUFvvnRtkcS6n1HmayxngGGkUrNIOJ6i9Dh3bCf51YesyiIhtiJImK6zO201+K0PnSTxpWp7ACaK65o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690550482969437.6169699793761; Fri, 28 Jul 2023 06:21:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qPNJz-0006Tl-H0; Fri, 28 Jul 2023 09:15:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qPNJw-0006Qu-Qg for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:53 -0400 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qPNJt-0003Mg-2X for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:52 -0400 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-1bb94563d19so1299970fac.0 for ; Fri, 28 Jul 2023 06:15:32 -0700 (PDT) Received: from grind.. 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550131; x=1691154931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XFuP7PaPRBJxoHUtdhdAxyN5WwLUi/EV/+uL9Zmq2Jk=; b=UDxx1aQE1TD+ZikaIjARYYn6DI3M883bFzZO5pyuB2h+J9+QTodUCSisUpS6yylsyv ATU+V8KNcArCaRfUUEsqJ8OjQNNbsSjA2N+1I0MWBJkaQJwqi/T7TJVyEe703LJboeUi 41c27LyxeDxvC74enttkSdRMltHark25NWc28GkdpSg2MnYmTXzu2bFFeWJp9lvtBJ7o dJqiJmxRbIMka4W6Q1+k+lTw0cAdWuHsw80UoPIokYaFtAZYSZqhrwQRlMvMZ0VRNrJQ tnHucZkxBXVhPUjX7amQelS2TLhfvM/moDM/52sYdwHs04hbee1XGlCixTNxIB4plycU 4X4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550131; x=1691154931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XFuP7PaPRBJxoHUtdhdAxyN5WwLUi/EV/+uL9Zmq2Jk=; b=G7mBq2g0n0hvigpvkX2gxtE5oMxS4ZOejVe5xDowT03lqoAwBpiRVMv7WYGZLvPCQX YnLyLFMXe8cxvsWt/Wm/pSFRHz02DEFcBjMW0bpDPNbg0UKxtNij1xyeUFfiqA4mwH+G hQ5YrkunsksU3WQmECk9BK4s9bUgvhoRpVwD65GDhKdSVE7H6CTGxxTS1dNnV0vrXkVD wVjG0XKecBgcodwk2ocTUQjdg0ZyBMNzioXBkDHvSbXoQgikUenb+3Uo3qY6puZ4RlyC usdDGD8Y5L7S5dLg4zsjBl8pTQUk+CCbkSQ+55iBG7wSrgtlBbrD3QNt8rezrTRlFqtE 8Cng== X-Gm-Message-State: ABy/qLYuOtOAa9/8L4iuSNhFa5kpz6aelwyLlLhWTsEoB8hyW9xz2Ewm aC/t0sFl8L4jkzcIWOwcBZ7nkbev97p3Lqx6h9g+Kg== X-Google-Smtp-Source: APBJJlGQN6qpG9mOd1nEy3Dyugc7BtmVFInmNnTXbDjXLIKYylVD36KIR8cjgHwwz5C36G/3T7LZVA== X-Received: by 2002:a05:6870:472b:b0:1bb:7f1d:10f5 with SMTP id b43-20020a056870472b00b001bb7f1d10f5mr4909077oaq.20.1690550131395; Fri, 28 Jul 2023 06:15:31 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 2/8] target/riscv: make CPUCFG() macro public Date: Fri, 28 Jul 2023 10:15:14 -0300 Message-ID: <20230728131520.110394-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690550485649100003 Content-Type: text/plain; charset="utf-8" The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset of a certain field in the struct RISCVCPUConfig. We're going to use this macro in target/riscv/cpu.c as well in the next patches. Make it public. Rename it to CPU_CFG_OFFSET() for more clarity while we're at it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 ++ target/riscv/kvm.c | 8 +++----- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 644ce7a018..3e62881d85 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -48,7 +48,7 @@ struct isa_ext_data { }; =20 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 /* * From vector_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..577abcd724 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -62,6 +62,8 @@ const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 +#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 =3D 0, diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 9d8a8982f9..9b8565d809 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -198,10 +198,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cp= u, CPUState *cs) } } =20 -#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop) - #define KVM_EXT_CFG(_name, _prop, _reg_id) \ - {.name =3D _name, .offset =3D CPUCFG(_prop), \ + {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .kvm_reg_id =3D _reg_id} =20 static KVMCPUConfig kvm_multi_ext_cfgs[] =3D { @@ -278,13 +276,13 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Vi= sitor *v, =20 static KVMCPUConfig kvm_cbom_blocksize =3D { .name =3D "cbom_blocksize", - .offset =3D CPUCFG(cbom_blocksize), + .offset =3D CPU_CFG_OFFSET(cbom_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) }; =20 static KVMCPUConfig kvm_cboz_blocksize =3D { .name =3D "cboz_blocksize", - .offset =3D CPUCFG(cboz_blocksize), + .offset =3D CPU_CFG_OFFSET(cboz_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) }; =20 --=20 2.41.0 From nobody Sat May 18 12:47:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1690550599; cv=none; d=zohomail.com; s=zohoarc; b=GJl3KCz9SSvJZFFfMm3c7DDISeSOD8GSkt/pP8Zn7XK6S111WWhGl19wlcwBOrMRJ9fxund0+rzEmUdiJXy0AbjvvkBgRT5DULgf93EiK3BQMeizOlZy55JzMCi0xK/+s3lTTH/uUbPbERw1lOkEFUEbWr5PyGEz68b++kB4UNg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690550599; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=87P/tos8Xfm7sOyDFm5C5C2VI/dnIEuzH+4kr2XLTao=; b=BCO8tC81ugRzjslYZjxlN7aZhfsPKY2chP1L1u6BlNhazP7e0ko+bL/1tq2gJN1Yz6Ofm7Vb8xYC5ba8fxY3xPbiuje6FzwFXZb9R6j1LRI7+Es9op6bxymiW/JImBed3eqQfPIpTbe+hmiMWH1s+PRy2KJ8KCCaQtbNFbcrknw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690550599672557.981151951941; Fri, 28 Jul 2023 06:23:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qPNJz-0006TQ-3Z; Fri, 28 Jul 2023 09:15:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qPNJv-0006Qk-HE for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:51 -0400 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qPNJr-0003PL-U9 for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:50 -0400 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-1bbdddd3c94so1196632fac.0 for ; Fri, 28 Jul 2023 06:15:35 -0700 (PDT) Received: from grind.. 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550134; x=1691154934; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=87P/tos8Xfm7sOyDFm5C5C2VI/dnIEuzH+4kr2XLTao=; b=fAxVKAjFQs8UcgvVap2dIJqR4N/lRhBnLDNqFN8fKvAcWtjyF9v1mvA9hSh5NWqI5p Gw6w9YkXhshC3gULKkylHI9JTTnJu4Is1pTrSeRtQDuvs4IjnpACSJBxn/FffcQqAmvA YgokrYjRWvABs5hPe7cW89LbUlnWytnvIrQ34/BcB7fg2/G3AXXLvWOcXLnS32oEacuQ wyrMaNczCPH7zaD25/vFVmMKoACgHs58bDwLGVdQ8eel/gFKcp0TMzfwOUCSyfOvHoAC n6K+LQj9T2rjG/Lz0RQ9XHtxubHyX8fCY7DB9E5VnejcPYyuEg3vA2wogQikdAjwV0IK s3AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550134; x=1691154934; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=87P/tos8Xfm7sOyDFm5C5C2VI/dnIEuzH+4kr2XLTao=; b=QWUozv4ZHz+8sVNi4a2Ubdoyes6l7JBHBOH6ufVZTTQEtum/X9f7zmxcJe4JwZ1kTP cmYeFy8gJ3vVey7OJGZZh8G8fdf9BU8SJ4u4LRlK058eyYlk9q0SzxLlIYHE15G84fJr Y6RWZAkxRwB9lhnZqtyRwRj8Y7CS4Zx9XLMYH1lb5dUQBuiTTO6b8//qNfvpF86QPb/m xPohOES+cvEnv046ysGLE8aA2QAGY+wdtrwCndehW6vEVPsc2uvJ8ZHlALTrfU5CUEUa rJKfgZISJy49zq9tEv35A6CTEtp1mGiynMytdETy82JuIqfxzxvSV1zMQu5J9SSN0QcX 0diw== X-Gm-Message-State: ABy/qLYg6EMItw9g0gnO8nAaW9DpxUpbcC/yoo/1QcVGjM0DqTcdXo0k nOFmJ8T3dInyFRSmZEGgNISCl7ubJJfqx+/BCuqZvQ== X-Google-Smtp-Source: APBJJlG5yfSmDjGcXSNSMQaFGtLMuztkBnx32DSYNGsxX3EgvDqcCk4h1ATGCnWTwT+I8SXC68KCxQ== X-Received: by 2002:a05:6870:b50e:b0:1bb:8162:dfcc with SMTP id v14-20020a056870b50e00b001bb8162dfccmr3419952oap.11.1690550134196; Fri, 28 Jul 2023 06:15:34 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 3/8] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Date: Fri, 28 Jul 2023 10:15:15 -0300 Message-ID: <20230728131520.110394-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690550600729100003 Content-Type: text/plain; charset="utf-8" During realize() time we're activating a lot of extensions based on some criteria, e.g.: if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; cpu->cfg.ext_zkt =3D true; } This practice resulted in at least one case where we ended up enabling something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that has priv_spec older than 1.12.0. We're also not considering user choice. There's no way of doing it now but this is about to change in the next few patches. cpu_cfg_ext_auto_update() will check for priv version mismatches before enabling extensions. If we have a mismatch between the current priv version and the extension we want to enable, do not enable it. In the near future, this same function will also consider user choice when deciding if we're going to enable/disable an extension or not. For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3e62881d85..75dc83407e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -168,6 +168,44 @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint= 32_t ext_offset, *ext_enabled =3D en; } =20 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + continue; + } + + return isa_edata_arr[i].min_version; + } + + /* Default to oldest priv spec if no match found */ + return PRIV_VERSION_1_10_0; +} + +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -1248,12 +1286,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) =20 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu->cfg.ext_zca =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { - cpu->cfg.ext_zcd =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); } } =20 --=20 2.41.0 From nobody Sat May 18 12:47:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1690553197; cv=none; d=zohomail.com; s=zohoarc; b=gh/CWctQvSfaqZKYgaoaSHlE4VNhk6RZdRgcQasILmTQHYClHwQ6Z17KdLfYVddpYSa8elWfmBHbVA9oQr0Ea0pYgm4N8rBvO2rTA4NEBGbg03cec8HAoDVhp2l3FatAuq+2Hc9zQbk+DrMRRRYpuw8mBntiWgmvNoShFllwYhw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690553197; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hURLgEYq1ah5AvqohmfouRDP0rqjlMJUdkrq8M2Fn4k=; b=RYiDNdKeo0JWlLn3xpGu0AUqIEJi+WKvGslQfyvlyWjREyY1db+PnE/8iaAeiNJ2y2Pm22QUCmar33bkIT50w79WdW2b99UMhNZTif+wqoVUd+VSCD2ndahjfRSXEoZR3NotPW25c3kW1D6T4ToUa+oJTcRQpzYUIfLtlheDH+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690553197726305.1472370599231; Fri, 28 Jul 2023 07:06:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qPNKM-0006kK-N8; Fri, 28 Jul 2023 09:16:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qPNJv-0006Qh-Fd for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:51 -0400 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qPNJr-0003Pk-Uu for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:50 -0400 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1bb74752ddbso1666188fac.0 for ; Fri, 28 Jul 2023 06:15:37 -0700 (PDT) Received: from grind.. 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550137; x=1691154937; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hURLgEYq1ah5AvqohmfouRDP0rqjlMJUdkrq8M2Fn4k=; b=SzFZbs5Bs1zvTAEsyk46J/s6cTaBuIiVx4axjsYkVdIMoTA0Ov1CKVxHfOvGIV/Agz Gg+qQP5bT3Lw4wFTobl7j0qUZJevQqLLbOVA/+whOZvrGMtdhc7ydf5nFwYIyl58kQ0c h8V4+ISYfkmve3j3aePTu2fT14Ip9RD9EDJ2JqVqX+7uH2clTXsOQ9cBAa2n41u/BdiB 4ORFV6LRhPQv1afpipPA8dIGhsMcwGCfDSqBJEpNvrwSylqcAE6RewHkcEp+cUUmOAno kDSAtebmgLQ3HeAxHWpvgpttI4gX+pBAVpMjbOF6obCxzWcHLxhZiTH0RmCnlz/lStI9 xqgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550137; x=1691154937; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hURLgEYq1ah5AvqohmfouRDP0rqjlMJUdkrq8M2Fn4k=; b=TrS24fIoXCRb6zWOTldp6LMWMgqL2QkWNUBjONylvGgXI9y4cZW78tnY0KphV9/99D 1orwvDWEbSuF2hZ469VHr9PSo7/p087tBUOpLn+s+2s4kFO3cZgRGqmJq57clFUy2J8M UCaG5j7X7Ko3viLgyKfI9SJCkPDCWlOkDXkfmL6ioDA1qWeknVvSaVqjaovZDTwAa9IM 91h1tBUngf7UALWz6EbOolk9owA8HP3/Ahu9YcYtxzZW5JqLBnTrcS6YDfcn3TAF6fvi H6fxMJLH2lhybV6QWnMjvNkdGKKHVUr8HNF6DWtx0jbK6N4bo8gWexPmAP1Am16hNHIo PXNg== X-Gm-Message-State: ABy/qLZCCxpEUM0Sc8hNB/p9SwGgEvwYnbPzBA7tQAGgTDwrItxPIIX5 lg1q5GEQ3P3Rc6sOAQgV1uyoS+H4TVokefo5DENtqA== X-Google-Smtp-Source: APBJJlFaD6lUXHpCyfYfbHsuve2yFQWDgZKquVN3bkPU4+TKlyM7sWpTPGTbKqn5SCNuc3YxPTqtBw== X-Received: by 2002:a05:6870:c093:b0:1b0:b13:c18 with SMTP id c19-20020a056870c09300b001b00b130c18mr3363467oad.3.1690550136837; Fri, 28 Jul 2023 06:15:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 4/8] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Date: Fri, 28 Jul 2023 10:15:16 -0300 Message-ID: <20230728131520.110394-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690553211372100001 Content-Type: text/plain; charset="utf-8" Let's change the other instances in realize() where we're enabling an extension based on a certain criteria (e.g. it's a dependency of another extension). We're leaving icsr and ifencei being enabled during RVG for later - we'll want to error out in that case. Every other extension enablement during realize is now done via cpu_cfg_ext_auto_update(). The end goal is that only cpu init() functions will handle extension flags directly via "cpu->cfg.ext_N =3D true|false". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 50 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 75dc83407e..88b263e830 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1174,7 +1174,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zfh) { - cpu->cfg.ext_zfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); } =20 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { @@ -1200,17 +1200,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - cpu->cfg.ext_zve64d =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); } =20 /* The Zve64d extension depends on the Zve64f extension */ if (cpu->cfg.ext_zve64d) { - cpu->cfg.ext_zve64f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); } =20 /* The Zve64f extension depends on the Zve32f extension */ if (cpu->cfg.ext_zve64f) { - cpu->cfg.ext_zve32f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); } =20 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { @@ -1224,7 +1224,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zvfh) { - cpu->cfg.ext_zvfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); } =20 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { @@ -1254,7 +1254,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) =20 /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { - cpu->cfg.ext_zhinxmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); } =20 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { @@ -1275,12 +1275,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zce) { - cpu->cfg.ext_zca =3D true; - cpu->cfg.ext_zcb =3D true; - cpu->cfg.ext_zcmp =3D true; - cpu->cfg.ext_zcmt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } =20 @@ -1329,26 +1329,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); } =20 if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); } =20 if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550139; x=1691154939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IpJo8abEeyCDApwOlh5w7EvNS+cv5QHlOzNKGp10Uwo=; b=kQWmg7k5Z14ftZUjttpY8FrZrN6KleBBoCQbT6yyXMgiIHtg0rWhQG9iKkqh743wFZ O2hErt9uthiiNG2JUdHk6qFcdOoTiS9xqKmBgo9zbWJHR/QO46+/nav/WFhE6f4bR9Tx 8eAGEMAsTrhZJtcSNeSPcdcMJCE5N46BIeKwLNWHK9desFuJ15uw2QZvqj9jjbdP8EUG 6hicjg0q+V6tncys4seH47WJtWLhtn7ypDIqwRpDwjqkgye5WX3/r7DAKiyoSKIJMKGl gbb8eRuNzz0yiUamQOP+XHr82SModE2ZubrKppAFnyoE3fAONWOQIb5+w6xKq8ICD7YF x4aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550139; x=1691154939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IpJo8abEeyCDApwOlh5w7EvNS+cv5QHlOzNKGp10Uwo=; b=Zy4EpmWnuGts9dwPEX07p6QgKmrAsVgn4SUnuMj9zxxkkBWgGVICUgwbH9JcyALPCj nRSZ6a2Q09NvyiZ8JGkI5yGdfYkloD5tdCxf+6eMO0UOZG1owf70DwGbp5k4bbBrwFZ6 I/21mQ53HaVMm8hxfyUgpKDKndelD1hYHkli7L9j4GF7urxxLQ95AbWA8wQLNBshlQn9 VUcry6/EcrvTJYb6ecsR0OayBR9t2Kp+N39rhJHYl+uu2sc7R0JJ26e2VHU29L2rsl6Z 5XcxeNPowKXGenHphIlny6aLZN4YunbBZ7Xx20JB87EZ/6+5uM4dEJqiwZInR/6l6Lkj NuyQ== X-Gm-Message-State: ABy/qLYzI9X4k0gyNDDcqQit/Wy1/aikJZd3OMoq7xYzqle7YgS5jyN4 xI/luXuNECXXo+FI+nvdnWVF3cCnXsqI7eG6VqB6Nw== X-Google-Smtp-Source: APBJJlFSaF4oCukFjxSA1UX+TW7N6XudC7oKuMZiXH/UwkIst38TVzDsG5AfMwJYlh87BQkf5cF0Sw== X-Received: by 2002:a05:6870:2115:b0:1bb:b13c:7fa4 with SMTP id f21-20020a056870211500b001bbb13c7fa4mr3107521oae.26.1690550139463; Fri, 28 Jul 2023 06:15:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 5/8] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Date: Fri, 28 Jul 2023 10:15:17 -0300 Message-ID: <20230728131520.110394-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690551198222100001 Content-Type: text/plain; charset="utf-8" If we want to make better decisions when auto-enabling extensions during realize() we need a way to tell if an user set an extension manually. The RISC-V KVM driver has its own solution via a KVMCPUConfig struct that has an 'user_set' flag that is set during the Property set() callback. The set() callback also does init() time validations based on the current KVM driver capabilities. For TCG we would want a 'user_set' mechanic too, but we would look ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set or not. If we copy what was made in the KVM side we would look for 'user_set' for one into 60+ extension structs spreaded in 3 arrays (riscv_cpu_extensions, riscv_cpu_experimental_exts, riscv_cpu_vendor_exts). We'll still need an extension struct but we won't be using the 'user_set' flag: - 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to wh= at we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'. DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct; - the 'multi_ext_user_opts' hash will be used to store the offset of each extension that the user set via the set() callback, cpu_set_multi_ext_cfg(). For now we're just initializing and populating it - next patch will use it to determine if a certain extension was user set; - cpu_add_multi_ext_prop() is a new helper that will replace the qdev_property_add_static() calls that our macros are doing to populate user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY() for clarity. Note that the non-extension properties in riscv_cpu_options[] still need to be declared via qdev(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 231 ++++++++++++++++++++++++++++----------------- 1 file changed, 145 insertions(+), 86 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88b263e830..b588f6969f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 +/* Hash that stores user set extensions */ +static GHashTable *multi_ext_user_opts; + static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; @@ -1668,6 +1671,8 @@ static void riscv_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ + + multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); } =20 typedef struct RISCVCPUMisaExtConfig { @@ -1819,94 +1824,104 @@ static void riscv_cpu_add_misa_properties(Object *= cpu_obj) } } =20 -static Property riscv_cpu_extensions[] =3D { +typedef struct RISCVCPUMultiExtConfig { + const char *name; + uint32_t offset; + bool enabled; +} RISCVCPUMultiExtConfig; + +#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ + {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ + .enabled =3D _defval} + +static RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), - DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), - DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), - DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), - DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), - - DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), - DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), - DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), - DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), - - DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), - DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), - DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), - DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), - DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), - DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), - DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), - DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), - DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), - DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), - DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), - DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), - DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), - DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), - DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), - DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), - DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), - - DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), - DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), - DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), - DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), - - DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), - DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), - - DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), - - DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), - DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), - DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), - DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), - DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), - DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), - DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), + MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), + MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), + MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true), + MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true), + MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true), + MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true), + MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false), + MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false), + MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false), + MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false), + MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false), + MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + + MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), + MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), + MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), + MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), + MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), + + MULTI_EXT_CFG_BOOL("zba", ext_zba, true), + MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), + MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true), + MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false), + MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false), + MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false), + MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true), + MULTI_EXT_CFG_BOOL("zk", ext_zk, false), + MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false), + MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false), + MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false), + MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false), + MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false), + MULTI_EXT_CFG_BOOL("zks", ext_zks, false), + MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false), + MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false), + MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false), + + MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false), + MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false), + MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false), + MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), + + MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true), + MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true), + + MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), + + MULTI_EXT_CFG_BOOL("zca", ext_zca, false), + MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false), + MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false), + MULTI_EXT_CFG_BOOL("zce", ext_zce, false), + MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false), + MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false), + MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), }; =20 -static Property riscv_cpu_vendor_exts[] =3D { - DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), - DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), - DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), - DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), - DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), - DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, fal= se), - DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), - DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), - DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false= ), - DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), - DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), - DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), +static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { + MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), + MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), + MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), + MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false), + MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false), + MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false), + MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false), + MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false), + MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false), + MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), + MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), + MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), }; =20 /* These are experimental so mark with 'x-' */ -static Property riscv_cpu_experimental_exts[] =3D { - DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), +static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { + MULTI_EXT_CFG_BOOL("x-zicond", ext_zicond, false), =20 /* ePMP 0.9.3 */ - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), - DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), + MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), + MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), + MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false), =20 - DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), - DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), + MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false), + MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false), =20 - DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), + MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false), + MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false), + MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false), }; =20 static Property riscv_cpu_options[] =3D { @@ -1925,6 +1940,49 @@ static Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), }; =20 +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(multi_ext_cfg->offset), + (gpointer)value); +} + +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_add_multi_ext_prop(Object *cpu_obj, + RISCVCPUMultiExtConfig *multi_cfg) +{ + object_property_add(cpu_obj, multi_cfg->name, "bool", + cpu_get_multi_ext_cfg, + cpu_set_multi_ext_cfg, + NULL, (void *)multi_cfg); + + /* + * Set def val directly instead of using + * object_property_set_bool() to save the set() + * callback hash for user inputs. + */ + isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, + multi_cfg->enabled); +} + #ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, const char *name, @@ -1944,10 +2002,10 @@ static void cpu_set_cfg_unavailable(Object *obj, Vi= sitor *v, } #endif =20 -#define ADD_CPU_QDEV_PROPERTIES_ARRAY(_dev, _array) \ +#define ADD_CPU_MULTIEXT_PROPS_ARRAY(_obj, _array) \ do { \ for (int i =3D 0; i < ARRAY_SIZE(_array); i++) { \ - qdev_property_add_static(_dev, &_array[i]); \ + cpu_add_multi_ext_prop(_obj, &_array[i]); \ } \ } while (0) =20 @@ -2005,8 +2063,6 @@ static void riscv_cpu_add_kvm_properties(Object *obj) */ static void riscv_cpu_add_user_properties(Object *obj) { - DeviceState *dev =3D DEVICE(obj); - #ifndef CONFIG_USER_ONLY riscv_add_satp_mode_properties(obj); =20 @@ -2018,10 +2074,13 @@ static void riscv_cpu_add_user_properties(Object *o= bj) =20 riscv_cpu_add_misa_properties(obj); =20 - ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_extensions); - ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_options); - ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_vendor_exts); - ADD_CPU_QDEV_PROPERTIES_ARRAY(dev, riscv_cpu_experimental_exts); + ADD_CPU_MULTIEXT_PROPS_ARRAY(obj, riscv_cpu_extensions); + ADD_CPU_MULTIEXT_PROPS_ARRAY(obj, riscv_cpu_vendor_exts); + ADD_CPU_MULTIEXT_PROPS_ARRAY(obj, riscv_cpu_experimental_exts); + + for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { + qdev_property_add_static(DEVICE(obj), &riscv_cpu_options[i]); + } } =20 /* --=20 2.41.0 From nobody Sat May 18 12:47:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1690551582; cv=none; d=zohomail.com; s=zohoarc; b=Qj2YeB7xz7OlZI8BreKeHTeWa0ncMiMndwLVQnN2t+V1kwQtc8Z7vU9Uw5KqYvmRvzi34+RQJtwm/5XaFj1R13dE9hazMM+ZKidDXuYdlpGB3qClMg60fEeBaK7IkFWj+CmYj4O2W7hMDY4LRdV64B8l1ZDfeARim4l+58ye24Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690551582; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i6sZacMewneSeQj5bmv5KaBVBjn8NIxNMS30kFI2Yv0=; b=RQTt1Od2ieb5h8tDyUA7JTAiUswrdtlsKXXhln0xqCalKtjMp1uQU5ESGU4y+otssZ4Q3gApVWhqRFjsLPN3qIAH0LSWp9T253AwWLgXSTiq5YchhTLBmLboQtnLpNXVpinjLR8F/HGIR+r4xpcTl+h0ioCQ8mUuFdQjMdAZx3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690551582449734.0842905628772; Fri, 28 Jul 2023 06:39:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qPNK0-0006UT-V7; Fri, 28 Jul 2023 09:15:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qPNJy-0006Sv-9Q for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:54 -0400 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qPNJt-0003R6-4E for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:53 -0400 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-1a28de15c8aso1665800fac.2 for ; Fri, 28 Jul 2023 06:15:43 -0700 (PDT) Received: from grind.. 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550142; x=1691154942; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i6sZacMewneSeQj5bmv5KaBVBjn8NIxNMS30kFI2Yv0=; b=lwyrLf50hxXJ4lvgmF0KvcNvAAwO/3i/lCO7l5hiyjdwr3AIYvezKxmp2bJ3SiSGe2 VgRRalJHbARMw0G3HtKuhFPYtk1eJiY47VoeXnwVikX+YhcaD2Bfon0nt/YudvhRlgVU pGZ50anvoOc6PbXsYQKIqeC1HDaPRNwAMzw9/Ml0fqIxfv/ST+ZZAtq5DSq8CvFGzevf FAujvkqr6e8UZDkIOfYb9SeGAdgOc5+2EUvqes12xR31GwI1rR92zP537eB5bMH7OAMn IHcz+zY5GM1iE5s7C7c7GVN6UpsjpigVE5sYRs1c3oTc19uIMmQ31pJwXOdkpO+IOxSF 6Hhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550142; x=1691154942; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i6sZacMewneSeQj5bmv5KaBVBjn8NIxNMS30kFI2Yv0=; b=iPkvkA+7aziQZdQ7nZssYhn5tQKygf9HRhKXHtiwTTX75dOcPn6U9ynQE527gdjDvv Rk7sWh+yk+rEao9DeZdJJVsQEpfKtLa1sKN3ixfvF8nmJjL0lhnzgm733nVubaMA9/VK wJ/K/KzDzyK2Pg/Q3C0gHODjycwnzuXLvB6elFuNA0ENkomsEm1/JkZrdNBPdGv0N66m aMxBtw/bjTmsWyVsq4A+NQ5HYjaUzBzawHPY7sXurrUgHQ2AHmll/C0SOSW3Y8TSAtCv GZvPqfo58RvQ2IEb8enE6IXRT0rg7UWJreWd4RTY06HiidY0kLdJFDt0ZWgDZ7e49U9I BvcA== X-Gm-Message-State: ABy/qLZ7ER7IwRc0UCAxdEakpGjA/lNqodL09nJL5EUGJf5SD6QyRoy/ p1PMiOsZZnqZjKGQ8v1aZubhAnQkclRY3ssrr0xbDg== X-Google-Smtp-Source: APBJJlGOF15QRQWtVMJmRwH7cwPGlSv5xIW3nUqj/0VtMrl6V/99OdOWzAAI2ZmIvSv1AjWdJXm4+w== X-Received: by 2002:a05:6870:73cf:b0:1bb:7d67:a807 with SMTP id a15-20020a05687073cf00b001bb7d67a807mr3199896oan.51.1690550142094; Fri, 28 Jul 2023 06:15:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 6/8] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Date: Fri, 28 Jul 2023 10:15:18 -0300 Message-ID: <20230728131520.110394-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690551584461100003 Content-Type: text/plain; charset="utf-8" Before adding support to detect if an extension was user set we need to handle how we're enabling extensions in riscv_init_max_cpu_extensions(). object_property_set_bool() calls the set() callback for the property, and we're going to use this callback to set the 'multi_ext_user_opts' hash. This means that, as is today, all extensions we're setting for the 'max' CPU will be seen as user set in the future. Let's change set_bool() to isa_ext_update_enabled() that will just enable/disable the flag on a certain offset. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b588f6969f..a40dc865a0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2096,25 +2096,24 @@ static void riscv_init_max_cpu_extensions(Object *o= bj) set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); =20 for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_extensions); i++) { - object_property_set_bool(obj, riscv_cpu_extensions[i].name, - true, NULL); + isa_ext_update_enabled(cpu, riscv_cpu_extensions[i].offset, true); } =20 /* set vector version */ env->vext_ver =3D VEXT_VERSION_1_00_0; =20 /* Zfinx is not compatible with F. Disable it */ - object_property_set_bool(obj, "zfinx", false, NULL); - object_property_set_bool(obj, "zdinx", false, NULL); - object_property_set_bool(obj, "zhinx", false, NULL); - object_property_set_bool(obj, "zhinxmin", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); =20 - object_property_set_bool(obj, "zce", false, NULL); - object_property_set_bool(obj, "zcmp", false, NULL); - object_property_set_bool(obj, "zcmt", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); =20 if (env->misa_mxl !=3D MXL_RV32) { - object_property_set_bool(obj, "zcf", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } } =20 --=20 2.41.0 From nobody Sat May 18 12:47:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1690553479; cv=none; d=zohomail.com; s=zohoarc; b=Dt5Fe9xtUOdcxmbz0RJVlAo5/P/l+lzK8N/8MuhzSt3YxgLuACQ7cBE3lNbS6kXvyNfpsoa/uAyfvBITiJ944f5jt6/o8HLB/H6Xy5rlykIUYhGOz0rlujMQocm8gWYR/0bRl8pb+K76PW4aMR+0/PA2YLqvp32ZpY6LY8r0Xmk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690553479; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mOnI9hH6NlaZaaUBLQ1CH8wjZUIfM0115L0/n42OTo4=; b=MAgiQMl9I7QfeiBvgU9FtuNbmkWNxbK1DOT8f65mbzvlxQYbKOLXnZQypQgH/vXLvuCHfiohzn0Nn2rVhgTYyCRaNHo2vwq4OR0WR+wNYdUxGMlqNWaLlyqKlrSGEefk1E6oPRvZpzqm/UVjf5n+YA8Ppz+mYCCf/H/JeBeta5Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690553479301438.08321630293096; Fri, 28 Jul 2023 07:11:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qPNKD-0006hD-8b; Fri, 28 Jul 2023 09:16:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qPNJx-0006Sc-UQ for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:54 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qPNJt-0003St-3y for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:53 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-1bb7297c505so1656515fac.1 for ; Fri, 28 Jul 2023 06:15:46 -0700 (PDT) Received: from grind.. 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550145; x=1691154945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mOnI9hH6NlaZaaUBLQ1CH8wjZUIfM0115L0/n42OTo4=; b=fu4ufrwxg2vhijt8buawqU/RP6oniT5YH0MQGy6Jnthk7FFIfyg7Pw/d6p3ItxZSh1 taGn0yhRksbe9wKGnN5TYtmimPhNjKKdXZPwpQ5tZihDirPWJyCfbiHi7hE9OuycEEKv 5nEwAeOM6UvEDZE1cFSSowRE/MBtWC0YV4xvniV6U7pJfMEADV+xligTYUqVpYwMISBz leu7v5oVjER4djNmDdLiO+XZjwA9RHXLIOyIbR3V4GJQ+Pvw/6FmLPcDLu2prEv4vCiX VTRz0njjoXE+YvuqCL9TH61eFtcLy2KuIvALfP3ZDSiO7luK4DdrBW8D44GC0PefxqCA OtYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550145; x=1691154945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mOnI9hH6NlaZaaUBLQ1CH8wjZUIfM0115L0/n42OTo4=; b=MTqx42W3nxGWPu4HsOg5spJ7HjulrW572dfmCasaBzaaW4SoBhlE8VEIkFNmEjhum0 TOvZ8IsE0BPzGBviW65GY1miB/wBHbkqFwoiTBNoYijU9xjcsgIdZLaSVHYRGFXAXNJS nNTpXMjmvLslDpMCUAY6SdE+AvJIjrJOusgj3xO91h1wNFR428QKSkgRRSAzUQaRSpx/ dzeMtkv7vVvyDQToKZAZBoI1JOrok17oQB+WC7b9CngSsvKoB1kV4BqKYz0s0PT/Bmc3 50qOFhCqMHmZonnpDHI+snFmPw7JwhphkpM6Q6ES+M5kxY/cAYNWyXz/6tcZCt0GAAPP vU3Q== X-Gm-Message-State: ABy/qLYCmvD2smMtrj+Au17Psz2jrqJGUHq7SeP6MfwASUFA0pzHxW+f aybsFdsF8bWJuNCkFdAWMkzW+1CzdSxj+LihFuMFyw== X-Google-Smtp-Source: APBJJlEH+bAbhWlP6MwIjmF0E3VKTVXK/Soat3fmbaPbzmXLJa9k46TU1LZau/0uxJ/uRjq7IuAbqg== X-Received: by 2002:a05:6870:e30e:b0:1b3:8285:153e with SMTP id z14-20020a056870e30e00b001b38285153emr2508163oad.44.1690550145312; Fri, 28 Jul 2023 06:15:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 7/8] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Date: Fri, 28 Jul 2023 10:15:19 -0300 Message-ID: <20230728131520.110394-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690553480207100001 Content-Type: text/plain; charset="utf-8" Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was set by the user in the command line. Use it inside cpu_cfg_ext_auto_update() to verify if the user set a certain extension and, if that's the case, do not change its value. This will make us honor user choice instead of overwriting the values. Users will then be informed whether they're using an incompatible set of extensions instead of QEMU setting a magic value that works. For example, we'll now error out if the user explictly set 'zce' to true and 'zca' to false: $ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=3Dtrue,zca=3Dfalse -nog= raphic qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension This didn't happen before because we were enabling 'zca' if 'zce' was enabl= ed regardless if the user explictly set 'zca' to false. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a40dc865a0..644d0fdad2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -187,6 +187,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) return PRIV_VERSION_1_10_0; } =20 +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -198,6 +204,10 @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uin= t32_t ext_offset, return; } =20 + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { /* Do not enable it if priv_ver is older than min_version */ min_version =3D cpu_cfg_ext_get_min_version(ext_offset); --=20 2.41.0 From nobody Sat May 18 12:47:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1690555272; cv=none; d=zohomail.com; s=zohoarc; b=SEXNt2hClO0FyrJUBtPvuOrelJo/ovQcHFMD0MQXtP/FDuCZ7aiMpIKpLcSqvgH/wrpVsJSeEtbqyHZyCKwc4nVE4hRuOPF9rRfHg9+JK96vOcYMrswchXBDDugAPUX81ltEWgKO3RpEM0xw7/A/IUpqR/uOSusbyhKEKcwoFSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690555272; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HDa6yMT5aLs7zW0tfsJSZj3Oa5XrkTDlwa0+B86L+T0=; b=A+R4XXdaBewwALH3FZSZa9HejMZOt1x40r4/0DsPaCxNiwSvZ4VkUn54NZv/cdc6nCEZBKI0tahUAtJkAmbCvmfoQuo5EQ3l3E52h3XNLX8CMW2S22FGUnTtQaR7T1S1Jt9TOcfA2GqiDraGK9CGG9iDX9PMdau2dvrLyaZXtU8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690555272798381.8992473032041; Fri, 28 Jul 2023 07:41:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qPNKK-0006hd-SW; Fri, 28 Jul 2023 09:16:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qPNJz-0006TS-1X for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:55 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qPNJt-0003Vk-C6 for qemu-devel@nongnu.org; Fri, 28 Jul 2023 09:15:54 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1bbaa549bcbso1663281fac.3 for ; Fri, 28 Jul 2023 06:15:48 -0700 (PDT) Received: from grind.. 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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id hv6-20020a056871cc0600b001b3d93884fdsm1699371oac.57.2023.07.28.06.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:15:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690550148; x=1691154948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HDa6yMT5aLs7zW0tfsJSZj3Oa5XrkTDlwa0+B86L+T0=; b=o/jT3dcwwh3XR2UtClubXxzuPb0PZMx/IM8yE2A2dbU5GxJYHJbklZveV0lUCscAE3 DND/M+MOEs51d/UPxlR5PATuFA54g29knTKAJSD3WA2EeNNWL74xMY1jDLNDELIjxP4+ /GwB2Tkw6+t79OD/cxAC1N1m7U7SpqzLvSOBBc1d7jgSEEjwd/xXbNz2S63inS4hM3Tb szDK/PKvOkj3V32STaExe56oKXeGC/VoUAVWII5c3SIg72syF1VO0b5NVdC8p8qDF9/A z+hB1C7GDfOnKGPeoDpUznqKCjF9ECWlyYEAYGyQ53R6gB0roie6P8srBX0p3zxuERXv QnBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690550148; x=1691154948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HDa6yMT5aLs7zW0tfsJSZj3Oa5XrkTDlwa0+B86L+T0=; b=SqSH8WZ8lCse37dqN0s/bFGGD6n6MdhXS3Pg7zIgL6NDEiTA663aZ2ohp0T8ngrruf RiyPgrTZj61KWzPdopfO6VljAPdyCDIZnknzL/7k1MBN6QZwkCvw6cdmMO1vmygEpbK2 z4L3OVYCcw3WdRO+XYQRhy8NDj7DR8nGDiwlaB3dHc+NPgZE27ZyIQwSQMNERWTvzrHz 2ZJIUqpxsgi+kqTdGnVcp9b03O17E//GU1cfjWxpJzALYo9d+hoAlhsPBZFwfRCRPf2n XkdRYSq4WcTAN1GL1DtTg+qb4euXhXYSMjqKflCwIpkplFefz5iIoHTlWXFhP+K/4tB5 XH8Q== X-Gm-Message-State: ABy/qLYxTFjAPvx9eqtXGa5NvcS6LJKaXY+b+rMgN3izZAekpexGjPO4 GhJhoF9hgyQd3DYR9Yc05sONpjQE60Eh+TVjMtT2+A== X-Google-Smtp-Source: APBJJlH4AIaa1v4ib38stcZXYfvq6lz2MnGifddJcZA86CgfhmHwX2HrrZd+X22QkKB7AgTtxiboFg== X-Received: by 2002:a05:6870:f70b:b0:1b7:609f:e0d4 with SMTP id ej11-20020a056870f70b00b001b7609fe0d4mr2899257oab.15.1690550147992; Fri, 28 Jul 2023 06:15:47 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 8/8] target/riscv/cpu.c: consider user option with RVG Date: Fri, 28 Jul 2023 10:15:20 -0300 Message-ID: <20230728131520.110394-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230728131520.110394-1-dbarboza@ventanamicro.com> References: <20230728131520.110394-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690555275137100001 Content-Type: text/plain; charset="utf-8" Enabling RVG will enable a set of extensions that we're not checking if the user was okay enabling or not. And in this case we want to error out, instead of ignoring, otherwise we will be inconsistent enabling RVG without all its extensions. After this patch, disabling ifencei or icsr while enabling RVG will result in error: $ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=3Dtrue,Zifencei=3Dfalse -= -nographic qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 644d0fdad2..72a36b47ed 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1135,8 +1135,22 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , Error **errp) riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_icsr =3D true; - cpu->cfg.ext_ifencei =3D true; + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && + !cpu->cfg.ext_icsr) { + error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); + return; + } + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && + !cpu->cfg.ext_ifencei) { + error_setg(errp, "RVG requires Zifencei but user set " + "Zifencei to false"); + return; + } + + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); =20 env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; --=20 2.41.0