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[201.69.66.36]) by smtp.gmail.com with ESMTPSA id y136-20020a4a458e000000b0051134f333d3sm1070471ooa.16.2023.07.27.15.09.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 15:09:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690495788; x=1691100588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sb7b3Ja0mlFb1eGR3Lro0dwO838RnJMqT2CPVh/wgOA=; b=gNwwiSkp/o8Dc3NupZd8nvP8/IMjCIku1eMT/WEGZ7IosCyCz79rFTe41+wSh1krdQ rfpV5/u0Z+qXID1cF4HEnHTgMlHJwu7Jccr9Yu9FWeXRazMOAt0xsPz1B4z3x676Q0Mf guK9YRIXEXHlCXa7ZqJaSG21G3CyI7S3UcinKIHGWzldnvPwFbDhYp5a0xO4/9UDueXH wLfZgijAB05eS/l5Vb23Ls/MwB7OYO2GRph3PZG5R9gkRuO+eRmPpmZznFrXNNMabEPm 08ZS/LlGRewrGyFx1Yoy2hZIJVQf/QaUNk/JmeMmF0GJmCsjuIhUgzIhncr0PGLCv9u4 sXjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690495788; x=1691100588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sb7b3Ja0mlFb1eGR3Lro0dwO838RnJMqT2CPVh/wgOA=; b=DWOp5G13x6ucS0SmFaEehiIJb9yGhAZPCQCQlV25lAsG47OODywy07cwZaygtREQU3 OAbH0gcsokYFwKYtdd9qjwAS5AqWuUSDY36JzPfbIBSBL/rnaDsEcFXqCPLn2KEwfCGd O4YJAfkXskMw5GQSqT2JFuNsexjADP047FSeYilvCqjrcTl2jylcrXMw1voh4GFAbDyv Zwojj8d26MZJ7SrxGA0JTnB7dR+H7n0K5fzJvNbPa/PG+wDjfsJiKT2U3ydiE/MKZkKq JrijuCeiu0R4oh3kcGg7TbbJxIQD3Ykc3J59X0q71pPJMNZi2X1/D35p6ytGN96TGu9O Fe2g== X-Gm-Message-State: ABy/qLbDacD7+nBpI0ITd5HmtHqFViXuBsD+QoY4RE8f+AkmhjHk3C/0 UnJOtHOg71mNGNmeGSec35SbJiTn4CYixrQR55axhQ== X-Google-Smtp-Source: APBJJlFi4FTlMuIYfzfdr9VBIwp+/Wv5jpdE3znddxfe0F/itc+acgtw2dludR8poNJLcdc7lcNXlw== X-Received: by 2002:a4a:851a:0:b0:569:e93d:1660 with SMTP id k26-20020a4a851a000000b00569e93d1660mr696112ooh.9.1690495788007; Thu, 27 Jul 2023 15:09:48 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v6 06/12] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] Date: Thu, 27 Jul 2023 19:09:21 -0300 Message-ID: <20230727220927.62950-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727220927.62950-1-dbarboza@ventanamicro.com> References: <20230727220927.62950-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1690496563933100003 Content-Type: text/plain; charset="utf-8" Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[]. riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are changed to keep adding non-ratified properties to users. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c8e1de68d3..d829517f40 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1813,21 +1813,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), - - /* These are experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), - - /* ePMP 0.9.3 */ - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), - DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), - - DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), - DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), - - DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), }; =20 static Property riscv_cpu_vendor_exts[] =3D { @@ -1845,6 +1830,23 @@ static Property riscv_cpu_vendor_exts[] =3D { DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), }; =20 +/* These are experimental so mark with 'x-' */ +static Property riscv_cpu_experimental_exts[] =3D { + DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), + + /* ePMP 0.9.3 */ + DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), + DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), + + DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), + DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), + + DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), + DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), + DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), +}; + static Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), =20 @@ -1913,6 +1915,11 @@ static void riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop(obj, riscv_cpu_vendor_exts[i].name); } =20 + for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_experimental_exts); i++) { + riscv_cpu_add_kvm_unavail_prop(obj, + riscv_cpu_experimental_exts[i].name= ); + } + for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { /* Check if KVM created the property already */ if (object_property_find(obj, riscv_cpu_options[i].name)) { @@ -1955,6 +1962,10 @@ static void riscv_cpu_add_user_properties(Object *ob= j) for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_vendor_exts); i++) { qdev_property_add_static(dev, &riscv_cpu_vendor_exts[i]); } + + for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_experimental_exts); i++) { + qdev_property_add_static(dev, &riscv_cpu_experimental_exts[i]); + } } =20 static Property riscv_cpu_properties[] =3D { --=20 2.41.0