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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=nospam@kota.moe; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kota.moe) X-ZM-MESSAGEID: 1690138862097100001 When QEMU is started with `-smp D,sockets=3D1,dies=3DD,cores=3D1,threads=3D= 1` (that is, 1 socket with D dies but each die contains just a single thread), both Linux and Windows guests incorrectly interprets the system as having D sockets with 1 die each Ultimately this is caused by various CPUID leaves not being die-aware in their "threads per socket" calculations, so this patch fixes that These changes are referenced to the AMD PPR for Family 19h Model 01h (Milan) and Family 17h Model 01h (Naples) manuals: - CPUID_Fn00000001_EBX[23:16]: Number of threads in the processor (Core::X86::Cpuid::SizeId[NC] + 1) - CPUID_Fn0000000B_EBX_x01[15:0]: Number of logical cores in processor socket (not present until Rome) - CPUID_Fn80000001_ECX[1]: Multi core product (Core::X86::Cpuid::SizeId[NC] !=3D 0) - CPUID_Fn80000008_ECX[7:0]: The number of threads in the package - 1 (Core::X86::Cpuid::SizeId[NC]) Note there are two remaining occurences that I didn't touch: - CPUID_Fn8000001E_ECX[10:8]: Always 0 (1 node per processor) for Milan. But for Naples, it can also be 2 or 4 nodes where each node is defined as one or two CCXes (CCD?). But Milan also has multiple CCXes, so clearly the definition of a node is different from model to model, so I've left it untouched. (QEMU seems to use the Naples definition) - MSR_CORE_THREAD_COUNT: This MSR doesn't exist on Milan or Naples Signed-off-by: =E5=B0=8F=E5=A4=AA --- target/i386/cpu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 97ad229d8b..6ff23fa590 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6049,8 +6049,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_EXT_OSXSAVE; } *edx =3D env->features[FEAT_1_EDX]; - if (cs->nr_cores * cs->nr_threads > 1) { - *ebx |=3D (cs->nr_cores * cs->nr_threads) << 16; + if (env->nr_dies * cs->nr_cores * cs->nr_threads > 1) { + *ebx |=3D (env->nr_dies * cs->nr_cores * cs->nr_threads) << 16; *edx |=3D CPUID_HT; } if (!cpu->enable_pmu) { @@ -6230,7 +6230,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 1: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; default: @@ -6496,7 +6496,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * discards multiple thread information if it is set. * So don't set it here for Intel to make Linux guests happy. */ - if (cs->nr_cores * cs->nr_threads > 1) { + if (env->nr_dies * cs->nr_cores * cs->nr_threads > 1) { if (env->cpuid_vendor1 !=3D CPUID_VENDOR_INTEL_1 || env->cpuid_vendor2 !=3D CPUID_VENDOR_INTEL_2 || env->cpuid_vendor3 !=3D CPUID_VENDOR_INTEL_3) { @@ -6562,7 +6562,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax |=3D (cpu_x86_virtual_addr_width(env) << 8); } *ebx =3D env->features[FEAT_8000_0008_EBX]; - if (cs->nr_cores * cs->nr_threads > 1) { + if (env->nr_dies * cs->nr_cores * cs->nr_threads > 1) { /* * Bits 15:12 is "The number of bits in the initial * Core::X86::Apic::ApicId[ApicId] value that indicate @@ -6570,7 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * Bits 7:0 is "The number of threads in the package is NC+1" */ *ecx =3D (apicid_pkg_offset(&topo_info) << 12) | - ((cs->nr_cores * cs->nr_threads) - 1); + ((env->nr_dies * cs->nr_cores * cs->nr_threads) - 1); } else { *ecx =3D 0; } --=20 2.39.2