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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=jean-philippe@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1689782284895100003 Content-Type: text/plain; charset="utf-8" When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0 translation regime, instead of the EL2 translation regime. The TLB VAE2* instructions invalidate the regime that corresponds to the current value of HCR_EL2.E2H. At the moment we only invalidate the EL2 translation regime. This causes problems with RMM, which issues TLBI VAE2IS instructions with HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into account. Signed-off-by: Jean-Philippe Brucker --- target/arm/helper.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e1b3db6f5f..07a9ac70f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4663,6 +4663,21 @@ static int vae1_tlbmask(CPUARMState *env) return mask; } =20 +static int vae2_tlbmask(CPUARMState *env) +{ + uint64_t hcr =3D arm_hcr_el2_eff(env); + uint16_t mask; + + if (hcr & HCR_E2H) { + mask =3D ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + } else { + mask =3D ARMMMUIdxBit_E2; + } + return mask; +} + /* Return 56 if TBI is enabled, 64 otherwise. */ static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) @@ -4781,7 +4796,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * flush-last-level-only. */ CPUState *cs =3D env_cpu(env); - int mask =3D e2_tlbmask(env); + int mask =3D vae2_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx(cs, pageaddr, mask); @@ -4838,11 +4853,11 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env= , const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); =20 - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2, bits); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -5014,11 +5029,6 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, do_rvae_write(env, value, vae1_tlbmask(env), true); } =20 -static int vae2_tlbmask(CPUARMState *env) -{ - return ARMMMUIdxBit_E2; -} - static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) --=20 2.41.0