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bh=i2OD4smg/ZvktuylTs1UWQ6Kcn05ZJ4begnPzWgRGK4=; b=KP/8d5dTAsH1zwu7+4hxssbp0uoXjC3w9YfBKM7YGwxXNz1NQncI6YFjq3OkdZnnC3D4EJ 9o6uYl/mmeAkoliennDs7lSMf8Vkg7C/+54xYuJ5Lqx/7Sg9QtyfYw2KWg+WZMfpb4ecrp +cBYOz0yUfe0FQEFCSj+Xio7RyjYNFo= X-MC-Unique: Uhqf_xZxO7SMb70xkQYFgw-1 From: Cornelia Huck To: Peter Maydell , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Cornelia Huck Subject: [PATCH for-8.2 1/2] arm/kvm: convert to kvm_set_one_reg Date: Tue, 18 Jul 2023 13:14:03 +0200 Message-ID: <20230718111404.23479-2-cohuck@redhat.com> In-Reply-To: <20230718111404.23479-1-cohuck@redhat.com> References: <20230718111404.23479-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1689678936116100002 Content-Type: text/plain; charset="utf-8" We can neaten the code by switching to the kvm_set_one_reg function. Signed-off-by: Cornelia Huck Reviewed-by: Gavin Shan --- target/arm/kvm.c | 13 +++------ target/arm/kvm64.c | 66 +++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b4c7654f4980..cdbffc3c6e0d 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -561,7 +561,6 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) bool ok =3D true; =20 for (i =3D 0; i < cpu->cpreg_array_len; i++) { - struct kvm_one_reg r; uint64_t regidx =3D cpu->cpreg_indexes[i]; uint32_t v32; int ret; @@ -570,19 +569,17 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) continue; } =20 - r.id =3D regidx; switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: v32 =3D cpu->cpreg_values[i]; - r.addr =3D (uintptr_t)&v32; + ret =3D kvm_set_one_reg(cs, regidx, &v32); break; case KVM_REG_SIZE_U64: - r.addr =3D (uintptr_t)(cpu->cpreg_values + i); + ret =3D kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); break; default: g_assert_not_reached(); } - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { /* We might fail for "unknown register" and also for * "you tried to set a register which is constant with @@ -703,17 +700,13 @@ void kvm_arm_get_virtual_time(CPUState *cs) void kvm_arm_put_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM_TIMER_CNT, - .addr =3D (uintptr_t)&cpu->kvm_vtime, - }; int ret; =20 if (!cpu->kvm_vtime_dirty) { return; } =20 - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); abort(); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 94bbd9661fd3..b4d02dff5381 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -540,14 +540,10 @@ static int kvm_arm_sve_set_vls(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM64_SVE_VLS, - .addr =3D (uint64_t)&vls[0], - }; =20 assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); =20 - return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); } =20 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 @@ -725,19 +721,17 @@ static void kvm_inject_arm_sea(CPUState *c) static int kvm_arch_put_fpsimd(CPUState *cs) { CPUARMState *env =3D &ARM_CPU(cs)->env; - struct kvm_one_reg reg; int i, ret; =20 for (i =3D 0; i < 32; i++) { uint64_t *q =3D aa64_vfp_qreg(env, i); #if HOST_BIG_ENDIAN uint64_t fp_val[2] =3D { q[1], q[0] }; - reg.addr =3D (uintptr_t)fp_val; + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), + &fp_val); #else - reg.addr =3D (uintptr_t)q; + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), &q); #endif - reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; } @@ -758,14 +752,11 @@ static int kvm_arch_put_sve(CPUState *cs) CPUARMState *env =3D &cpu->env; uint64_t tmp[ARM_MAX_VQ * 2]; uint64_t *r; - struct kvm_one_reg reg; int n, ret; =20 for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { r =3D sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * = 2); - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_ZREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); if (ret) { return ret; } @@ -774,9 +765,7 @@ static int kvm_arch_put_sve(CPUState *cs) for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { r =3D sve_bswap64(tmp, r =3D &env->vfp.pregs[n].p[0], DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_PREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); if (ret) { return ret; } @@ -784,9 +773,7 @@ static int kvm_arch_put_sve(CPUState *cs) =20 r =3D sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_FFR(0); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); if (ret) { return ret; } @@ -796,7 +783,6 @@ static int kvm_arch_put_sve(CPUState *cs) =20 int kvm_arch_put_registers(CPUState *cs, int level) { - struct kvm_one_reg reg; uint64_t val; uint32_t fpr; int i, ret; @@ -813,9 +799,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) } =20 for (i =3D 0; i < 31; i++) { - reg.id =3D AARCH64_CORE_REG(regs.regs[i]); - reg.addr =3D (uintptr_t) &env->xregs[i]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); if (ret) { return ret; } @@ -826,16 +811,12 @@ int kvm_arch_put_registers(CPUState *cs, int level) */ aarch64_save_sp(env, 1); =20 - reg.id =3D AARCH64_CORE_REG(regs.sp); - reg.addr =3D (uintptr_t) &env->sp_el[0]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(sp_el1); - reg.addr =3D (uintptr_t) &env->sp_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); if (ret) { return ret; } @@ -846,23 +827,17 @@ int kvm_arch_put_registers(CPUState *cs, int level) } else { val =3D cpsr_read(env); } - reg.id =3D AARCH64_CORE_REG(regs.pstate); - reg.addr =3D (uintptr_t) &val; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(regs.pc); - reg.addr =3D (uintptr_t) &env->pc; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(elr_el1); - reg.addr =3D (uintptr_t) &env->elr_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); if (ret) { return ret; } @@ -881,9 +856,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) =20 /* KVM 0-4 map to QEMU banks 1-5 */ for (i =3D 0; i < KVM_NR_SPSR; i++) { - reg.id =3D AARCH64_CORE_REG(spsr[i]); - reg.addr =3D (uintptr_t) &env->banked_spsr[i + 1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); if (ret) { return ret; } @@ -898,18 +872,14 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 - reg.addr =3D (uintptr_t)(&fpr); fpr =3D vfp_get_fpsr(env); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { return ret; } =20 - reg.addr =3D (uintptr_t)(&fpr); fpr =3D vfp_get_fpcr(env); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 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Tue, 18 Jul 2023 07:14:31 -0400 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-343-63YcouFBNXmbrKigtV9tAA-1; Tue, 18 Jul 2023 07:14:20 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id BBC9A185A792; Tue, 18 Jul 2023 11:14:19 +0000 (UTC) Received: from gondolin.redhat.com (unknown [10.39.193.57]) by smtp.corp.redhat.com (Postfix) with ESMTP id B88C140C6F4C; Tue, 18 Jul 2023 11:14:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1689678866; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6VjQZ/VhQRFxeTlxCQ+F15BB8+mqTDYu8x6ynIEKQEU=; b=jApXnBq+NKTSyzBFSVwdObYJU2z1Zg+BJFgUedJBgQ+b7opq349gJualxpsGpdXvcgmYpf Oql3xwymLjt4Lp6J3XMZUpWG4g4WyPNoaFWIqiFDlJSF4f+4VQFbGFj+hmU5A8lTQEzRrz ux2IOgfHaYJmLGZEuIf96Y1NcyUVnL0= X-MC-Unique: 63YcouFBNXmbrKigtV9tAA-1 From: Cornelia Huck To: Peter Maydell , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Cornelia Huck Subject: [PATCH for-8.2 2/2] arm/kvm: convert to kvm_get_one_reg Date: Tue, 18 Jul 2023 13:14:04 +0200 Message-ID: <20230718111404.23479-3-cohuck@redhat.com> In-Reply-To: <20230718111404.23479-1-cohuck@redhat.com> References: <20230718111404.23479-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1689678939044100007 Content-Type: text/plain; charset="utf-8" We can neaten the code by switching the callers that work on a CPUstate to the kvm_get_one_reg function. Signed-off-by: Cornelia Huck Reviewed-by: Gavin Shan --- target/arm/kvm.c | 15 +++--------- target/arm/kvm64.c | 57 ++++++++++++---------------------------------- 2 files changed, 18 insertions(+), 54 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index cdbffc3c6e0d..4123f6dc9d72 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -525,24 +525,19 @@ bool write_kvmstate_to_list(ARMCPU *cpu) bool ok =3D true; =20 for (i =3D 0; i < cpu->cpreg_array_len; i++) { - struct kvm_one_reg r; uint64_t regidx =3D cpu->cpreg_indexes[i]; uint32_t v32; int ret; =20 - r.id =3D regidx; - switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: - r.addr =3D (uintptr_t)&v32; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + ret =3D kvm_get_one_reg(cs, regidx, &v32); if (!ret) { cpu->cpreg_values[i] =3D v32; } break; case KVM_REG_SIZE_U64: - r.addr =3D (uintptr_t)(cpu->cpreg_values + i); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + ret =3D kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); break; default: g_assert_not_reached(); @@ -678,17 +673,13 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) void kvm_arm_get_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM_TIMER_CNT, - .addr =3D (uintptr_t)&cpu->kvm_vtime, - }; int ret; =20 if (cpu->kvm_vtime_dirty) { return; } =20 - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); abort(); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b4d02dff5381..66b52d6f8d23 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -908,14 +908,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) static int kvm_arch_get_fpsimd(CPUState *cs) { CPUARMState *env =3D &ARM_CPU(cs)->env; - struct kvm_one_reg reg; int i, ret; =20 for (i =3D 0; i < 32; i++) { uint64_t *q =3D aa64_vfp_qreg(env, i); - reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr =3D (uintptr_t)q; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); if (ret) { return ret; } else { @@ -939,15 +936,12 @@ static int kvm_arch_get_sve(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - struct kvm_one_reg reg; uint64_t *r; int n, ret; =20 for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { r =3D &env->vfp.zregs[n].d[0]; - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_ZREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); if (ret) { return ret; } @@ -956,9 +950,7 @@ static int kvm_arch_get_sve(CPUState *cs) =20 for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { r =3D &env->vfp.pregs[n].p[0]; - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_PREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); if (ret) { return ret; } @@ -966,9 +958,7 @@ static int kvm_arch_get_sve(CPUState *cs) } =20 r =3D &env->vfp.pregs[FFR_PRED_NUM].p[0]; - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_FFR(0); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); if (ret) { return ret; } @@ -979,7 +969,6 @@ static int kvm_arch_get_sve(CPUState *cs) =20 int kvm_arch_get_registers(CPUState *cs) { - struct kvm_one_reg reg; uint64_t val; unsigned int el; uint32_t fpr; @@ -989,31 +978,24 @@ int kvm_arch_get_registers(CPUState *cs) CPUARMState *env =3D &cpu->env; =20 for (i =3D 0; i < 31; i++) { - reg.id =3D AARCH64_CORE_REG(regs.regs[i]); - reg.addr =3D (uintptr_t) &env->xregs[i]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); if (ret) { return ret; } } =20 - reg.id =3D AARCH64_CORE_REG(regs.sp); - reg.addr =3D (uintptr_t) &env->sp_el[0]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(sp_el1); - reg.addr =3D (uintptr_t) &env->sp_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(regs.pstate); - reg.addr =3D (uintptr_t) &val; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); if (ret) { return ret; } @@ -1030,9 +1012,7 @@ int kvm_arch_get_registers(CPUState *cs) */ aarch64_restore_sp(env, 1); =20 - reg.id =3D AARCH64_CORE_REG(regs.pc); - reg.addr =3D (uintptr_t) &env->pc; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); if (ret) { return ret; } @@ -1046,9 +1026,7 @@ int kvm_arch_get_registers(CPUState *cs) aarch64_sync_64_to_32(env); } =20 - reg.id =3D AARCH64_CORE_REG(elr_el1); - reg.addr =3D (uintptr_t) &env->elr_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); if (ret) { return ret; } @@ -1058,9 +1036,8 @@ int kvm_arch_get_registers(CPUState *cs) * KVM SPSRs 0-4 map to QEMU banks 1-5 */ for (i =3D 0; i < KVM_NR_SPSR; i++) { - reg.id =3D AARCH64_CORE_REG(spsr[i]); - reg.addr =3D (uintptr_t) &env->banked_spsr[i + 1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); if (ret) { return ret; } @@ -1081,17 +1058,13 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } =20 - reg.addr =3D (uintptr_t)(&fpr); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { return ret; } vfp_set_fpsr(env, fpr); =20 - reg.addr =3D (uintptr_t)(&fpr); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); if (ret) { return ret; } --=20 2.41.0