From nobody Mon May 20 14:32:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16895087845961002.8218521141008; Sun, 16 Jul 2023 04:59:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qL0OL-0004D2-Td; Sun, 16 Jul 2023 07:58:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OJ-0004CX-Sn; Sun, 16 Jul 2023 07:58:19 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OI-0001r5-1o; Sun, 16 Jul 2023 07:58:19 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id CCB4714246; Sun, 16 Jul 2023 14:58:24 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id BE2DF14F2F; Sun, 16 Jul 2023 14:58:04 +0300 (MSK) Received: (nullmailer pid 1505318 invoked by uid 1000); Sun, 16 Jul 2023 11:58:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Daniel Henrique Barboza , Alistair Francis , Michael Tokarev Subject: [PATCH 1/6] docs/system/target-riscv.rst: tidy CPU firmware section Date: Sun, 16 Jul 2023 14:57:56 +0300 Message-Id: <20230716115801.1505288-2-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230716115801.1505288-1-mjt@tls.msk.ru> References: <20230716115801.1505288-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1689508787026100011 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This is how the content of the "RISC-V CPU firmware" section is displayed after the html is generated: "When using the sifive_u or virt machine there are three different firmware boot options: 1. -bios default - This is the default behaviour if no -bios option is included. (...) 3. -bios - Tells QEMU to load the specified file as the firmware." It's all in the same paragraph, in a numbered list, and no special formatting for the options. Tidy it a bit by adding line breaks between items and its description. Remove the numbered list. And apply formatting for the options cited in the middle of the text. Cc: qemu-trivial@nongnu.org Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Michael Tokarev --- docs/system/target-riscv.rst | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 89a866e4f4..ba195f1518 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -76,11 +76,19 @@ RISC-V CPU firmware =20 When using the ``sifive_u`` or ``virt`` machine there are three different firmware boot options: -1. ``-bios default`` - This is the default behaviour if no -bios option -is included. This option will load the default OpenSBI firmware automatica= lly. -The firmware is included with the QEMU release and no user interaction is -required. All a user needs to do is specify the kernel they want to boot -with the -kernel option -2. ``-bios none`` - QEMU will not automatically load any firmware. It is up -to the user to load all the images they need. -3. ``-bios `` - Tells QEMU to load the specified file as the firmwar= e. + +* ``-bios default`` + +This is the default behaviour if no ``-bios`` option is included. This opt= ion +will load the default OpenSBI firmware automatically. The firmware is incl= uded +with the QEMU release and no user interaction is required. All a user need= s to +do is specify the kernel they want to boot with the ``-kernel`` option + +* ``-bios none`` + +QEMU will not automatically load any firmware. It is up to the user to loa= d all +the images they need. + +* ``-bios `` + +Tells QEMU to load the specified file as the firmware. --=20 2.39.2 From nobody Mon May 20 14:32:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168950878347635.04940041671432; Sun, 16 Jul 2023 04:59:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qL0OO-0004Ej-SX; Sun, 16 Jul 2023 07:58:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0ON-0004E4-6S; Sun, 16 Jul 2023 07:58:23 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OL-0001sN-8N; Sun, 16 Jul 2023 07:58:22 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id EB7FB14247; Sun, 16 Jul 2023 14:58:24 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id EAF8214F30; Sun, 16 Jul 2023 14:58:04 +0300 (MSK) Received: (nullmailer pid 1505321 invoked by uid 1000); Sun, 16 Jul 2023 11:58:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev , Fabiano Rosas Subject: [PATCH 2/6] tree-wide spelling fixes in comments and some messages: migration/ Date: Sun, 16 Jul 2023 14:57:57 +0300 Message-Id: <20230716115801.1505288-3-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230716115801.1505288-1-mjt@tls.msk.ru> References: <20230716115801.1505288-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1689508784871100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Fabiano Rosas --- migration/migration-stats.c | 2 +- migration/migration.h | 4 ++-- migration/multifd-zlib.c | 2 +- migration/multifd-zstd.c | 2 +- migration/multifd.c | 2 +- migration/savevm.c | 2 +- migration/trace-events | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/migration/migration-stats.c b/migration/migration-stats.c index f98c8260be..095d6d75bb 100644 --- a/migration/migration-stats.c +++ b/migration/migration-stats.c @@ -48,7 +48,7 @@ uint64_t migration_rate_get(void) void migration_rate_set(uint64_t limit) { /* - * 'limit' is per second. But we check it each BUFER_DELAY milisecond= s. + * 'limit' is per second. But we check it each BUFFER_DELAY milliseco= nds. */ stat64_set(&mig_stats.rate_limit_max, limit / XFER_LIMIT_RATIO); } diff --git a/migration/migration.h b/migration/migration.h index b7c8b67542..6eea18db36 100644 --- a/migration/migration.h +++ b/migration/migration.h @@ -134,7 +134,7 @@ struct MigrationIncomingState { /* * Always set by the main vm load thread only, but can be read by the * postcopy preempt thread. "volatile" makes sure all reads will be - * uptodate across cores. + * up-to-date across cores. */ volatile PreemptThreadStatus preempt_thread_status; /* @@ -409,7 +409,7 @@ struct MigrationState { * channel itself. * * - postcopy preempt channel will be created at the switching phase - * from precopy -> postcopy (to avoid race condtion of misordered + * from precopy -> postcopy (to avoid race condition of misordered * creation of channels). * * NOTE: See message-id on qemu-devel diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index 81701250ad..37ce48621e 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -57,7 +57,7 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **= errp) err_msg =3D "deflate init failed"; goto err_free_z; } - /* This is the maxium size of the compressed buffer */ + /* This is the maximum size of the compressed buffer */ z->zbuff_len =3D compressBound(MULTIFD_PACKET_SIZE); z->zbuff =3D g_try_malloc(z->zbuff_len); if (!z->zbuff) { diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index d1d29e76cc..b471daadcd 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -68,7 +68,7 @@ static int zstd_send_setup(MultiFDSendParams *p, Error **= errp) p->id, ZSTD_getErrorName(res)); return -1; } - /* This is the maxium size of the compressed buffer */ + /* This is the maximum size of the compressed buffer */ z->zbuff_len =3D ZSTD_compressBound(MULTIFD_PACKET_SIZE); z->zbuff =3D g_try_malloc(z->zbuff_len); if (!z->zbuff) { diff --git a/migration/multifd.c b/migration/multifd.c index 3387d8277f..0e3ae87449 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -878,7 +878,7 @@ static void multifd_new_send_channel_cleanup(MultiFDSen= dParams *p, qemu_sem_post(&p->sem_sync); /* * Although multifd_send_thread is not created, but main migration - * thread neet to judge whether it is running, so we need to mark + * thread need to judge whether it is running, so we need to mark * its status. */ p->quit =3D true; diff --git a/migration/savevm.c b/migration/savevm.c index 95c2abf47c..51e40e3a0b 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -117,7 +117,7 @@ static struct mig_cmd_args { * The format of arguments is depending on postcopy mode: * - postcopy RAM only * uint64_t host page size - * uint64_t taget page size + * uint64_t target page size * * - postcopy RAM and postcopy dirty bitmaps * format is the same as for postcopy RAM only diff --git a/migration/trace-events b/migration/trace-events index 5259c1044b..4e43fe20fc 100644 --- a/migration/trace-events +++ b/migration/trace-events @@ -184,7 +184,7 @@ source_return_path_thread_shut(uint32_t val) "0x%x" source_return_path_thread_resume_ack(uint32_t v) "%"PRIu32 source_return_path_thread_switchover_acked(void) "" migration_thread_low_pending(uint64_t pending) "%" PRIu64 -migrate_transferred(uint64_t tranferred, uint64_t time_spent, uint64_t ban= dwidth, uint64_t size) "transferred %" PRIu64 " time_spent %" PRIu64 " band= width %" PRIu64 " max_size %" PRId64 +migrate_transferred(uint64_t transferred, uint64_t time_spent, uint64_t ba= ndwidth, uint64_t size) "transferred %" PRIu64 " time_spent %" PRIu64 " ban= dwidth %" PRIu64 " max_size %" PRId64 process_incoming_migration_co_end(int ret, int ps) "ret=3D%d postcopy-stat= e=3D%d" process_incoming_migration_co_postcopy_end_main(void) "" postcopy_preempt_enabled(bool value) "%d" --=20 2.39.2 From nobody Mon May 20 14:32:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1689508745003532.5164068794033; Sun, 16 Jul 2023 04:59:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qL0OQ-0004FE-59; Sun, 16 Jul 2023 07:58:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0ON-0004EC-H3; Sun, 16 Jul 2023 07:58:23 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OL-0001sX-I7; Sun, 16 Jul 2023 07:58:23 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 2224514248; Sun, 16 Jul 2023 14:58:25 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 1D93F14F31; Sun, 16 Jul 2023 14:58:05 +0300 (MSK) Received: (nullmailer pid 1505324 invoked by uid 1000); Sun, 16 Jul 2023 11:58:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev , Thomas Huth Subject: [PATCH 3/6] tree-wide spelling fixes in comments and some messages: s390x Date: Sun, 16 Jul 2023 14:57:58 +0300 Message-Id: <20230716115801.1505288-4-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230716115801.1505288-1-mjt@tls.msk.ru> References: <20230716115801.1505288-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1689508749142100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Thomas Huth --- hw/intc/s390_flic_kvm.c | 2 +- include/hw/s390x/s390-pci-bus.h | 2 +- include/hw/s390x/sclp.h | 2 +- target/s390x/cpu_features.c | 2 +- target/s390x/cpu_models.c | 2 +- target/s390x/tcg/fpu_helper.c | 2 +- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/translate.c | 2 +- tests/tcg/s390x/mvc.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c index 4e86d2d436..28364b22d6 100644 --- a/hw/intc/s390_flic_kvm.c +++ b/hw/intc/s390_flic_kvm.c @@ -380,7 +380,7 @@ static void kvm_s390_release_adapter_routes(S390FLICSta= te *fs, * @size: ignored * * Note: Pass buf and len to kernel. Start with one page and - * increase until buffer is sufficient or maxium size is + * increase until buffer is sufficient or maximum size is * reached */ static int kvm_flic_save(QEMUFile *f, void *opaque, size_t size, diff --git a/include/hw/s390x/s390-pci-bus.h b/include/hw/s390x/s390-pci-bu= s.h index e0a9f9385b..b1bdbeaeb5 100644 --- a/include/hw/s390x/s390-pci-bus.h +++ b/include/hw/s390x/s390-pci-bus.h @@ -184,7 +184,7 @@ enum ZpciIoatDtype { * The following states make up the "configured" meta-state: * disabled: device is configured but not enabled; transition between this * state and enabled via clp enable/disable - * enbaled: device is ready for use; transition to disabled via clp disabl= e; + * enabled: device is ready for use; transition to disabled via clp disabl= e; * may enter an error state * blocked: ignore all DMA and interrupts; transition back to enabled or f= rom * error state via mpcifc diff --git a/include/hw/s390x/sclp.h b/include/hw/s390x/sclp.h index d3ade40a5a..cf1f2efae2 100644 --- a/include/hw/s390x/sclp.h +++ b/include/hw/s390x/sclp.h @@ -87,7 +87,7 @@ * - we work on a private copy of the SCCB, since there are several length * fields, that would cause a security nightmare if we allow the guest to * alter the structure while we parse it. We cannot use ldl_p and friends - * either without doing pointer arithmetics + * either without doing pointer arithmetic * So we have to double check that all users of sclp data structures use t= he * right endianness wrappers. */ diff --git a/target/s390x/cpu_features.c b/target/s390x/cpu_features.c index ebb155ce1c..d28eb65845 100644 --- a/target/s390x/cpu_features.c +++ b/target/s390x/cpu_features.c @@ -249,7 +249,7 @@ static void init_groups(void) { int i; =20 - /* init all bitmaps from gnerated data initially */ + /* init all bitmaps from generated data initially */ for (i =3D 0; i < ARRAY_SIZE(s390_feature_groups); i++) { s390_init_feat_bitmap(s390_feature_groups[i].init, s390_feature_groups[i].feat); diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 42b52afdb4..91ce896491 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -975,7 +975,7 @@ static void register_types(void) =20 init_ignored_base_feat(); =20 - /* init all bitmaps from gnerated data initially */ + /* init all bitmaps from generated data initially */ s390_init_feat_bitmap(qemu_max_init, qemu_max_cpu_feat); for (i =3D 0; i < ARRAY_SIZE(s390_cpu_defs); i++) { s390_init_feat_bitmap(s390_cpu_defs[i].base_init, diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 4b7fa58af3..5364372c8b 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -86,7 +86,7 @@ static void handle_exceptions(CPUS390XState *env, bool Xx= C, uintptr_t retaddr) =20 /* * FIXME: - * 1. Right now, all inexact conditions are inidicated as + * 1. Right now, all inexact conditions are indicated as * "truncated" (0) and never as "incremented" (1) in the DXC. * 2. Only traps due to invalid/divbyzero are suppressing. Other traps * are completing, meaning the target register has to be written! diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 457ed25d2f..555c147c7c 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -529,7 +529,7 @@ /* LOAD LOGICAL HALFWORD RELATIVE LONG */ C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0) C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0) -/* LOAD LOGICAL IMMEDATE */ +/* LOAD LOGICAL IMMEDIATE */ D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32) D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0) D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 6661b27efa..94c8c1f9aa 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -429,7 +429,7 @@ static void gen_exception(int excp) =20 static void gen_program_exception(DisasContext *s, int code) { - /* Remember what pgm exeption this was. */ + /* Remember what pgm exception this was. */ tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, offsetof(CPUS390XState, int_pgm_code)); =20 diff --git a/tests/tcg/s390x/mvc.c b/tests/tcg/s390x/mvc.c index 7ae4c44550..b572aa3ced 100644 --- a/tests/tcg/s390x/mvc.c +++ b/tests/tcg/s390x/mvc.c @@ -85,7 +85,7 @@ int main(void) } } =20 - /* test if MVC works now correctly accross page boundaries */ + /* test if MVC works now correctly across page boundaries */ mvc_256(dst + 4096 - 128, src + 4096 - 128); for (i =3D 0; i < ALLOC_SIZE; i++) { if (src[i] !=3D 0xff) { --=20 2.39.2 From nobody Mon May 20 14:32:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1689508764808846.7192610974417; Sun, 16 Jul 2023 04:59:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qL0OT-0004G2-EI; Sun, 16 Jul 2023 07:58:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OR-0004Fa-9i; Sun, 16 Jul 2023 07:58:27 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OO-0001t8-Hs; Sun, 16 Jul 2023 07:58:27 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 5126314249; Sun, 16 Jul 2023 14:58:25 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 4865114F32; Sun, 16 Jul 2023 14:58:05 +0300 (MSK) Received: (nullmailer pid 1505327 invoked by uid 1000); Sun, 16 Jul 2023 11:58:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev , Peter Maydell Subject: [PATCH 4/6] tree-wide spelling fixes in comments and some messages: arm Date: Sun, 16 Jul 2023 14:57:59 +0300 Message-Id: <20230716115801.1505288-5-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230716115801.1505288-1-mjt@tls.msk.ru> References: <20230716115801.1505288-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1689508768699100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Peter Maydell --- host/include/aarch64/host/cpuinfo.h | 2 +- hw/arm/aspeed.c | 2 +- hw/arm/mps2-tz.c | 2 +- hw/intc/arm_gic.c | 4 ++-- hw/intc/arm_gicv3_redist.c | 2 +- hw/intc/armv7m_nvic.c | 2 +- hw/misc/allwinner-r40-dramc.c | 2 +- hw/misc/exynos4210_rng.c | 2 +- include/hw/arm/fsl-imx7.h | 2 +- include/hw/intc/armv7m_nvic.h | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu.h | 2 +- target/arm/cpu64.c | 2 +- target/arm/helper.c | 4 ++-- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/translate-a64.c | 4 ++-- target/arm/tcg/translate-mve.c | 4 ++-- target/arm/tcg/translate-sve.c | 2 +- target/arm/tcg/translate-vfp.c | 2 +- target/arm/tcg/vec_helper.c | 2 +- tests/tcg/aarch64/gdbstub/test-sve.py | 2 +- tests/tcg/aarch64/sme-outprod1.c | 2 +- tests/tcg/aarch64/system/boot.S | 6 +++--- tests/tcg/aarch64/system/semiheap.c | 2 +- 24 files changed, 30 insertions(+), 30 deletions(-) diff --git a/host/include/aarch64/host/cpuinfo.h b/host/include/aarch64/hos= t/cpuinfo.h index 05feeb4f43..769626b098 100644 --- a/host/include/aarch64/host/cpuinfo.h +++ b/host/include/aarch64/host/cpuinfo.h @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for AArch64. + * Host specific cpu identification for AArch64. */ =20 #ifndef HOST_CPUINFO_H diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 6880998484..263626abea 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1565,7 +1565,7 @@ static void ast1030_evb_i2c_init(AspeedMachineState *= bmc) { AspeedSoCState *soc =3D &bmc->soc; =20 - /* U10 24C08 connects to SDA/SCL Groupt 1 by default */ + /* U10 24C08 connects to SDA/SCL Group 1 by default */ uint8_t *eeprom_buf =3D g_malloc0(32 * 1024); smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_b= uf); =20 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 07aecd9497..5873107302 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -1205,7 +1205,7 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uin= t32_t address, { /* * The MPS2 TZ FPGA images have IDAUs in them which are connected to - * the Master Security Controllers. Thes have the same logic as + * the Master Security Controllers. These have the same logic as * is used by the IoTKit for the IDAU connected to the CPU, except * that MSCs don't care about the NSC attribute. */ diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 7a34bc0998..074cf50af2 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -239,7 +239,7 @@ static inline bool gic_lr_entry_is_free(uint32_t entry) } =20 /* Return true if this LR should trigger an EOI maintenance interrupt, i.e= . the - * corrsponding bit in EISR is set. + * corresponding bit in EISR is set. */ static inline bool gic_lr_entry_is_eoi(uint32_t entry) { @@ -1333,7 +1333,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, =20 /* ??? This currently clears the pending bit for all CPUs, even for per-CPU interrupts. It's unclear whether this is the - corect behavior. */ + correct behavior. */ if (value & (1 << i)) { GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 297f7f0263..8153525849 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -494,7 +494,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwadd= r offset, /* Only the ProcessorSleep bit is writable. When the guest sets * it, it requests that we transition the channel between the * redistributor and the cpu interface to quiescent, and that - * we set the ChildrenAsleep bit once the inteface has reached the + * we set the ChildrenAsleep bit once the interface has reached the * quiescent state. * Setting the ProcessorSleep to 0 reverses the quiescing, and * ChildrenAsleep is cleared once the transition is complete. diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 63afe1fdf5..03b6b8c986 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -894,7 +894,7 @@ int armv7m_nvic_complete_irq(NVICState *s, int irq, boo= l secure) vec->active =3D 0; if (vec->level) { /* Re-pend the exception if it's still held high; only - * happens for extenal IRQs + * happens for external IRQs */ assert(irq >=3D NVIC_FIRST_IRQ); vec->pending =3D 1; diff --git a/hw/misc/allwinner-r40-dramc.c b/hw/misc/allwinner-r40-dramc.c index ea6124744f..6944f84455 100644 --- a/hw/misc/allwinner-r40-dramc.c +++ b/hw/misc/allwinner-r40-dramc.c @@ -368,7 +368,7 @@ static const MemoryRegionOps allwinner_r40_detect_ops = =3D { =20 /* * mctl_r40_detect_rank_count in u-boot will write the high 1G of DDR - * to detect wether the board support dual_rank or not. Create a virtual m= emory + * to detect whether the board support dual_rank or not. Create a virtual = memory * if the board's ram_size less or equal than 1G, and set read time out fl= ag of * REG_DRAMCTL_PGSR when the user touch this high dram. */ diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c index 1b9e8347a1..9214ec14cc 100644 --- a/hw/misc/exynos4210_rng.c +++ b/hw/misc/exynos4210_rng.c @@ -1,5 +1,5 @@ /* - * Exynos4210 Pseudo Random Nubmer Generator Emulation + * Exynos4210 Pseudo Random Number Generator Emulation * * Copyright (c) 2017 Krzysztof Kozlowski * diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 54ea2f0890..fcce6421c8 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -165,7 +165,7 @@ enum FslIMX7MemoryMap { * Some versions of the reference manual claim that UART2 is @ * 0x30870000, but experiments with HW + DT files in upstream * Linux kernel show that not to be true and that block is - * acutally located @ 0x30890000 + * actually located @ 0x30890000 */ FSL_IMX7_UART2_ADDR =3D 0x30890000, FSL_IMX7_UART3_ADDR =3D 0x30880000, diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 1ca262fbf8..6b4ae566c9 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -74,7 +74,7 @@ struct NVICState { */ bool vectpending_is_s_banked; int exception_prio; /* group prio of the highest prio active exception= */ - int vectpending_prio; /* group prio of the exeception in vectpending */ + int vectpending_prio; /* group prio of the exception in vectpending */ =20 MemoryRegion sysregmem; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 69e2bde3c2..93c28d50e5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -677,7 +677,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, } =20 /* - * The PSTATE bits only mask the interrupt if we have not overriden the + * The PSTATE bits only mask the interrupt if we have not overridden t= he * ability above. */ return unmasked || pstate_unmasked; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d6c0f95d5..88e5accda6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2592,7 +2592,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, i= nt el) return aa64; } =20 -/* Function for determing whether guest cp register reads and writes should +/* Function for determining whether guest cp register reads and writes sho= uld * access the secure or non-secure bank of a cp register. When EL3 is * operating in AArch32 state, the NS-bit determines whether the secure * instance of a cp register should be used. When EL3 is AArch64 (or if diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6012e4ef54..96158093cc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -95,7 +95,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) =20 if (kvm_enabled()) { /* - * For KVM we have to automatically enable all supported uniti= alized + * For KVM we have to automatically enable all supported unini= tialized * lengths, even when the smaller lengths are not all powers-o= f-two. */ vq_map |=3D vq_supported & ~vq_init & vq_mask; diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e836aaee1..50f61e42ca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1674,7 +1674,7 @@ static void pmevtyper_rawwrite(CPUARMState *env, cons= t ARMCPRegInfo *ri, * pmevtyper_rawwrite is called between a pair of pmu_op_start and * pmu_op_finish calls when loading saved state for a migration. Becau= se * we're potentially updating the type of event here, the value writte= n to - * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a + * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a * different counter type. Therefore, we need to set this value to the * current count for the counter type we're writing so that pmu_op_fin= ish * has the correct count for its calculation. @@ -7009,7 +7009,7 @@ static const ARMCPRegInfo rme_reginfo[] =3D { /* * QEMU does not have a way to invalidate by physical address, thus * invalidating a range of physical addresses is accomplished by - * flushing all tlb entries in the outer sharable domain, + * flushing all tlb entries in the outer shareable domain, * just like PAALLOS. */ { .name =3D "TLBI_RPALOS", .state =3D ARM_CP_STATE_AA64, diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 9cef70e5c9..0045c18f80 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -148,7 +148,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr= , uint32_t op) * R: 0 because unpriv and A flag not set * SRVALID: 0 because NS * MRVALID: 0 because unpriv and A flag not set - * SREGION: 0 becaus SRVALID is 0 + * SREGION: 0 because SRVALID is 0 * MREGION: 0 because MRVALID is 0 */ return 0; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7d0c8f79a7..ef0c47407a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -182,7 +182,7 @@ void gen_a64_update_pc(DisasContext *s, target_long dif= f) * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 - * and TBI1 controls addressses with bit 55 =3D=3D 1. + * and TBI1 controls addresses with bit 55 =3D=3D 1. * If the appropriate TBI bit is set for the address then * the address is sign-extended from bit 55 into bits [63:56] * @@ -2313,7 +2313,7 @@ static void handle_sys(DisasContext *s, bool isread, =20 if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* - * A write to any coprocessor regiser that ends a TB + * A write to any coprocessor register that ends a TB * must rebuild the hflags for the next TB. */ gen_rebuild_hflags(s); diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index bbc7b3f4ce..17d8e6804e 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -2182,7 +2182,7 @@ static bool trans_VMOV_to_2gp(DisasContext *s, arg_VM= OV_to_2gp *a) * execution if it is not in an IT block. For us this means * only that if PSR.ECI says we should not be executing the beat * corresponding to the lane of the vector register being accessed - * then we should skip perfoming the move, and that we need to do + * then we should skip performing the move, and that we need to do * the usual check for bad ECI state and advance of ECI state. * (If PSR.ECI is non-zero then we cannot be in an IT block.) */ @@ -2225,7 +2225,7 @@ static bool trans_VMOV_from_2gp(DisasContext *s, arg_= VMOV_to_2gp *a) * execution if it is not in an IT block. For us this means * only that if PSR.ECI says we should not be executing the beat * corresponding to the lane of the vector register being accessed - * then we should skip perfoming the move, and that we need to do + * then we should skip performing the move, and that we need to do * the usual check for bad ECI state and advance of ECI state. * (If PSR.ECI is non-zero then we cannot be in an IT block.) */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 8350a65f31..2ba5efadfd 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -1841,7 +1841,7 @@ TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_h= elper_sve_pnext) =20 /* Perform an inline saturating addition of a 32-bit value within * a 64-bit register. The second operand is known to be positive, - * which halves the comparisions we must perform to bound the result. + * which halves the comparisons we must perform to bound the result. */ static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) { diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 359b1e3e96..d3e89fda91 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -144,7 +144,7 @@ static void gen_preserve_fp_state(DisasContext *s, bool= skip_context_update) * Generate code for M-profile FP context handling: update the * ownership of the FP context, and create a new context if * necessary. This corresponds to the parts of the pseudocode - * ExecuteFPCheck() after the inital PreserveFPState() call. + * ExecuteFPCheck() after the initial PreserveFPState() call. */ static void gen_update_fp_context(DisasContext *s) { diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index f59d3b26ea..6712a2c790 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2626,7 +2626,7 @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm= , void *va, uint32_t desc) * Process the entire segment at once, writing back the * results only after we've consumed all of the inputs. * - * Key to indicies by column: + * Key to indices by column: * i j i k j k */ sum00 =3D a[s + H4(0 + 0)]; diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbs= tub/test-sve.py index b96bdbb99a..ef57c7412c 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve.py +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -1,6 +1,6 @@ from __future__ import print_function # -# Test the SVE registers are visable and changeable via gdbstub +# Test the SVE registers are visible and changeable via gdbstub # # This is launched via tests/guest-debug/run-test.py # diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outpr= od1.c index 6e5972d75e..0c814ed529 100644 --- a/tests/tcg/aarch64/sme-outprod1.c +++ b/tests/tcg/aarch64/sme-outprod1.c @@ -28,7 +28,7 @@ asm( " fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n" /* * Read the first 4x4 sub-matrix of elements from tile 1: - * Note that za1h should be interchangable here. + * Note that za1h should be interchangeable here. */ " mov w12, #0\n" " mova z0.s, p0/m, za1v.s[w12, #0]\n" diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boo= t.S index f136363d2a..501685d0ec 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -9,7 +9,7 @@ =20 /* * Semihosting interface on ARM AArch64 - * See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM + * See "Semihosting for AArch32 and AArch64 Release 2.0" by ARM * w0 - semihosting call number * x1 - semihosting parameter */ @@ -147,7 +147,7 @@ __start: * T0SZ[5:0] =3D 2^(64 - 25) * * The size of T0SZ controls what the initial lookup level. It - * would be nice to start at level 2 but unfortunatly for a + * would be nice to start at level 2 but unfortunately for a * flat-mapping on the virt machine we need to handle IA's * with at least 1gb range to see RAM. So we start with a * level 1 lookup. @@ -189,7 +189,7 @@ __start: msr cpacr_el1, x0 =20 /* Setup some stack space and enter the test code. - * Assume everthing except the return value is garbage when we + * Assume everything except the return value is garbage when we * return, we won't need it. */ adrp x0, stack_end diff --git a/tests/tcg/aarch64/system/semiheap.c b/tests/tcg/aarch64/system= /semiheap.c index 693a1b037d..1a8c0f31a0 100644 --- a/tests/tcg/aarch64/system/semiheap.c +++ b/tests/tcg/aarch64/system/semiheap.c @@ -86,7 +86,7 @@ int main(int argc, char *argv[argc]) } ptr_to_heap++; } - ml_printf("r/w to heap upto %p\n", ptr_to_heap); + ml_printf("r/w to heap up to %p\n", ptr_to_heap); =20 ml_printf("Passed HeapInfo checks\n"); return 0; --=20 2.39.2 From nobody Mon May 20 14:32:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1689508786005174.38680982004087; Sun, 16 Jul 2023 04:59:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qL0OV-0004Gj-4r; Sun, 16 Jul 2023 07:58:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OT-0004G3-9U; Sun, 16 Jul 2023 07:58:29 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OO-0001tG-U4; Sun, 16 Jul 2023 07:58:29 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 91A801424A; Sun, 16 Jul 2023 14:58:25 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 76A9314F33; Sun, 16 Jul 2023 14:58:05 +0300 (MSK) Received: (nullmailer pid 1505330 invoked by uid 1000); Sun, 16 Jul 2023 11:58:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev , Peter Maydell Subject: [PATCH 5/6] tree-wide spelling fixes in comments and some messages: other architectures Date: Sun, 16 Jul 2023 14:58:00 +0300 Message-Id: <20230716115801.1505288-6-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230716115801.1505288-1-mjt@tls.msk.ru> References: <20230716115801.1505288-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1689508787059100013 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Peter Maydell --- host/include/generic/host/cpuinfo.h | 2 +- hw/m68k/next-cube.c | 2 +- hw/m68k/next-kbd.c | 2 +- hw/m68k/virt.c | 2 +- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/sparc/sun4m_iommu.c | 8 ++++---- target/alpha/cpu.h | 4 ++-- target/alpha/translate.c | 2 +- target/cris/helper.c | 6 +++--- target/cris/op_helper.c | 2 +- target/cris/translate.c | 16 ++++++++-------- target/hppa/cpu.h | 4 ++-- target/hppa/int_helper.c | 2 +- target/hppa/translate.c | 2 +- target/loongarch/cpu-csr.h | 2 +- target/m68k/helper.c | 4 ++-- target/microblaze/cpu.h | 2 +- target/openrisc/cpu.h | 2 +- target/openrisc/translate.c | 4 ++-- target/rx/translate.c | 4 ++-- target/sparc/asi.h | 14 +++++++------- target/tricore/csfr.h.inc | 2 +- target/tricore/helper.c | 2 +- target/tricore/translate.c | 8 ++++---- tests/tcg/Makefile.target | 4 ++-- tests/tcg/multiarch/sha512.c | 2 +- .../tcg/multiarch/system/Makefile.softmmu-target | 2 +- tests/tcg/tricore/c/crt0-tc2x.S | 4 ++-- tests/tcg/x86_64/system/boot.S | 4 ++-- 29 files changed, 58 insertions(+), 58 deletions(-) diff --git a/host/include/generic/host/cpuinfo.h b/host/include/generic/hos= t/cpuinfo.h index eca672064a..67ad410871 100644 --- a/host/include/generic/host/cpuinfo.h +++ b/host/include/generic/host/cpuinfo.h @@ -1,4 +1,4 @@ /* - * No host specific cpu indentification. + * No host specific cpu identification. * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index ce8ee50b9e..5d244b3b95 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -734,7 +734,7 @@ static void next_irq(void *opaque, int number, int leve= l) M68kCPU *cpu =3D s->cpu; int shift =3D 0; =20 - /* first switch sets interupt status */ + /* first switch sets interrupt status */ /* DPRINTF("IRQ %i\n",number); */ switch (number) { /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c index 0544160e91..0c348c18cf 100644 --- a/hw/m68k/next-kbd.c +++ b/hw/m68k/next-kbd.c @@ -37,7 +37,7 @@ =20 OBJECT_DECLARE_SIMPLE_TYPE(NextKBDState, NEXTKBD) =20 -/* following defintions from next68k netbsd */ +/* following definitions from next68k netbsd */ #define CSR_INT 0x00800000 #define CSR_DATA 0x00400000 =20 diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c index 731205b215..de91726cf9 100644 --- a/hw/m68k/virt.c +++ b/hw/m68k/virt.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later * - * QEMU Vitual M68K Machine + * QEMU Virtual M68K Machine * * (c) 2020 Laurent Vivier * diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index a24fadddca..babb053035 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -104,7 +104,7 @@ petalogix_ml605_init(MachineState *machine) =20 dinfo =3D drive_get(IF_PFLASH, 0, 0); /* 5th parameter 2 means bank-width - * 10th paremeter 0 means little-endian */ + * 10th parameter 0 means little-endian */ pflash_cfi01_register(FLASH_BASEADDR, "petalogix_ml605.flash", FLASH_S= IZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0); diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 71f5465249..eb40f9377c 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -96,10 +96,10 @@ #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ #define IOMMU_AER_MASK 0x801f000f =20 -#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ -#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ -#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ -#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ +#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configuration per-slot */ +#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configuration per-slot */ +#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configuration per-slot */ +#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configuration per-slot */ #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */ #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index fcd20bfd3a..13306665af 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -191,7 +191,7 @@ enum { =20 That said, we're only emulating Unix PALcode, and not attempting VMS, so we don't need to implement Executive and Supervisor. QEMU's own - PALcode cheats and usees the KSEG mapping for its code+data rather than + PALcode cheats and uses the KSEG mapping for its code+data rather than physical addresses. */ =20 #define MMU_KERNEL_IDX 0 @@ -362,7 +362,7 @@ enum { The Unix PALcode only uses bit 4. */ #define PS_USER_MODE 8u =20 -/* CPUAlphaState->flags constants. These are layed out so that we +/* CPUAlphaState->flags constants. These are laid out so that we can set or reset the pieces individually by assigning to the byte, or manipulated as a whole. */ =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 1f7dd078d8..846f3d8091 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2893,7 +2893,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) the first fp insn of the TB. Alternately we could define a proper default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure to reset the FP_STATUS to that default at the end of any TB that - changes the default. We could even (gasp) dynamiclly figure out + changes the default. We could even (gasp) dynamically figure out what default would be most efficient given the running program. */ ctx->tb_rm =3D -1; /* Similarly for flush-to-zero. */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 81a72699b5..c0bf987e3e 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -113,7 +113,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); switch (cs->exception_index) { case EXCP_BREAK: - /* These exceptions are genereated by the core itself. + /* These exceptions are generated by the core itself. ERP should point to the insn following the brk. */ ex_vec =3D env->trap_vector; env->pregs[PRV10_BRP] =3D env->pc; @@ -169,7 +169,7 @@ void cris_cpu_do_interrupt(CPUState *cs) =20 switch (cs->exception_index) { case EXCP_BREAK: - /* These exceptions are genereated by the core itself. + /* These exceptions are generated by the core itself. ERP should point to the insn following the brk. */ ex_vec =3D env->trap_vector; env->pregs[PR_ERP] =3D env->pc; @@ -228,7 +228,7 @@ void cris_cpu_do_interrupt(CPUState *cs) undefined. */ env->pc =3D cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4); =20 - /* Clear the excption_index to avoid spurios hw_aborts for recursive + /* Clear the excption_index to avoid spurious hw_aborts for recursive bus faults. */ cs->exception_index =3D -1; =20 diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index d55a18a213..40cb74ce73 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -231,7 +231,7 @@ static inline uint32_t evaluate_flags_writeback(CPUCRIS= State *env, { unsigned int x, z, mask; =20 - /* Extended arithmetics, leave the z flag alone. */ + /* Extended arithmetic, leave the z flag alone. */ x =3D env->cc_x; mask =3D env->cc_mask | X_FLAG; if (x) { diff --git a/target/cris/translate.c b/target/cris/translate.c index 1445cd8bb5..0b3d724281 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -342,7 +342,7 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TC= Gv ccs) tcg_gen_add_tl(d, d, t); } =20 -/* Extended arithmetics on CRIS. */ +/* Extended arithmetic on CRIS. */ static inline void t_gen_add_flag(TCGv d, int flag) { TCGv c; @@ -646,7 +646,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, switch (op) { case CC_OP_ADD: tcg_gen_add_tl(dst, a, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_addx_carry(dc, dst); break; case CC_OP_ADDC: @@ -659,7 +659,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, break; case CC_OP_SUB: tcg_gen_sub_tl(dst, a, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_subx_carry(dc, dst); break; case CC_OP_MOVE: @@ -685,7 +685,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, break; case CC_OP_NEG: tcg_gen_neg_tl(dst, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_subx_carry(dc, dst); break; case CC_OP_LZ: @@ -708,7 +708,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, break; case CC_OP_CMP: tcg_gen_sub_tl(dst, a, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_subx_carry(dc, dst); break; default: @@ -2924,12 +2924,12 @@ static unsigned int crisv32_decoder(CPUCRISState *e= nv, DisasContext *dc) * On QEMU care needs to be taken when a branch+delayslot sequence is brok= en * and the branch and delayslot don't share pages. * - * The TB contaning the branch insn will set up env->btarget and evaluate=20 + * The TB containing the branch insn will set up env->btarget and evaluate=20 * env->btaken. When the translation loop exits we will note that the bran= ch=20 * sequence is broken and let env->dslot be the size of the branch insn (t= hose * vary in length). * - * The TB contaning the delayslot will have the PC of its real insn (i.e n= o lsb + * The TB containing the delayslot will have the PC of its real insn (i.e = no lsb * set). It will also expect to have env->dslot setup with the size of the=20 * delay slot so that env->pc - env->dslot point to the branch insn. This = TB=20 * will execute the dslot and take the branch, either to btarget or just o= ne=20 @@ -3143,7 +3143,7 @@ static void cris_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cpu) tcg_gen_lookup_and_goto_ptr(); break; case DISAS_UPDATE: - /* Indicate that interupts must be re-evaluated before the next TB= . */ + /* Indicate that interrupts must be re-evaluated before the next T= B. */ tcg_gen_exit_tb(NULL, 0); break; default: diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7373177b55..9fe79b1242 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -35,7 +35,7 @@ #define MMU_PHYS_IDX 4 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* Hardware exceptions, interupts, faults, and traps. */ +/* Hardware exceptions, interrupts, faults, and traps. */ #define EXCP_HPMC 1 /* high priority machine check */ #define EXCP_POWER_FAIL 2 #define EXCP_RC 3 /* recovery counter */ @@ -276,7 +276,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, /* TB lookup assumes that PC contains the complete virtual address. If we leave space+offset separate, we'll get ITLB misses to an incomplete virtual address. This also means that we must separate - out current cpu priviledge from the low bits of IAOQ_F. */ + out current cpu privilege from the low bits of IAOQ_F. */ #ifdef CONFIG_USER_ONLY *pc =3D env->iaoq_f & -4; *cs_base =3D env->iaoq_b & -4; diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index d2480b163b..bebc732c97 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -37,7 +37,7 @@ static void eval_interrupt(HPPACPU *cpu) =20 /* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus * can write to this word to raise an external interrupt on the target CPU. - * This includes the system controler (DINO) for regular devices, or + * This includes the system controller (DINO) for regular devices, or * another CPU for SMP interprocessor interrupts. */ static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d33813d173..d66fcb3e6a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1964,7 +1964,7 @@ static void do_page_zero(DisasContext *ctx) { /* If by some means we get here with PSW[N]=3D1, that implies that the B,GATE instruction would be skipped, and we'd fault on the - next insn within the privilaged page. */ + next insn within the privileged page. */ switch (ctx->null_cond.c) { case TCG_COND_NEVER: break; diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 4c8ce7fed5..f8f24032cb 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -10,7 +10,7 @@ =20 #include "hw/registerfields.h" =20 -/* Base on kernal definitions: arch/loongarch/include/asm/loongarch.h */ +/* Based on kernel definitions: arch/loongarch/include/asm/loongarch.h */ =20 /* Basic CSRs */ #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 01c18a7c59..0a1544cd68 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -590,10 +590,10 @@ static void dump_address_map(CPUM68KState *env, uint3= 2_t root_pointer) =20 #define DUMP_CACHEFLAGS(a) \ switch (a & M68K_DESC_CACHEMODE) { \ - case M68K_DESC_CM_WRTHRU: /* cachable, write-through */ \ + case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \ qemu_printf("T"); \ break; \ - case M68K_DESC_CM_COPYBK: /* cachable, copyback */ \ + case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \ qemu_printf("C"); \ break; \ case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a7b040abd4..f6cab6ce19 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -205,7 +205,7 @@ typedef struct CPUArchState CPUMBState; #define PVR10_TARGET_FAMILY_MASK 0xFF000000 #define PVR10_ASIZE_SHIFT 18 =20 -/* MMU descrtiption */ +/* MMU description */ #define PVR11_USE_MMU 0xC0000000 #define PVR11_MMU_ITLB_SIZE 0x38000000 #define PVR11_MMU_DTLB_SIZE 0x07000000 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 92c38f54c2..ce4d605eb7 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -290,7 +290,7 @@ typedef struct CPUArchState { int is_counting; =20 uint32_t picmr; /* Interrupt mask register */ - uint32_t picsr; /* Interrupt contrl register*/ + uint32_t picsr; /* Interrupt control register */ #endif } CPUOpenRISCState; =20 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7760329e75..a86360d4f5 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -273,7 +273,7 @@ static void gen_div(DisasContext *dc, TCGv dest, TCGv s= rca, TCGv srcb) =20 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); /* The result of divide-by-zero is undefined. - Supress the host-side exception by dividing by 1. */ + Suppress the host-side exception by dividing by 1. */ tcg_gen_or_tl(t0, srcb, cpu_sr_ov); tcg_gen_div_tl(dest, srca, t0); =20 @@ -287,7 +287,7 @@ static void gen_divu(DisasContext *dc, TCGv dest, TCGv = srca, TCGv srcb) =20 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); /* The result of divide-by-zero is undefined. - Supress the host-side exception by dividing by 1. */ + Suppress the host-side exception by dividing by 1. */ tcg_gen_or_tl(t0, srcb, cpu_sr_cy); tcg_gen_divu_tl(dest, srca, t0); =20 diff --git a/target/rx/translate.c b/target/rx/translate.c index 08cabbde61..f552a0319a 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2066,7 +2066,7 @@ static inline void clrsetpsw(DisasContext *ctx, int c= b, int val) tcg_gen_movi_i32(cpu_psw_o, val << 31); break; default: - qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); + qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb); break; } } else if (is_privileged(ctx, 0)) { @@ -2084,7 +2084,7 @@ static inline void clrsetpsw(DisasContext *ctx, int c= b, int val) } break; default: - qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); + qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb); break; } } diff --git a/target/sparc/asi.h b/target/sparc/asi.h index bb58735ddb..3270ed0c7f 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -144,13 +144,13 @@ * ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-= T4 * and later ASIs. */ -#define ASI_REAL 0x14 /* Real address, cachable */ +#define ASI_REAL 0x14 /* Real address, cacheable */ #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ #define ASI_REAL_IO 0x15 /* Real address, non-cachable */ #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ #define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ #define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ -#define ASI_REAL_L 0x1c /* Real address, cachable, LE */ +#define ASI_REAL_L 0x1c /* Real address, cacheable, LE */ #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ #define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */ #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ @@ -163,15 +163,15 @@ #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load, * secondary, user */ -#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */ +#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */ #define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */ -#define ASI_TWINX_REAL 0x26 /* twin load, real, cachable */ +#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */ #define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */ #define ASI_TWINX_N 0x27 /* twin load, nucleus */ #define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */ #define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */ -#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */ -#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cachable, LE */ +#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */ +#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */ #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */ #define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */ #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ @@ -231,7 +231,7 @@ #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ diff --git a/target/tricore/csfr.h.inc b/target/tricore/csfr.h.inc index ff004cbddc..cdfaf1d662 100644 --- a/target/tricore/csfr.h.inc +++ b/target/tricore/csfr.h.inc @@ -1,4 +1,4 @@ -/* A(ll) access permited +/* A(ll) access permitted R(ead only) access E(nd init protected) access =20 diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 951024d491..7587c2ffe8 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -57,7 +57,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) return phys_addr; } =20 -/* TODO: Add exeption support*/ +/* TODO: Add exception support */ static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, int rw, int tlb_error) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 2f32463d4d..1947733870 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -128,7 +128,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) * Functions to generate micro-ops */ =20 -/* Makros for generating helpers */ +/* Macros for generating helpers */ =20 #define gen_helper_1arg(name, arg) do { \ TCGv_i32 helper_tmp =3D tcg_constant_i32(arg); \ @@ -336,8 +336,8 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCG= v ea) =20 /* We generate loads and store to core special function register (csfr) th= rough the function gen_mfcr and gen_mtcr. To handle access permissions, we us= e 3 - makros R, A and E, which allow read-only, all and endinit protected acc= ess. - These makros also specify in which ISA version the csfr was introduced.= */ + macros R, A and E, which allow read-only, all and endinit protected acc= ess. + These macros also specify in which ISA version the csfr was introduced.= */ #define R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ if (has_feature(ctx, FEATURE)) { \ @@ -362,7 +362,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret= , int32_t offset) #undef E =20 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, - since no execption occurs */ + since no exception occurs */ #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ if (has_feature(ctx, FEATURE)) { \ diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 2462c26000..462289f47c 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -120,7 +120,7 @@ endif %: %.S $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) else -# For softmmu targets we include a different Makefile fragement as the +# For softmmu targets we include a different Makefile fragment as the # build options for bare programs are usually pretty different. They # are expected to provide their own build recipes. EXTRA_CFLAGS +=3D -ffreestanding @@ -154,7 +154,7 @@ PLUGINS=3D$(patsubst %.c, lib%.so, $(notdir $(wildcard = $(PLUGIN_SRC)/*.c))) # pre-requistes manually here as we can't use stems to handle it. We # only expand MULTIARCH_TESTS which are common on most of our targets # to avoid an exponential explosion as new tests are added. We also -# add some special helpers the run-plugin- rules can use bellow. +# add some special helpers the run-plugin- rules can use below. =20 ifneq ($(MULTIARCH_TESTS),) $(foreach p,$(PLUGINS), \ diff --git a/tests/tcg/multiarch/sha512.c b/tests/tcg/multiarch/sha512.c index 9e701bcf20..12c2b6c2b7 100644 --- a/tests/tcg/multiarch/sha512.c +++ b/tests/tcg/multiarch/sha512.c @@ -453,7 +453,7 @@ void sha512(struct sha512 *sha, const void *p, size_t s= ize) /* From hex.h */ /** * hex_decode - Unpack a hex string. - * @str: the hexidecimal string + * @str: the hexadecimal string * @slen: the length of @str * @buf: the buffer to write the data into * @bufsize: the length of @buf diff --git a/tests/tcg/multiarch/system/Makefile.softmmu-target b/tests/tcg= /multiarch/system/Makefile.softmmu-target index fe40195d39..7ba9053375 100644 --- a/tests/tcg/multiarch/system/Makefile.softmmu-target +++ b/tests/tcg/multiarch/system/Makefile.softmmu-target @@ -3,7 +3,7 @@ # Multiarch system tests # # We just collect the tests together here and rely on the actual guest -# architecture to add to the test dependancies and deal with the +# architecture to add to the test dependencies and deal with the # complications of building. # =20 diff --git a/tests/tcg/tricore/c/crt0-tc2x.S b/tests/tcg/tricore/c/crt0-tc2= x.S index 3100da123c..399f112c35 100644 --- a/tests/tcg/tricore/c/crt0-tc2x.S +++ b/tests/tcg/tricore/c/crt0-tc2x.S @@ -263,7 +263,7 @@ __copy_table_next: ld.w %d3,[%a13+]4 # %d3 =3D block length jeq %d3,-1,__copy_table_done # length =3D=3D -1 =3D> end of table sh %d0,%d3,-3 # %d0 =3D length / 8 (doublewords) - and %d1,%d3,7 # %d1 =3D lenght % 8 (rem. bytes) + and %d1,%d3,7 # %d1 =3D length % 8 (rem. bytes) jz %d0,__copy_word # block size < 8 =3D> copy word addi %d0,%d0,-1 # else doublewords -=3D 1 mov.a %a2,%d0 # %a2 =3D loop counter @@ -274,7 +274,7 @@ __copy_dword: __copy_word: jz %d1,__copy_table_next sh %d0,%d1,-2 # %d0 =3D length / 4 (words) - and %d1,%d1,3 # %d1 =3D lenght % 4 (rem. bytes) + and %d1,%d1,3 # %d1 =3D length % 4 (rem. bytes) jz %d0,__copy_hword # block size < 4 =3D> copy hword ld.w %d14,[%a15+]4 # copy one word st.w [%a14+]4,%d14 diff --git a/tests/tcg/x86_64/system/boot.S b/tests/tcg/x86_64/system/boot.S index ed0f638406..dac9bd534d 100644 --- a/tests/tcg/x86_64/system/boot.S +++ b/tests/tcg/x86_64/system/boot.S @@ -121,7 +121,7 @@ _start: // Setup stack ASAP movq $stack_end,%rsp =20 - /* don't worry about stack frame, assume everthing is garbage when= we return */ + /* don't worry about stack frame, assume everything is garbage whe= n we return */ call main =20 _exit: /* output any non-zero result in eax to isa-debug-exit device */ @@ -195,7 +195,7 @@ idt_1F: .int 0, 0 * * This describes various memory areas (segments) through * segment descriptors. In 32 bit mode each segment each - * segement is associated with segment registers which are + * segment is associated with segment registers which are * implicitly (or explicitly) referenced depending on the * instruction. However in 64 bit mode selectors are flat and * segmented addressing isn't used. --=20 2.39.2 From nobody Mon May 20 14:32:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1689508783271569.1350465485887; Sun, 16 Jul 2023 04:59:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qL0OV-0004Hf-Vg; Sun, 16 Jul 2023 07:58:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OU-0004GW-Gl; Sun, 16 Jul 2023 07:58:30 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qL0OS-0001vJ-M7; Sun, 16 Jul 2023 07:58:30 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id CD8251424B; Sun, 16 Jul 2023 14:58:25 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id B75C414F34; Sun, 16 Jul 2023 14:58:05 +0300 (MSK) Received: (nullmailer pid 1505333 invoked by uid 1000); Sun, 16 Jul 2023 11:58:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev , Christian Schoenebeck Subject: [PATCH 6/6] tree-wide spelling fixes in comments and some messages: hw/9pfs Date: Sun, 16 Jul 2023 14:58:01 +0300 Message-Id: <20230716115801.1505288-7-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230716115801.1505288-1-mjt@tls.msk.ru> References: <20230716115801.1505288-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1689508785474100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Christian Schoenebeck --- hw/9pfs/9p-local.c | 8 ++++---- hw/9pfs/9p-proxy.c | 2 +- hw/9pfs/9p-synth.c | 2 +- hw/9pfs/9p-util.h | 2 +- hw/9pfs/9p.c | 4 ++-- hw/9pfs/9p.h | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/9pfs/9p-local.c b/hw/9pfs/9p-local.c index 9d07620235..1b1f3b9ec8 100644 --- a/hw/9pfs/9p-local.c +++ b/hw/9pfs/9p-local.c @@ -624,7 +624,7 @@ static ssize_t local_pwritev(FsContext *ctx, V9fsFidOpe= nState *fs, /* * Initiate a writeback. This is not a data integrity sync. * We want to ensure that we don't leave dirty pages in the cache - * after write when writeout=3Dimmediate is sepcified. + * after write when writeout=3Dimmediate is specified. */ sync_file_range(fs->fd, offset, ret, SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WRIT= E); @@ -843,7 +843,7 @@ static int local_open2(FsContext *fs_ctx, V9fsPath *dir= _path, const char *name, } credp->fc_mode =3D credp->fc_mode | S_IFREG; if (fs_ctx->export_flags & V9FS_SM_MAPPED) { - /* Set cleint credentials in xattr */ + /* Set client credentials in xattr */ err =3D local_set_xattrat(dirfd, name, credp); } else { err =3D local_set_mapped_file_attrat(dirfd, name, credp); @@ -912,7 +912,7 @@ static int local_symlink(FsContext *fs_ctx, const char = *oldpath, if (write_size !=3D oldpath_size) { goto err_end; } - /* Set cleint credentials in symlink's xattr */ + /* Set client credentials in symlink's xattr */ credp->fc_mode =3D credp->fc_mode | S_IFLNK; =20 if (fs_ctx->export_flags & V9FS_SM_MAPPED) { @@ -1418,7 +1418,7 @@ static int local_ioc_getversion_init(FsContext *ctx, = LocalData *data, Error **er struct statfs stbuf; =20 /* - * use ioc_getversion only if the ioctl is definied + * use ioc_getversion only if the ioctl is defined */ if (fstatfs(data->mountfd, &stbuf) < 0) { error_setg_errno(errp, errno, diff --git a/hw/9pfs/9p-proxy.c b/hw/9pfs/9p-proxy.c index 905cae6992..7aac49ad4a 100644 --- a/hw/9pfs/9p-proxy.c +++ b/hw/9pfs/9p-proxy.c @@ -767,7 +767,7 @@ static ssize_t proxy_pwritev(FsContext *ctx, V9fsFidOpe= nState *fs, /* * Initiate a writeback. This is not a data integrity sync. * We want to ensure that we don't leave dirty pages in the cache - * after write when writeout=3Dimmediate is sepcified. + * after write when writeout=3Dimmediate is specified. */ sync_file_range(fs->fd, offset, ret, SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WRIT= E); diff --git a/hw/9pfs/9p-synth.c b/hw/9pfs/9p-synth.c index f62c40b639..0ac79a500b 100644 --- a/hw/9pfs/9p-synth.c +++ b/hw/9pfs/9p-synth.c @@ -493,7 +493,7 @@ static int synth_name_to_path(FsContext *ctx, V9fsPath = *dir_path, node =3D dir_node; goto out; } - /* search for the name in the childern */ + /* search for the name in the children */ rcu_read_lock(); QLIST_FOREACH(node, &dir_node->child, sibling) { if (!strcmp(node->name, name)) { diff --git a/hw/9pfs/9p-util.h b/hw/9pfs/9p-util.h index df1b583a5e..51c94b0116 100644 --- a/hw/9pfs/9p-util.h +++ b/hw/9pfs/9p-util.h @@ -48,7 +48,7 @@ static inline uint64_t makedev_dotl(uint32_t dev_major, u= int32_t dev_minor) /* * Converts given device number from host's device number format to Linux * device number format. As both the size of type dev_t and encoding of - * dev_t is system dependant, we have to convert them for Linux guests if + * dev_t is system dependent, we have to convert them for Linux guests if * host is not running Linux. */ static inline uint64_t host_dev_to_dotl_dev(dev_t dev) diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c index 991645adca..323f042e65 100644 --- a/hw/9pfs/9p.c +++ b/hw/9pfs/9p.c @@ -644,7 +644,7 @@ static inline uint64_t mirror64bit(uint64_t value) } =20 /* - * Parameter k for the Exponential Golomb algorihm to be used. + * Parameter k for the Exponential Golomb algorithm to be used. * * The smaller this value, the smaller the minimum bit count for the Exp. * Golomb generated affixes will be (at lowest index) however for the @@ -1039,7 +1039,7 @@ static void coroutine_fn pdu_complete(V9fsPDU *pdu, s= size_t len) * Sending a reply would confuse clients because they would * assume that any EINTR is the actual result of the operation, * rather than a consequence of the cancellation. However, if - * the operation completed (succesfully or with an error other + * the operation completed (successfully or with an error other * than caused be cancellation), we do send out that reply, both * for efficiency and to avoid confusing the rest of the state machine * that assumes passing a non-error here will mean a successful diff --git a/hw/9pfs/9p.h b/hw/9pfs/9p.h index 1b0d805b9c..a6f59abccb 100644 --- a/hw/9pfs/9p.h +++ b/hw/9pfs/9p.h @@ -304,7 +304,7 @@ typedef struct VariLenAffix { AffixType_t type; /* Whether this affix is a suffix or a prefix. */ uint64_t value; /* Actual numerical value of this affix. */ /* - * Lenght of the affix, that is how many (of the lowest) bits of ``val= ue`` + * Length of the affix, that is how many (of the lowest) bits of ``val= ue`` * must be used for appending/prepending this affix to its final resul= ting, * unique number. */ --=20 2.39.2