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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c10-20020a63724a000000b0055386b1415dsm4989198pgn.51.2023.07.13.01.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 01:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1689237868; x=1691829868; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=TInFTBHuF+SmzJxy3gMWFeCGYHH0/coaMMeOCtsjHH0=; b=hm77oFoTpkB0AvitGeC0SfsSWGXi5wE5Tdhh83+2NvgRNh5sPBhI49UYTX8fO5PqTr +Q1VtFS/e8XdfPB3CO84C/G3SyrTnHVvwvajtkR4mdWBdNqdtSj4PghpZixRPMsst9GS 7b4iC4YLl1e2ex46d6S1R3BFCoBNUA9YfrnEeZ0AmAb6Hi1kVMYm/spLvAN/+w7eZnXZ UTwbeCocu1K6bPbQswkxlUFtKFHXY/TCy/5ORti2wkuIisBanXKdii4UmxERmd9babN+ 7yARiAlvFvDVR0POBeYnrkqaKy8XyCwgVLIKAwU46Hl1+5dSlib1zPwQfJq2J60KfXT8 MKbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689237868; x=1691829868; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=TInFTBHuF+SmzJxy3gMWFeCGYHH0/coaMMeOCtsjHH0=; b=Mf3Hy6+iVCUernE6up/0uaYOm8bpkBPjxTLP9Bs87Zv+qlZE8IML5lwBSY3662NODw OR/DHhCIkNwD4poERY9nTy8qr8+eI+2TarJ+wtMuvI8xrHs7mvQ2ZTL+jNqgtJJGaFuY +706gA6H0U8ZeeLWrdWasrggoec0fU4DnmIWBWADiBa0Q7ZvqEMsqqe9qLvjq9xpFcUp 3ew8URKBTFq2XacpOLVJSWId9pXm068uBOXpwT2kNJCRuSxqX+fl9GzXK874vJbLpClR r0hjxReNKbq6SOmKGWGwChmoQrZeu4KhLUY7iekkyjRXZXEMYMIUbohcV0zVbQUl+V1S LMbg== X-Gm-Message-State: ABy/qLaIrSVDJ6SLWFn+3TY7OkPNiI325lALRNXXgG2w6bJc2nOP+FFy mO5Ceo0BCWm9zJeeanOgi2dCXhO7MoELWAXD1b6SVFhYXFV+1yC9aqEMp+v+ls1yY+YWInPUiby gabQ+WkcVSSZJib/P+o3E2BI30ullYYto/MtS/lqGltIndkAYddfYhu4CaOGf1mAulEW7RCpzUT p+FXOJ X-Google-Smtp-Source: APBJJlGIIS9SWvwBr06+S3cPMiWK4R0LzvHQWvnQYxA5wg/Eswfxg2NUcoGvixGAV5h74X4bGWgY2A== X-Received: by 2002:a05:6a20:244d:b0:122:4a16:dfa4 with SMTP id t13-20020a056a20244d00b001224a16dfa4mr1023154pzc.10.1689237868118; Thu, 13 Jul 2023 01:44:28 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, ajones@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Paolo Bonzini , kvm@vger.kernel.org Subject: [PATCH v5 3/5] target/riscv: Create an KVM AIA irqchip Date: Thu, 13 Jul 2023 08:43:55 +0000 Message-Id: <20230713084405.24545-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230713084405.24545-1-yongxuan.wang@sifive.com> References: <20230713084405.24545-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=yongxuan.wang@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1689237999190100005 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 160 +++++++++++++++++++++++++++++++++++++++ target/riscv/kvm_riscv.h | 6 ++ 2 files changed, 166 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 005e054604..64156c15ec 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -36,6 +36,7 @@ #include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" +#include "hw/intc/riscv_imsic.h" #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" @@ -43,6 +44,7 @@ #include "chardev/char-fe.h" #include "migration/migration.h" #include "sysemu/runstate.h" +#include "hw/riscv/numa.h" =20 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx) @@ -1026,3 +1028,161 @@ bool kvm_arch_cpu_check_are_resettable(void) void kvm_arch_accel_class_init(ObjectClass *oc) { } + +char *kvm_aia_mode_str(uint64_t aia_mode) +{ + const char *val; + + switch (aia_mode) { + case KVM_DEV_RISCV_AIA_MODE_EMUL: + return "emul"; + case KVM_DEV_RISCV_AIA_MODE_HWACCEL: + return "hwaccel"; + case KVM_DEV_RISCV_AIA_MODE_AUTO: + default: + return "auto"; + }; +} + +void kvm_riscv_aia_create(MachineState *machine, + uint64_t aia_mode, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + int ret, i; + int aia_fd =3D -1; + uint64_t default_aia_mode; + uint64_t socket_count =3D riscv_socket_count(machine); + uint64_t max_hart_per_socket =3D 0; + uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; + uint64_t socket_bits, hart_bits, guest_bits; + + aia_fd =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); + + if (aia_fd < 0) { + error_report("Unable to create in-kernel irqchip"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &default_aia_mode, false, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to get current KVM AIA mode"); + exit(1); + } + qemu_log("KVM AIA: default mode is %s\n", + kvm_aia_mode_str(default_aia_mode)); + + if (default_aia_mode !=3D aia_mode) { + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &aia_mode, true, NULL); + if (ret < 0) + warn_report("KVM AIA: failed to set KVM AIA mode"); + else + qemu_log("KVM AIA: set current mode to %s\n", + kvm_aia_mode_str(aia_mode)); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of input irq lines"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_IDS, + &aia_msi_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of msi"); + exit(1); + } + + socket_bits =3D find_last_bit(&socket_count, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, + &socket_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_bits"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, + &group_shift, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_shift"); + exit(1); + } + + guest_bits =3D guest_num =3D=3D 0 ? 0 : + find_last_bit(&guest_num, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, + &guest_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set guest_bits"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the base address of APLIC"); + exit(1); + } + + for (socket =3D 0; socket < socket_count; socket++) { + socket_imsic_base =3D imsic_base + socket * (1U << group_shift); + hart_count =3D riscv_socket_hart_count(machine, socket); + base_hart =3D riscv_socket_first_hartid(machine, socket); + + if (max_hart_per_socket < hart_count) { + max_hart_per_socket =3D hart_count; + } + + for (i =3D 0; i < hart_count; i++) { + imsic_addr =3D socket_imsic_base + i * IMSIC_HART_SIZE(guest_b= its); + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_= hart), + &imsic_addr, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the address of IMSICs= "); + exit(1); + } + } + } + + hart_bits =3D find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, + &hart_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set hart_bits"); + exit(1); + } + + if (kvm_has_gsi_routing()) { + for (uint64_t idx =3D 0; idx < aia_irq_num + 1; ++idx) { + /* KVM AIA only has one APLIC instance */ + kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); + } + kvm_gsi_routing_allowed =3D true; + kvm_irqchip_commit_routes(kvm_state); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, + KVM_DEV_RISCV_AIA_CTRL_INIT, + NULL, true, NULL); + if (ret < 0) { + error_report("KVM AIA: initialized fail"); + exit(1); + } + + kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); +} diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index e3ba935808..c6745dd29a 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -22,5 +22,11 @@ void kvm_riscv_init_user_properties(Object *cpu_obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +char *kvm_aia_mode_str(uint64_t aia_mode); +void kvm_riscv_aia_create(MachineState *machine, + uint64_t aia_mode, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num); =20 #endif --=20 2.17.1