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Tue, 11 Jul 2023 17:24:21 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id iTbb7zi2dsqS; Tue, 11 Jul 2023 17:24:20 -0500 (CDT) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 640C68285751; Tue, 11 Jul 2023 17:24:20 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ubVhUrGGwYzs; Tue, 11 Jul 2023 17:24:20 -0500 (CDT) Received: from raptor-ewks-026.lan (5.edge.rptsys.com [23.155.224.38]) by mail.rptsys.com (Postfix) with ESMTPSA id 4F97B828549E; Tue, 11 Jul 2023 17:24:19 -0500 (CDT) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.rptsys.com 640C68285751 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1689114260; bh=o4OveDXgLcp/4SKUzDEYdxB5hcG9iUGQEyk8ii5G7/0=; h=From:To:Date:Message-Id:MIME-Version; b=mskzOP2rcBeXpOg3gbp0lcsYq7QzwH9soGwrUbvTlXZJ+PiVKu2kUw1k527NkKgki BtrQETLtypouwkyYE1EsgqLGkhs3MYXNHZRs2W8Q/6spu+viZeJ1UvlcIJuWJ8Ey8I vGgIctvwpOFfXA+HDfbRaRtIWeSRyGJMn0epAu9E= X-Virus-Scanned: amavisd-new at rptsys.com From: Shawn Anastasio To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Nicholas Piggin , Greg Kurz , David Gibson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , Timothy Pearson , Shawn Anastasio Subject: [PATCH] target/ppc: Generate storage interrupts for radix RC changes Date: Tue, 11 Jul 2023 17:24:05 -0500 Message-Id: <20230711222405.2712188-1-sanastasio@raptorengineering.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=23.155.224.40; envelope-from=sanastasio@raptorengineering.com; helo=raptorengineering.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @raptorengineering.com) X-ZM-MESSAGEID: 1689114337593100002 Content-Type: text/plain; charset="utf-8" Change radix64_set_rc to always generate a storage interrupt when the R/C bits are not set appropriately instead of setting the bits itself. According to the ISA both behaviors are valid, but in practice this change more closely matches behavior observed on the POWER9 CPU. From the POWER9 Processor User's Manual, Section 4.10.13.1: "When performing Radix translation, the POWER9 hardware triggers the appropriate interrupt ... for the mode and type of access whenever Reference (R) and Change (C) bits require setting in either the guest or host page-table entry (PTE)." Signed-off-by: Shawn Anastasio --- target/ppc/mmu-radix64.c | 57 ++++++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 920084bd8f..06e1cced31 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -219,27 +219,48 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, M= MUAccessType access_type, return false; } =20 -static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type, - uint64_t pte, hwaddr pte_addr, int *prot) +static int ppc_radix64_check_rc(PowerPCCPU *cpu, MMUAccessType access_type, + uint64_t pte, vaddr eaddr, bool partition_s= coped, + hwaddr g_raddr) { - CPUState *cs =3D CPU(cpu); - uint64_t npte; + uint64_t lpid =3D 0; + uint64_t pid =3D 0; =20 - npte =3D pte | R_PTE_R; /* Always set reference bit */ + switch (access_type) { + case MMU_DATA_STORE: + if (!(pte & R_PTE_C)) { + break; + } + /* fall through */ + case MMU_INST_FETCH: + case MMU_DATA_LOAD: + if (!(pte & R_PTE_R)) { + break; + } =20 - if (access_type =3D=3D MMU_DATA_STORE) { /* Store/Write */ - npte |=3D R_PTE_C; /* Set change bit */ - } else { - /* - * Treat the page as read-only for now, so that a later write - * will pass through this function again to set the C bit. - */ - *prot &=3D ~PAGE_WRITE; + /* R/C bits are already set appropriately for this access */ + return 0; } =20 - if (pte ^ npte) { /* If pte has changed then write it back */ - stq_phys(cs->as, pte_addr, npte); + /* Obtain effLPID */ + (void)ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &p= id); + + /* + * Per ISA 3.1 Book III, 7.5.3 and 7.5.5, failure to set R/C during + * partition-scoped translation when effLPID =3D 0 results in normal + * (non-Hypervisor) Data and Instruction Storage Interrupts respective= ly. + * + * ISA 3.0 is ambiguous about this, but tests on POWER9 hardware seem = to + * exhibit the same behavior. + */ + if (partition_scoped && lpid > 0) { + ppc_radix64_raise_hsi(cpu, access_type, eaddr, g_raddr, + DSISR_ATOMIC_RC); + } else { + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_ATOMIC_RC); } + + return 1; } =20 static bool ppc_radix64_is_valid_level(int level, int psize, uint64_t nls) @@ -418,7 +439,8 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCP= U *cpu, } =20 if (guest_visible) { - ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, h_prot); + return ppc_radix64_check_rc(cpu, access_type, pte, eaddr, true, + g_raddr); } =20 return 0; @@ -580,7 +602,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, } =20 if (guest_visible) { - ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, g_prot); + return ppc_radix64_check_rc(cpu, access_type, pte, eaddr, false, + *g_raddr); } =20 return 0; --=20 2.30.2