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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id i126-20020a639d84000000b0055b44a901absm181559pgd.70.2023.07.10.05.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 05:34:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688992461; x=1691584461; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dfGeRq0ifhDkAXBFg1n3NHO7gtDa2a7NXLhI86+lfNE=; b=qIWFnuT8mB77TxBB6vC9O+oku2wjLAqKv9UZaRZmTFUGQUwjG2hov/J6Sw3SpX5IYh /+PTJMe0lPCVX5duMr0SlJYsprLgpxiOcB3RMZjAKQW+Os9QzVy/7SXLvY6Sq+AC0bvD L3Qrd6dSHpGxUE6XEH3X1yKyzGU+Hjy1sCrNwwzkr7FpDQpBo77EQk21R5ZPLiBEjstu Xfrpxx1ZZSEfRJCh8tSk4lisAdgEPm4yFULWBY+HiGNRrw5lFVXyFXJvGp+S3yXk3vnO MjDQhJJyZIrSAItV23jtZ42dLZz2EO7R8vmGHxLbVubvyOMhHPhS0kL32K1vqTec67pD 7KeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688992461; x=1691584461; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dfGeRq0ifhDkAXBFg1n3NHO7gtDa2a7NXLhI86+lfNE=; b=LKBfSVFu4Abu6IfKl4zn8CC7uNdc7arnU2fuTKHOC1QaSsRu/bQoK+79FfkmqU5zXk IBo0HGeCHUyagYjxyEaEDaCA1rk8LBO2aCyTFPKdmH+6Im8470s6SxTWfaaHAm0WL3JX F1679GfQBjGIF8s4Frt6oVwcfk8WTikO3uudNXuwFHMoI6I0gEp5+7qsESmkqQHwni/m Tn2TiN/MSZS0wj/XBKLeOHuaFaRlUXvhJ9o6XH4XQ9Os80YtdmvlLjp2+Z64XumhxZbQ eiBBBlv69AeqTFSFb9tG29hFtlXgltCZ90j7ci1q3D+jtRU7+u6KHU8OqY7TNGvQP+IT WVEA== X-Gm-Message-State: ABy/qLYqzyIOJE9s8nIGsIN7AndJlFLZf3NVkocdi0+9KemDw6Gx1Pwe fawDtDOcT3q1Bad49zxXqrhE8idy10+l/w== X-Google-Smtp-Source: APBJJlGvMWOA2EX90MRTbRcNjGzHFJ2WdOq+t/gchsvJScRYTOhC1U78jGBVKVvZ4JXAXaHooiomxQ== X-Received: by 2002:a05:6808:3089:b0:3a0:4636:d079 with SMTP id bl9-20020a056808308900b003a04636d079mr11996411oib.22.1688992461273; Mon, 10 Jul 2023 05:34:21 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 35/54] target/riscv: skip features setup for KVM CPUs Date: Mon, 10 Jul 2023 22:31:46 +1000 Message-Id: <20230710123205.2441106-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710123205.2441106-1-alistair.francis@wdc.com> References: <20230710123205.2441106-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=alistair23@gmail.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1688992734255100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza As it is today it's not possible to use '-cpu host' if the RISC-V host has RVH enabled. This is the resulting error: $ ./qemu/build/qemu-system-riscv64 \ -machine virt,accel=3Dkvm -m 2G -smp 1 \ -nographic -snapshot -kernel ./guest_imgs/Image \ -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ -append "earlycon=3Dsbi root=3D/dev/ram rw" \ -cpu host qemu-system-riscv64: H extension requires priv spec 1.12.0 This happens because we're checking for priv spec for all CPUs, and since we're not setting env->priv_ver for the 'host' CPU, it's being default to zero (i.e. PRIV_SPEC_1_10_0). In reality env->priv_ver does not make sense when running with the KVM 'host' CPU. It's used to gate certain CSRs/extensions during translation to make them unavailable if the hart declares an older spec version. It doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs are available [1]. 'priv_ver' is just one example. We're doing a lot of feature validation and setup during riscv_cpu_realize() that it doesn't apply to KVM CPUs. Validating the feature set for those CPUs is a KVM problem that should be handled in KVM specific code. The new riscv_cpu_realize_tcg() helper contains all validation logic that are applicable to TCG CPUs only. riscv_cpu_realize() verifies if we're running TCG and, if it's the case, proceed with the usual TCG realize() logic. [1] lib/sbi/sbi_hart.c, hart_detect_features() Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-Id: <20230706101738.460804-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd647534cf..6232e6513b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,7 @@ #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_riscv.h" #include "tcg/tcg.h" =20 @@ -1386,20 +1387,12 @@ static void riscv_cpu_validate_misa_priv(CPURISCVSt= ate *env, Error **errp) } } =20 -static void riscv_cpu_realize(DeviceState *dev, Error **errp) +static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - riscv_cpu_validate_misa_mxl(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1434,7 +1427,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 #ifndef CONFIG_USER_ONLY - cs->tcg_cflags |=3D CF_PCREL; + CPU(dev)->tcg_cflags |=3D CF_PCREL; =20 if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); @@ -1447,6 +1440,28 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } } #endif +} + +static void riscv_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs =3D CPU(dev); + RISCVCPU *cpu =3D RISCV_CPU(dev); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + Error *local_err =3D NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + if (tcg_enabled()) { + riscv_cpu_realize_tcg(dev, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + } =20 riscv_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { --=20 2.40.1