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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id i126-20020a639d84000000b0055b44a901absm181559pgd.70.2023.07.10.05.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 05:33:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688992422; x=1691584422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=daTrB8dvvdsS+fCR1O2AOiztsnv8EvMR+anEKHWfbCI=; b=l8AobLxj1ZJCA5umHbRElVvsxUOj28mstVOUXbwHBpmQOoUlwDvffoAjWu2VDht1+b yHM13ODN4aJ7EQiz8BUIWzT+prgMJ4i4Inhq5uRBT2mN0lVgwlk/N1NTC6o+/MN98/Z/ InIJtUDrMV06DYaael1l5tNtEmUqTRzXnLbz8dOV2JFpukTo+lbH0CGcKD431elQKETj dV42zLojoVHp3J/YDzO+cSoxhCAOZ7SoLm9uztUV3B5ayhUvthjlVMICSVbDDPSZUDw5 aL7579CS3jilOUqjlNjL3UhsLODL1vKOeI/78D7+KlSYuvorhbso9a8nNL0l4k/wVbk1 Md0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688992422; x=1691584422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=daTrB8dvvdsS+fCR1O2AOiztsnv8EvMR+anEKHWfbCI=; b=S4De1zmKlx+BPZOZDXvZiA9lMnxJ4RO8MPO/p9OKwuYdhcW6NIt7ddbq12hNcUg4zt emx35In+I3u5dIucs+NnSmWf3ejCj5EfDsoH1iFf/WCMILKOpdTg936ecb7tnFAD0MGt mdD0AqxokiS4iDNAYeH5X6fH9NBKViNPlvh7kTe/RHWfe3uDIp7JOeuP/Uy7mACnfhw3 83WV12ZMtzv/oY5mKeXxCQAtRJQj/3N7r7fLzHpHItjpzM57Jt2L4r/uqmT7Z5Agdfot VXqfggcxSiK34ap81hpLO+d63lUykBFvJuL3BWEy7RKC5mN8mT9tCWYAP2jjeLBb7nrC k4wA== X-Gm-Message-State: ABy/qLaQvE5uPMMSP18w4EVHHSLRLWDf8DXS4J7jNCXi9gOoTy/hma6n GarC+LUO+BVaupSQ5np5FRbXVk4XcqB9mw== X-Google-Smtp-Source: APBJJlF6EAavbMmCwgbCzS7DdcRNZTLP+ZYrv63k+bVSwXssYtSA0N22vDbrFs51Bmepc+hAUEULWg== X-Received: by 2002:a05:6808:bd4:b0:38e:a824:27d3 with SMTP id o20-20020a0568080bd400b0038ea82427d3mr13966984oik.27.1688992422686; Mon, 10 Jul 2023 05:33:42 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Robbin Ehn , Palmer Dabbelt , Alistair Francis Subject: [PULL 24/54] linux-user/riscv: Add syscall riscv_hwprobe Date: Mon, 10 Jul 2023 22:31:35 +1000 Message-Id: <20230710123205.2441106-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710123205.2441106-1-alistair.francis@wdc.com> References: <20230710123205.2441106-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1688992622329100002 Content-Type: text/plain; charset="utf-8" From: Robbin Ehn This patch adds the new syscall for the "RISC-V Hardware Probing Interface" (https://docs.kernel.org/riscv/hwprobe.html). Reviewed-by: Palmer Dabbelt Signed-off-by: Robbin Ehn Message-Id: <06a4543df2aa6101ca9a48f21a3198064b4f1f87.camel@rivosinc.com> Signed-off-by: Alistair Francis --- linux-user/riscv/syscall32_nr.h | 1 + linux-user/riscv/syscall64_nr.h | 1 + linux-user/syscall.c | 146 ++++++++++++++++++++++++++++++++ 3 files changed, 148 insertions(+) diff --git a/linux-user/riscv/syscall32_nr.h b/linux-user/riscv/syscall32_n= r.h index 1327d7dffa..412e58e5b2 100644 --- a/linux-user/riscv/syscall32_nr.h +++ b/linux-user/riscv/syscall32_nr.h @@ -228,6 +228,7 @@ #define TARGET_NR_accept4 242 #define TARGET_NR_arch_specific_syscall 244 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) #define TARGET_NR_prlimit64 261 #define TARGET_NR_fanotify_init 262 #define TARGET_NR_fanotify_mark 263 diff --git a/linux-user/riscv/syscall64_nr.h b/linux-user/riscv/syscall64_n= r.h index 6659751933..29e1eb2075 100644 --- a/linux-user/riscv/syscall64_nr.h +++ b/linux-user/riscv/syscall64_nr.h @@ -251,6 +251,7 @@ #define TARGET_NR_recvmmsg 243 #define TARGET_NR_arch_specific_syscall 244 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) #define TARGET_NR_wait4 260 #define TARGET_NR_prlimit64 261 #define TARGET_NR_fanotify_init 262 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 9b9e3bd5e3..420bab7c68 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8983,6 +8983,147 @@ static int do_getdents64(abi_long dirfd, abi_long a= rg2, abi_long count) } #endif /* TARGET_NR_getdents64 */ =20 +#if defined(TARGET_NR_riscv_hwprobe) + +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 + +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) + +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) + +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) + +struct riscv_hwprobe { + abi_llong key; + abi_ullong value; +}; + +static void risc_hwprobe_fill_pairs(CPURISCVState *env, + struct riscv_hwprobe *pair, + size_t pair_count) +{ + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); + + for (; pair_count > 0; pair_count--, pair++) { + abi_llong key; + abi_ullong value; + __put_user(0, &pair->value); + __get_user(key, &pair->key); + switch (key) { + case RISCV_HWPROBE_KEY_MVENDORID: + __put_user(cfg->mvendorid, &pair->value); + break; + case RISCV_HWPROBE_KEY_MARCHID: + __put_user(cfg->marchid, &pair->value); + break; + case RISCV_HWPROBE_KEY_MIMPID: + __put_user(cfg->mimpid, &pair->value); + break; + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + value =3D riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) ? + RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0; + __put_user(value, &pair->value); + break; + case RISCV_HWPROBE_KEY_IMA_EXT_0: + value =3D riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) ? + RISCV_HWPROBE_IMA_FD : 0; + value |=3D riscv_has_ext(env, RVC) ? + RISCV_HWPROBE_IMA_C : pair->value; + __put_user(value, &pair->value); + break; + case RISCV_HWPROBE_KEY_CPUPERF_0: + __put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value); + break; + default: + __put_user(-1, &pair->key); + break; + } + } +} + +static int cpu_set_valid(abi_long arg3, abi_long arg4) +{ + int ret, i, tmp; + size_t host_mask_size, target_mask_size; + unsigned long *host_mask; + + /* + * cpu_set_t represent CPU masks as bit masks of type unsigned long *. + * arg3 contains the cpu count. + */ + tmp =3D (8 * sizeof(abi_ulong)); + target_mask_size =3D ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong); + host_mask_size =3D (target_mask_size + (sizeof(*host_mask) - 1)) & + ~(sizeof(*host_mask) - 1); + + host_mask =3D alloca(host_mask_size); + + ret =3D target_to_host_cpu_mask(host_mask, host_mask_size, + arg4, target_mask_size); + if (ret !=3D 0) { + return ret; + } + + for (i =3D 0 ; i < host_mask_size / sizeof(*host_mask); i++) { + if (host_mask[i] !=3D 0) { + return 0; + } + } + return -TARGET_EINVAL; +} + +static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1, + abi_long arg2, abi_long arg3, + abi_long arg4, abi_long arg5) +{ + int ret; + struct riscv_hwprobe *host_pairs; + + /* flags must be 0 */ + if (arg5 !=3D 0) { + return -TARGET_EINVAL; + } + + /* check cpu_set */ + if (arg3 !=3D 0) { + ret =3D cpu_set_valid(arg3, arg4); + if (ret !=3D 0) { + return ret; + } + } else if (arg4 !=3D 0) { + return -TARGET_EINVAL; + } + + /* no pairs */ + if (arg2 =3D=3D 0) { + return 0; + } + + host_pairs =3D lock_user(VERIFY_WRITE, arg1, + sizeof(*host_pairs) * (size_t)arg2, 0); + if (host_pairs =3D=3D NULL) { + return -TARGET_EFAULT; + } + risc_hwprobe_fill_pairs(cpu_env, host_pairs, arg2); + unlock_user(host_pairs, arg1, sizeof(*host_pairs) * (size_t)arg2); + return 0; +} +#endif /* TARGET_NR_riscv_hwprobe */ + #if defined(TARGET_NR_pivot_root) && defined(__NR_pivot_root) _syscall2(int, pivot_root, const char *, new_root, const char *, put_old) #endif @@ -13665,6 +13806,11 @@ static abi_long do_syscall1(CPUArchState *cpu_env,= int num, abi_long arg1, return ret; #endif =20 +#if defined(TARGET_NR_riscv_hwprobe) + case TARGET_NR_riscv_hwprobe: + return do_riscv_hwprobe(cpu_env, arg1, arg2, arg3, arg4, arg5); +#endif + default: qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num); return -TARGET_ENOSYS; --=20 2.40.1