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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id i126-20020a639d84000000b0055b44a901absm181559pgd.70.2023.07.10.05.33.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 05:33:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688992384; x=1691584384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q02apAqlmOQugFoaiIWP++2Y9Op4N1E0jUWJOT5Xf8k=; b=Yr7Nf5CKbW1Dv15egdG8knfiIFT+GxGxaISmUW7TCDxsCYqlXdP+CjcfyzjT24tTFn i7wKFLFMzjIjZkuIDugj3Wt5LiET79Roc6k4pyYEa+n19Yjmrl9kPqOiUUqLCylJjqc7 sYwHPPF6nqmCBHNknx+1tstFZuuJnYAjenEEzKZsioikJTfbDvKthcMngLrrDucKWwMq w+zz6IjpJigQZGg9t+pItbQKBtuNsk9kruNdp8/x8EPEByEvlVFgd4jmnLq7sdzq00ub dD08QsBfyTqk0wIJ8qcc9bPRcFFbRV8jVUWcyskxKahROy+JW9ZyXvnxXoZanhGhgAE5 /L7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688992384; x=1691584384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q02apAqlmOQugFoaiIWP++2Y9Op4N1E0jUWJOT5Xf8k=; b=bEV5A5PQ7QA8arKuUkP013R/v6HyrZkIkh7ljlA09NUjnJrW4wayrDQh6Ol5L+Z2m9 rkuQ3UrJVySmbwJ046uwtrYAXl9Ouq//6iUf4oD9OaY41BCNv2/MfHl3yUZhdLztSefB 5FWRDyLAHq03NPBraHtVoW603XapX09mL7xTzJSoWJbW3OahFdVn9wzuwqoSYteVMsav h97LdVLr4z5TN9pZLn680nBYlx9eczfWjd+bQ64HveaFuYKAlPKvnf3BcHLzG9NhW3lI 0zrO5ksse3Xf9lQpAqaSnxZ1KXYgjCoVpFqsinn0q8qKdBYWmtuwcYNRfXnkfeYt7myU gTUQ== X-Gm-Message-State: ABy/qLbRhlLQclR+tQgJcile3kY/ZGvL6nOYnwpkRpSCdBrvOBaBlBre pjrJ+cPxiDeYc3Wf9iF7fACjjTMroImOSw== X-Google-Smtp-Source: APBJJlExMD2PjQsfAmc3eqWP9BFLI/hXRg0PDAUsma9ou7MMGqJDyNyP2zp5/JNxkxWIDmOnkoSlFw== X-Received: by 2002:a05:6808:1a21:b0:3a0:58f6:c424 with SMTP id bk33-20020a0568081a2100b003a058f6c424mr15423896oib.26.1688992384531; Mon, 10 Jul 2023 05:33:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 13/54] target/riscv: Add additional xlen for address when MPRV=1 Date: Mon, 10 Jul 2023 22:31:24 +1000 Message-Id: <20230710123205.2441106-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710123205.2441106-1-alistair.francis@wdc.com> References: <20230710123205.2441106-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=alistair23@gmail.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1688992437367100002 From: Weiwei Li As specified in privilege spec:"When MPRV=3D1, load and store memory addresses are treated as though the current XLEN were set to MPP=E2=80=99s XLEN". So the xlen for address may be different from current xlen. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-Id: <20230614032547.35895-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 49 +++++++++++++++++++++++++++++++++------ target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 13 ++++++++++- 3 files changed, 55 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7adb8706ac..3081603464 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -500,6 +500,7 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) FIELD(TB_FLAGS, PRIV, 24, 2) +FIELD(TB_FLAGS, AXL, 26, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -516,13 +517,20 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPU= RISCVState *env) return &env_archcpu(env)->cfg; } =20 -#if defined(TARGET_RISCV32) -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) -#else -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +#if !defined(CONFIG_USER_ONLY) +static inline int cpu_address_mode(CPURISCVState *env) +{ + int mode =3D env->priv; + + if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(env->mstatus, MSTATUS_MPP); + } + return mode; +} + +static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) { RISCVMXL xl =3D env->misa_mxl; -#if !defined(CONFIG_USER_ONLY) /* * When emulating a 32-bit-only cpu, use RV32. * When emulating a 64-bit cpu, and MXL has been reduced to RV32, @@ -530,7 +538,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *= env) * back to RV64 for lower privs. */ if (xl !=3D MXL_RV32) { - switch (env->priv) { + switch (mode) { case PRV_M: break; case PRV_U: @@ -541,11 +549,38 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState= *env) break; } } -#endif return xl; } #endif =20 +#if defined(TARGET_RISCV32) +#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +{ +#if !defined(CONFIG_USER_ONLY) + return cpu_get_xl(env, env->priv); +#else + return env->misa_mxl; +#endif +} +#endif + +#if defined(TARGET_RISCV32) +#define cpu_address_xl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL cpu_address_xl(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + return env->xl; +#else + int mode =3D cpu_address_mode(env); + + return cpu_get_xl(env, mode); +#endif +} +#endif + static inline int riscv_cpu_xlen(CPURISCVState *env) { return 16 << env->xl; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8e3c73da52..2e771ddfc9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,6 +135,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); if (env->cur_pmmask !=3D 0) { flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0a5ab89c43..98d54c5617 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,6 +64,7 @@ typedef struct DisasContext { target_ulong priv_ver; RISCVMXL misa_mxl_max; RISCVMXL xl; + RISCVMXL address_xl; uint32_t misa_ext; uint32_t opcode; RISCVExtStatus mstatus_fs; @@ -129,6 +130,14 @@ static inline bool has_ext(DisasContext *ctx, uint32_t= ext) #define get_xl(ctx) ((ctx)->xl) #endif =20 +#ifdef TARGET_RISCV32 +#define get_address_xl(ctx) MXL_RV32 +#elif defined(CONFIG_USER_ONLY) +#define get_address_xl(ctx) MXL_RV64 +#else +#define get_address_xl(ctx) ((ctx)->address_xl) +#endif + /* The word size for this machine mode. */ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) { @@ -575,12 +584,13 @@ static TCGv get_address(DisasContext *ctx, int rs1, i= nt imm) tcg_gen_addi_tl(addr, src1, imm); if (ctx->pm_mask_enabled) { tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_xl(ctx) =3D=3D MXL_RV32) { + } else if (get_address_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } if (ctx->pm_base_enabled) { tcg_gen_or_tl(addr, addr, pm_base); } + return addr; } =20 @@ -1177,6 +1187,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->misa_mxl_max =3D env->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); + ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); --=20 2.40.1