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Fri, 07 Jul 2023 07:04:48 -0700 (PDT) X-Google-Smtp-Source: APBJJlHbMZyTPRiBLHIxCDguaXKffoR/JroWYLteOPtfpW+AeH8RpDOsZHD88JYVlQS9os0FFjHw4w== X-Received: by 2002:ac2:5e7b:0:b0:4fb:8948:2b28 with SMTP id a27-20020ac25e7b000000b004fb89482b28mr3945950lfr.63.1688738687745; Fri, 07 Jul 2023 07:04:47 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Lei Wang , Tao Su Subject: [PULL 8/9] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Date: Fri, 7 Jul 2023 16:04:31 +0200 Message-ID: <20230707140432.88073-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230707140432.88073-1-pbonzini@redhat.com> References: <20230707140432.88073-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1688738830274100003 Content-Type: text/plain; charset="utf-8" From: Lei Wang SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security fixes. Add version 2 of SapphireRapids CPU model with those bits enabled also. Signed-off-by: Lei Wang Signed-off-by: Tao Su Message-ID: <20230706054949.66556-6-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 852c45b9658..ec229072e76 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3944,8 +3944,17 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { .model_id =3D "Intel Xeon Processor (SapphireRapids)", .versions =3D (X86CPUVersionDefinition[]) { { .version =3D 1 }, - { /* end of list */ }, - }, + { + .version =3D 2, + .props =3D (PropValue[]) { + { "sbdr-ssdp-no", "on" }, + { "fbsdp-no", "on" }, + { "psdp-no", "on" }, + { /* end of list */ } + } + }, + { /* end of list */ } + } }, { .name =3D "Denverton", --=20 2.41.0