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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id h25-20020a9d6a59000000b006b8850ad193sm511382otn.56.2023.07.06.03.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 03:18:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1688638682; x=1691230682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qoye68O0i1yEKW8VfAgtj15Ya8kYL4Awy2Enb7ifSQs=; b=UmHvE2FvRNb6YpdPaS6lHY0ZH7r77kL/8B0BP3Xd9tqkdTXo08RiaaoViz/gjvEpVf v6rYMpW+DdU0JkrBQv7TUKDrftTLXrZH8h2yuce32wf8W+VI+sKpumeM4YAj69ph6oBJ TB0dU3uWYKk8gKpcYIT/0KLDIjIxZWymPm41DriXiL+bqs9Qv/WSdYK+aqU9N5N8y+Wu +sO8OzxOBvi+rAaALrEa8RPAeIeLwB/yV4eMMxwIsLUjsFZZcSIWQY9svc7vNGJ2I2OK SRyc88NeiiDmW/i1+TUHd8FzTUit1LBX/ASJ6gBkLkkjKYxcVWP02LqIwLsQRkePjEqi 8J4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688638682; x=1691230682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qoye68O0i1yEKW8VfAgtj15Ya8kYL4Awy2Enb7ifSQs=; b=VITuubhjIQmcRP9GclvSbogX4M4UUv0KZ7RlAoxDSeAcMBs1TZ82qoBYlpG5j3jVND FOiY9cSH86rpCFWPITvrB55kEZaxfLDcRhZpbTaTPmM6ncWMCiDQVBI8TIRBlNcXUtXv 3laG5LvNpIub+4y8DuOzj14C3zUL4aM1GFR6nDLfPcflMdj5Ap4nH00TJyli/AUNDdSH 9iqqRdDb+LQU7x2oRYGu5jLlC0r5puMqHoranKiIUsWoSxvQKTo7VaLQ6YzEF7K612kX j5vGGa8wbeL44O6Lkm8tU80HmNIHzkqMoLJjL/WFqu9HA5NH4QAk1075L7SCTs6hzwAQ fJ5g== X-Gm-Message-State: ABy/qLZXp++yrO70ZSuX8fudPAKLiZj7cq/lWa0euiIwyE+L+dp9nasO 6m9s1puB+iNDW3HrMffOE2WiP2f3PHeUpnE5ulo= X-Google-Smtp-Source: APBJJlE3vfhH654RCHyG37AnTAoXE9RIpVDSvMFOUju5XPF/RNgy1Qo3eYQKNqoBa6SiGB7/Xsh3wQ== X-Received: by 2002:a05:6830:1da8:b0:6b8:7eef:a236 with SMTP id z8-20020a0568301da800b006b87eefa236mr1394814oti.30.1688638682048; Thu, 06 Jul 2023 03:18:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v9 05/20] target/riscv/cpu.c: restrict 'marchid' value Date: Thu, 6 Jul 2023 07:17:23 -0300 Message-ID: <20230706101738.460804-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706101738.460804-1-dbarboza@ventanamicro.com> References: <20230706101738.460804-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1688638876444100001 Content-Type: text/plain; charset="utf-8" 'marchid' shouldn't be set to a different value as previously set for named CPUs. For all other CPUs it shouldn't be freely set either - the spec requires that 'marchid' can't have the MSB (most significant bit) set and every other bit set to zero, i.e. 0x80000000 is an invalid 'marchid' value for 32 bit CPUs. As with 'mimpid', setting a default value based on the current QEMU version is not a good idea because it implies that the CPU implementation changes from one QEMU version to the other. Named CPUs should set 'marchid' to a meaningful value instead, and generic CPUs can set to any valid value. For the 'veyron-v1' CPU this is the error thrown if 'marchid' is set to a different val: $ ./build/qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,marchid=3D0= x80000000 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.marchid=3D0x800= 00000: Unable to change veyron-v1-riscv-cpu marchid (0x8000000000010000) And, for generics CPUs, this is the error when trying to set to an invalid val: $ ./build/qemu-system-riscv64 -M virt -nographic -cpu rv64,marchid=3D0x8000= 000000000000 qemu-system-riscv64: can't apply global rv64-riscv-cpu.marchid=3D0x80000000= 00000000: Unable to set marchid with MSB (64) bit set and the remaining bits zero Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 53 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 477f8f8f97..9080d021fa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -39,11 +39,6 @@ #include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ - -#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ - (QEMU_VERSION_MINOR << 8) | \ - (QEMU_VERSION_MICRO)) - static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 struct isa_ext_data { @@ -1811,8 +1806,6 @@ static void riscv_cpu_add_user_properties(Object *obj) static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif @@ -1959,6 +1952,56 @@ static void cpu_get_mimpid(Object *obj, Visitor *v, = const char *name, visit_type_bool(v, name, &value, errp); } =20 +static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.marchid; + uint64_t value, invalid_val; + uint32_t mxlen =3D 0; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: + mxlen =3D 32; + break; + case MXL_RV64: + case MXL_RV128: + mxlen =3D 64; + break; + default: + g_assert_not_reached(); + } + + invalid_val =3D 1LL << (mxlen - 1); + + if (value =3D=3D invalid_val) { + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " + "and the remaining bits zero", mxlen); + return; + } + + cpu->cfg.marchid =3D value; +} + +static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.marchid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -1996,6 +2039,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, cpu_set_mimpid, NULL, NULL); =20 + object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, + cpu_set_marchid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.41.0