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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=npiggin@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1688622036091100002 Content-Type: text/plain; charset="utf-8" The P10 core xscom memory regions overlap because the size is wrong. The P10 core+L2 xscom region size is allocated as 0x1000 (with some unused ranges). "EC" is used as a closer match, as "EX" includes L3 which has a disjoint xscom range that would require a different region if it were implemented. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_core.c | 6 ++++-- include/hw/ppc/pnv_core.h | 1 + include/hw/ppc/pnv_xscom.h | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 8a72171ce0..aa363e4b85 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -296,9 +296,8 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) } =20 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); - /* TODO: check PNV_XSCOM_EX_SIZE for p10 */ pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, - pc, name, PNV_XSCOM_EX_SIZE); + pc, name, pcc->xscom_size); =20 qemu_register_reset(pnv_core_reset, pc); return; @@ -350,6 +349,7 @@ static void pnv_core_power8_class_init(ObjectClass *oc,= void *data) PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); =20 pcc->xscom_ops =3D &pnv_core_power8_xscom_ops; + pcc->xscom_size =3D PNV_XSCOM_EX_SIZE; } =20 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) @@ -357,6 +357,7 @@ static void pnv_core_power9_class_init(ObjectClass *oc,= void *data) PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); =20 pcc->xscom_ops =3D &pnv_core_power9_xscom_ops; + pcc->xscom_size =3D PNV_XSCOM_EX_SIZE; } =20 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) @@ -364,6 +365,7 @@ static void pnv_core_power10_class_init(ObjectClass *oc= , void *data) PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); =20 pcc->xscom_ops =3D &pnv_core_power10_xscom_ops; + pcc->xscom_size =3D PNV10_XSCOM_EC_SIZE; } =20 static void pnv_core_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 77ef00f47a..aa5ca281fc 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -46,6 +46,7 @@ struct PnvCoreClass { DeviceClass parent_class; =20 const MemoryRegionOps *xscom_ops; + uint64_t xscom_size; }; =20 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index f7da9a1dc6..a4c9d95dc5 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -133,7 +133,7 @@ struct PnvXScomInterfaceClass { =20 #define PNV10_XSCOM_EC_BASE(core) \ ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) -#define PNV10_XSCOM_EC_SIZE 0x100000 +#define PNV10_XSCOM_EC_SIZE 0x1000 =20 #define PNV10_XSCOM_PSIHB_BASE 0x3011D00 #define PNV10_XSCOM_PSIHB_SIZE 0x100 --=20 2.40.1 From nobody Mon May 13 07:19:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=npiggin@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1688622037148100011 Content-Type: text/plain; charset="utf-8" Add basic chip and core xscom tests for powernv10 machine, equivalent to tests for powernv8 and 9. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater --- tests/qtest/pnv-xscom-test.c | 44 ++++++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/tests/qtest/pnv-xscom-test.c b/tests/qtest/pnv-xscom-test.c index 2c46d5cf6d..80903fa782 100644 --- a/tests/qtest/pnv-xscom-test.c +++ b/tests/qtest/pnv-xscom-test.c @@ -15,6 +15,7 @@ typedef enum PnvChipType { PNV_CHIP_POWER8, /* AKA Venice */ PNV_CHIP_POWER8NVL, /* AKA Naples */ PNV_CHIP_POWER9, /* AKA Nimbus */ + PNV_CHIP_POWER10, } PnvChipType; =20 typedef struct PnvChip { @@ -46,13 +47,22 @@ static const PnvChip pnv_chips[] =3D { .cfam_id =3D 0x220d104900008000ull, .first_core =3D 0x0, }, + { + .chip_type =3D PNV_CHIP_POWER10, + .cpu_model =3D "POWER10", + .xscom_base =3D 0x000603fc00000000ull, + .cfam_id =3D 0x120da04900008000ull, + .first_core =3D 0x0, + }, }; =20 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba) { uint64_t addr =3D chip->xscom_base; =20 - if (chip->chip_type =3D=3D PNV_CHIP_POWER9) { + if (chip->chip_type =3D=3D PNV_CHIP_POWER10) { + addr |=3D ((uint64_t) pcba << 3); + } else if (chip->chip_type =3D=3D PNV_CHIP_POWER9) { addr |=3D ((uint64_t) pcba << 3); } else { addr |=3D (((uint64_t) pcba << 4) & ~0xffull) | @@ -82,6 +92,8 @@ static void test_cfam_id(const void *data) =20 if (chip->chip_type =3D=3D PNV_CHIP_POWER9) { machine =3D "powernv9"; + } else if (chip->chip_type =3D=3D PNV_CHIP_POWER10) { + machine =3D "powernv10"; } =20 qts =3D qtest_initf("-M %s -accel tcg -cpu %s", @@ -96,23 +108,35 @@ static void test_cfam_id(const void *data) (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) #define PNV_XSCOM_P9_EC_BASE(core) \ ((uint64_t)(((core) & 0x1F) + 0x20) << 24) +#define PNV_XSCOM_P10_EC_BASE(core) \ + ((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + (0x1000 << (3 = - (core & 0x3)))) =20 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 =20 static void test_xscom_core(QTestState *qts, const PnvChip *chip) { - uint32_t first_core_dts0 =3D PNV_XSCOM_EX_DTS_RESULT0; - uint64_t dts0; + if (chip->chip_type =3D=3D PNV_CHIP_POWER10) { + uint32_t first_core_thread_state =3D + PNV_XSCOM_P10_EC_BASE(chip->first_core) + 0x412; + uint64_t thread_state; + + thread_state =3D pnv_xscom_read(qts, chip, first_core_thread_state= ); =20 - if (chip->chip_type !=3D PNV_CHIP_POWER9) { - first_core_dts0 |=3D PNV_XSCOM_EX_BASE(chip->first_core); + g_assert_cmphex(thread_state, =3D=3D, 0); } else { - first_core_dts0 |=3D PNV_XSCOM_P9_EC_BASE(chip->first_core); - } + uint32_t first_core_dts0 =3D PNV_XSCOM_EX_DTS_RESULT0; + uint64_t dts0; =20 - dts0 =3D pnv_xscom_read(qts, chip, first_core_dts0); + if (chip->chip_type =3D=3D PNV_CHIP_POWER9) { + first_core_dts0 |=3D PNV_XSCOM_P9_EC_BASE(chip->first_core); + } else { /* POWER8 */ + first_core_dts0 |=3D PNV_XSCOM_EX_BASE(chip->first_core); + } =20 - g_assert_cmphex(dts0, =3D=3D, 0x26f024f023f0000ull); + dts0 =3D pnv_xscom_read(qts, chip, first_core_dts0); + + g_assert_cmphex(dts0, =3D=3D, 0x26f024f023f0000ull); + } } =20 static void test_core(const void *data) @@ -123,6 +147,8 @@ static void test_core(const void *data) =20 if (chip->chip_type =3D=3D PNV_CHIP_POWER9) { machine =3D "powernv9"; + } else if (chip->chip_type =3D=3D PNV_CHIP_POWER10) { + machine =3D "powernv10"; } =20 qts =3D qtest_initf("-M %s -accel tcg -cpu %s", --=20 2.40.1