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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id m1-20020a4add01000000b0056665a16536sm70764oou.30.2023.07.05.14.40.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jul 2023 14:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1688593216; x=1691185216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cHoOs/OimalkJ6RrZxhbIIfv+GnVj9j4utc/gNZGEOg=; b=iu0DpZbXfs6eo6ck50fg5s3VoB6qJi5zYvb6UvEZ4cFxaqtrzjMbpV1A8XDjV29CmM uLaW6iuEPQkxhGisB+Uuo+o0FyGUlCiaKVxsql6uUP1yuuXTXWwztC4MZEHhnHwx0Ahs LMoyYGDtyHeFZ8WgTz9OjgWrGoH/FFCmzZSfu2o+/k+6tiE15aJLpIykuc8UkgaTzro+ 41WYp4OPIFUgF/ETg/tr2rPuVDWTa/Zx9PEM98p4DgRCFQyFxB4lC5WhKPr0YNT5Wa1k OC2rFwarD8itq27GryFBJOYSoh8W5yHtqo7mdep0vyYJa1XrsL3GQuhJcrnAwFEjiObF gcOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688593216; x=1691185216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cHoOs/OimalkJ6RrZxhbIIfv+GnVj9j4utc/gNZGEOg=; b=bR8GnFm10M58xV72IMIeUj6RbGsW9/ArN2FajwxXy7F3yp8s1aujU++KWxI49MDCEq +vEyae5yrVsY7d63TA5JxG7Wjmb/07bTJMlM7LOqQpG0qg4XkRsLq4FyALy7LfDnvzI5 aeRZZreSz4knUdSQa7FKaLvsMRVEYCXdAqjsEVycyfiRodjyBQ3N8IMSgRjaO/gOS50s 3VYKSBFWIL6mMuEcStj86GiGw02CkzO54Ex4lzBytpoKyjF/tbPvDOFlGrWEXiZPWwmP kmZ6VGR38/GbKIH+xLB8yns6CoE+awJ/hXBxfHzXVG8Zs7ZCZgn17euak/cg9YXJRKON WRTA== X-Gm-Message-State: ABy/qLbinjv0j6/uVj4tbXmTIeMNvf3ObUv950KrLW96NvXFLJwbyhv1 3ulboyVtbWZKP6pAVw7cxBwP/8rJ2sT5oHriLOc= X-Google-Smtp-Source: APBJJlGUUovyXgRqXdHdRXhUSIZM0VvehKh7k9RQIuZ2lkb3r3uieMXC/rSO/MwIWJciT4nIO0ZsJA== X-Received: by 2002:a05:6870:96a0:b0:1b0:7c30:7baf with SMTP id o32-20020a05687096a000b001b07c307bafmr244069oaq.42.1688593216164; Wed, 05 Jul 2023 14:40:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 04/20] target/riscv/cpu.c: restrict 'mimpid' value Date: Wed, 5 Jul 2023 18:39:39 -0300 Message-ID: <20230705213955.429895-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230705213955.429895-1-dbarboza@ventanamicro.com> References: <20230705213955.429895-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1688593287330100003 Content-Type: text/plain; charset="utf-8" Following the same logic used with 'mvendorid' let's also restrict 'mimpid' for named CPUs. Generic CPUs keep setting the value freely. Note that we're getting rid of the default RISCV_CPU_MARCHID value. The reason is that this is not a good default since it's dynamic, changing with with every QEMU version, regardless of whether the actual implementation of the CPU changed from one QEMU version to the other. Named CPU should set it to a meaningful value instead and generic CPUs can set whatever they want. This is the error thrown for an invalid 'mimpid' value for the veyron-v1 CPU: $ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=3D2 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=3D2: Unable to change veyron-v1-riscv-cpu mimpid (0x111) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a778241d9f..477f8f8f97 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -43,7 +43,6 @@ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ (QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MICRO)) -#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID =20 static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 @@ -1813,7 +1812,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -1932,6 +1930,35 @@ static void cpu_get_mvendorid(Object *obj, Visitor *= v, const char *name, visit_type_bool(v, name, &value, errp); } =20 +static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid =3D value; +} + +static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mimpid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -1966,6 +1993,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); =20 + object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, + cpu_set_mimpid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.41.0