From nobody Mon May 13 12:25:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688488640; cv=none; d=zohomail.com; s=zohoarc; b=FXq6IOvjA4021huNPaL2MfPmcDtv6k9IGh9c2wGJMHZEdWxoUzhx+Y0AbOzn21Kj5P17jW/vOGfObTQ0W8/LxrM+oBcQS7TJfge3Fuo0CLaNZzwcI8D1f+yqDhNXmHC/K+jrj5crLtdgNrHeB18yFOtnXgNEheUPhI18iTx9aO4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688488640; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=woUU+HiOTdfeWxIkByv1Ka1J61xMATqCD7GSJSY7c+4=; b=TQD8k+eQPPMGdRkwj/fKt7eenuVNelgsPnYIw21nMor7qTj5RXgOuWTbTGnR8dBXiQ9qhnqRdII3sJEajEAMsy8TX+itxmdYFhgOCzOs5RTh58qju3Ici5bLgrvpXuHYO/rrcsHet5sB88Oc5RniuLYAcpIaxXGWCfZr0h3ekD4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688488640122243.17035588585975; Tue, 4 Jul 2023 09:37:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGj18-0001GD-1p; Tue, 04 Jul 2023 12:36:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGj15-0001F8-W7 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:40 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGj13-0001nf-Nm for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:39 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3142a9ff6d8so4121326f8f.3 for ; Tue, 04 Jul 2023 09:36:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488596; x=1691080596; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=woUU+HiOTdfeWxIkByv1Ka1J61xMATqCD7GSJSY7c+4=; b=bq6XGx6vIzYSjaikfzWWvuPStDyyihVJ6RmEwst1cS2Nn2PCwCXytz7UQxSlutQ0ww al4D3COamNfKCPU2sEJRZop1jg5GTt7Amf7VZvEgQJ2pavVNsWLd9JNFXB92t8cJDr+K 0CUHkmLvg3P/DO8AAKKVV/+38ZQSJ9lWpYkgvhtw7KbwBjkYywHInm3/ikHiaZCMxzyf qKSmR8Iuf86JN9RiQMFFB9XveblG3IV7OJeMxq9ivQfkvso1DapPp+3/PctT9edl3dIl izTrw67sGF2VbbI1JK4xf7dvhmDTOc7/xMWExTwSsTjRUlLT2OTRcvNZHhR+AocxHFT4 MJVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488596; x=1691080596; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=woUU+HiOTdfeWxIkByv1Ka1J61xMATqCD7GSJSY7c+4=; b=gTcTEJZe2pTCU2nClXD+Df0OQdt3j8iTgQ0Z5nYhEJqzyKGvkGFHdCtaY9Bo/zDiTV rP6DeVV5ZZbUjUKFK8ODCgmpZKxUSCPlitWKk/90bFAJ4ueL/MiRlCl3wuJjOFt/sbX5 F2XYm52xnnXHQfMecVHKxnjEu64MOcWT4Ha2r8mrG6xB/KeOTtnmxmUAh9l6UvQpm8a1 1loojAuvH6fGectDGuSOy0leJJ1GppU0I4hk6E4LbeHE4+Xd5g6Q6YhfDRl31cjMt6vY PvZn6kYzkADwkDYcMoPiNP3VIc9VDHcd76bWog0ozDTg+TPtBtc6K9JZ677fHjy+Iobr hRSA== X-Gm-Message-State: ABy/qLaaQ4pSp3T6KfWD75Jv2ej0p6TDEafDegDvHreRtUrtSfuhnHSE Sey8E1okAL+cMbLyidESHdO1gPZ5vTL7qvL2E2M= X-Google-Smtp-Source: APBJJlFx4w0HbppuE2P6SCjoFzTPx5CejP6GKwKP3tgnWQDWw/xoc3KXKhgakJfCaL1sRlJPtV2bLg== X-Received: by 2002:a5d:4f08:0:b0:314:10c1:881d with SMTP id c8-20020a5d4f08000000b0031410c1881dmr11021939wru.68.1688488596243; Tue, 04 Jul 2023 09:36:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/11] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Date: Tue, 4 Jul 2023 17:36:24 +0100 Message-Id: <20230704163634.3188465-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488641649100004 Content-Type: text/plain; charset="utf-8" From: Eric Auger Some registers whose 'cooked' writefns induce TLB maintenance do not have raw_writefn ops defined. If only the writefn ops is set (ie. no raw_writefn is provided), it is assumed the cooked also work as the raw one. For those registers it is not obvious the tlb_flush works on KVM mode so better/safer setting the raw write. Signed-off-by: Eric Auger Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d08c058e424..a0b84efab52 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4189,14 +4189,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR0_EL1, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR1_EL1, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -4456,13 +4456,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_write, .raw_writefn =3D raw_write }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_write, .raw_writefn =3D raw_write }, }; =20 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5911,7 +5911,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_write }, + .writefn =3D hcr_write, .raw_writefn =3D raw_write }, { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, @@ -5983,6 +5983,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -5999,10 +6000,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), - .writefn =3D vttbr_write }, + .writefn =3D vttbr_write, .raw_writefn =3D raw_write }, { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .writefn =3D vttbr_write, + .access =3D PL2_RW, .writefn =3D vttbr_write, .raw_writefn =3D raw_w= rite, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, @@ -6014,7 +6015,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D vmsa_tcr_ttbr_el2_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6201,12 +6203,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), - .resetfn =3D scr_reset, .writefn =3D scr_write }, + .resetfn =3D scr_reset, .writefn =3D scr_write, .raw_writefn =3D raw= _write }, { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_NEWEL, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn =3D scr_write }, + .writefn =3D scr_write, .raw_writefn =3D raw_write }, { .name =3D "SDER32_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, .access =3D PL3_RW, .resetvalue =3D 0, @@ -7927,6 +7929,7 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, #ifndef CONFIG_USER_ONLY { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, --=20 2.34.1 From nobody Mon May 13 12:25:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488596; x=1691080596; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xgCaPGnXl46UU9A6jcwSSpnZq6M2JkIzMN4VboZNQHE=; b=SDuvYv8zZq65Gg+CrFMlDVf499JnmegaJ7AZOtsSndelw92DsGOIb/OzS3WQNhG392 mQQns5mqJpsaILgi7Db3bqhC4L0d4Wd02NVtXmvYEJnONz1SMpIgusZ/kXneXGWAgRnE 3qZZrV+9g/p78kwVQhXs2hs9E2lxzaRxAvQLix09412JUzytoF+ZvmPWU9sbKsHLz+2t fcegYUH1ZwRu/bOr4pov6OWnYKf2ADGhTU5qwcaNTCPQ/pLgtFobWaTooJY+6lCcMEqA NdBk8hZ0A+jmrw+slAPDjqUU9g56c+6lFYxxCS2EEmCR9sHbCQEC6DgYUSaBhzznv24P fYiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488596; x=1691080596; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xgCaPGnXl46UU9A6jcwSSpnZq6M2JkIzMN4VboZNQHE=; b=LodP/qTEifm4NPFUIOot2fZgx0qRnk4X5sYU2RuMZryy3euaR4yu/avGSxex1PzSLn HEQDsMLQgwwl9zJzdgMd07/Y8okyyo8DShZAbWXMV1K7We9GQKTDUae+hJQG1CgzxqOj 2AvZgtpiLkYW7bndkkfBnHevmP2jfZe/h91+XwsaLD/1W2lCyId0pwTEf6x/URYk536x ENVGLjca3SVkeihjZpfWmPTf+C0sTylUOXiwzm9OFRMV+uoMawE/iKmMVEDdP1v1Y1zy EvX7o+q/xrddZ4wjCaVtZRSbaNhvPpyQWeX0SQvlHxWiS48pkJF1cu7yaMgJX6HRbY// /Zgw== X-Gm-Message-State: ABy/qLaCD//WGjQqhzXV2wh7VxMaWGShmSFXyS6RELulCEr4GdFbFiGn LLmYJGVe1qWTJmJA+jDFwoyNj7pG0mCsB7AkSqo= X-Google-Smtp-Source: APBJJlEMw2BR77RS6PuXcL1QK6d4dC+N7TOjogzcpnGXikPU7mUK0+PFXzAGARdcYmW52Pl3Jrvrig== X-Received: by 2002:a5d:62d1:0:b0:313:f38f:1f4e with SMTP id o17-20020a5d62d1000000b00313f38f1f4emr10358292wrv.27.1688488596617; Tue, 04 Jul 2023 09:36:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/11] hw/arm/sbsa-ref: use XHCI to replace EHCI Date: Tue, 4 Jul 2023 17:36:25 +0100 Message-Id: <20230704163634.3188465-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488723635100001 Content-Type: text/plain; charset="utf-8" From: Yuquan Wang The current sbsa-ref cannot use EHCI controller which is only able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB. Hence, this uses XHCI to provide a usb controller with 64-bit DMA capablity instead of EHCI. We bump the platform version to 0.3 with this change. Although the hardware at the USB controller address changes, the firmware and Linux can both cope with this -- on an older non-XHCI-aware firmware/kernel setup the probe routine simply fails and the guest proceeds without any USB. (This isn't a loss of functionality, because the old USB controller never worked in the first place.) So we can call this a backwards-compatible change and only bump the minor version. Signed-off-by: Yuquan Wang Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn [PMM: tweaked commit message; add line to docs about what changes in platform version 0.3] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 5 ++++- hw/arm/sbsa-ref.c | 23 +++++++++++++---------- hw/arm/Kconfig | 2 +- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index a8e0b530a24..bca61608ff8 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -19,7 +19,7 @@ The ``sbsa-ref`` board supports: - A configurable number of AArch64 CPUs - GIC version 3 - System bus AHCI controller - - System bus EHCI controller + - System bus XHCI controller - CDROM and hard disc on AHCI bus - E1000E ethernet card on PCIe bus - Bochs display adapter on PCIe bus @@ -68,3 +68,6 @@ Platform version changes: =20 0.2 GIC ITS information is present in devicetree. + +0.3 + The USB controller is an XHCI device, not EHCI diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 82a28b2e0be..1a8519b868f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -42,6 +42,7 @@ #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "hw/usb.h" +#include "hw/usb/xhci.h" #include "hw/char/pl011.h" #include "hw/watchdog/sbsa_gwdt.h" #include "net/net.h" @@ -85,7 +86,7 @@ enum { SBSA_SECURE_UART_MM, SBSA_SECURE_MEM, SBSA_AHCI, - SBSA_EHCI, + SBSA_XHCI, }; =20 struct SBSAMachineState { @@ -123,7 +124,7 @@ static const MemMapEntry sbsa_ref_memmap[] =3D { [SBSA_SMMU] =3D { 0x60050000, 0x00020000 }, /* Space here reserved for more SMMUs */ [SBSA_AHCI] =3D { 0x60100000, 0x00010000 }, - [SBSA_EHCI] =3D { 0x60110000, 0x00010000 }, + [SBSA_XHCI] =3D { 0x60110000, 0x00010000 }, /* Space here reserved for other devices */ [SBSA_PCIE_PIO] =3D { 0x7fff0000, 0x00010000 }, /* 32-bit address PCIE MMIO space */ @@ -143,7 +144,7 @@ static const int sbsa_ref_irqmap[] =3D { [SBSA_SECURE_UART] =3D 8, [SBSA_SECURE_UART_MM] =3D 9, [SBSA_AHCI] =3D 10, - [SBSA_EHCI] =3D 11, + [SBSA_XHCI] =3D 11, [SBSA_SMMU] =3D 12, /* ... to 15 */ [SBSA_GWDT_WS0] =3D 16, }; @@ -230,7 +231,7 @@ static void create_fdt(SBSAMachineState *sms) * fw compatibility. */ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); =20 if (ms->numa_state->have_numa_distance) { int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -604,13 +605,15 @@ static void create_ahci(const SBSAMachineState *sms) } } =20 -static void create_ehci(const SBSAMachineState *sms) +static void create_xhci(const SBSAMachineState *sms) { - hwaddr base =3D sbsa_ref_memmap[SBSA_EHCI].base; - int irq =3D sbsa_ref_irqmap[SBSA_EHCI]; + hwaddr base =3D sbsa_ref_memmap[SBSA_XHCI].base; + int irq =3D sbsa_ref_irqmap[SBSA_XHCI]; + DeviceState *dev =3D qdev_new(TYPE_XHCI_SYSBUS); =20 - sysbus_create_simple("platform-ehci-usb", base, - qdev_get_gpio_in(sms->gic, irq)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, = irq)); } =20 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) @@ -832,7 +835,7 @@ static void sbsa_ref_init(MachineState *machine) =20 create_ahci(sms); =20 - create_ehci(sms); + create_xhci(sms); =20 create_pcie(sms); =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7de17d1e8c3..7e683484405 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -266,7 +266,7 @@ config SBSA_REF select PL011 # UART select PL031 # RTC select PL061 # GPIO - select USB_EHCI_SYSBUS + select USB_XHCI_SYSBUS select WDT_SBSA select BOCHS_DISPLAY =20 --=20 2.34.1 From nobody Mon May 13 12:25:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488597; x=1691080597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ANDE8o5tT4TCHpJ1lybjyH19qs/lumWSbTmj9hQZYtk=; b=raiJEk0nQA0pqGWXspkImP+EkS3myBqBZhuJ0UAYZ2thIttrWMp11BFd2kJW4MgZ7m n0BN2mPCgXpPYr4lT0QqWR8BO8CV65kkwnFvTh7Ygd8tfo+/NPmn2mYc+mLTdF1fgtF3 qgOUztbT3UlUHl6zOGs2XmnJneaTs54veus9UJx/EOahUPlb9a7FUxm5GNmVcDL50/Pm MQQq/7oC1jEeI6lLh8tB/erMVCyipJguNhyQVa6A0tznufnB/R1T3kqNiNTuF2m8nfli VA32RMxSXey09xxlOQ4/ZHpN4aDWMEVqgVW3VS3F6BeNZ8U7vGGbHOkEVzLh9Ggkr3M1 A/uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488597; x=1691080597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ANDE8o5tT4TCHpJ1lybjyH19qs/lumWSbTmj9hQZYtk=; b=ZY8D6KydpOVFbk39klubaRjSJYFhZriZAI3xEGDCYKLB8/VR+KPusSugfvPA03K+kB PBBod69KqGTNv8ILdHFcSFht6zC9oCZpvqbelRiPU+U82tBQmhIjX9ZXo9NvPgu96QgJ jMfyJa73mr7awnq6vmAobPtD7r2uJrcqsqgTphZllhYusjce7wGdWaq9muPRPysDNyEN P9UzWQAH3Pops9q6rDry7WDB63UwO4vr+J5crGicleb/VjvUj/CEsD/h+MGZpLUevj7O tav20gBmy3uI4gG3KmdDDeVxHwQbV4jg+N7rlksEsnbVPRJiCBWGJvEyKTULs2hE4OgF JNfg== X-Gm-Message-State: ABy/qLZJLkt/QvqYRnUK20adZyuxvFlEWQeQ3jzjDINV+4niUdtaeEPo vgAdhXayJdmZHZk7X1atDKRGssEadqtuvg/lUDc= X-Google-Smtp-Source: APBJJlHOz/r2UppZfoACYBp4upU/d98XIJU/PiKONjJCLt8p+Qp9/66jIpax1GgbQOEDN2yfe3GBmw== X-Received: by 2002:a1c:f30b:0:b0:3fb:ce46:c0b3 with SMTP id q11-20020a1cf30b000000b003fbce46c0b3mr10156238wmq.35.1688488597011; Tue, 04 Jul 2023 09:36:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/11] target/arm: Avoid splitting Zregs across lines in dump Date: Tue, 4 Jul 2023 17:36:26 +0100 Message-Id: <20230704163634.3188465-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488659483100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Allow the line length to extend to 548 columns. While annoyingly wide, it's still less confusing than the continuations we print. Also, the default VL used by Linux (and max for A64FX) uses only 140 columns. Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1e77698ba2..f12c714bc43 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -955,7 +955,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *= f, int flags) ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; uint32_t psr =3D pstate_read(env); - int i; + int i, j; int el =3D arm_current_el(env); const char *ns_status; bool sve; @@ -1014,7 +1014,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) } =20 if (sve) { - int j, zcr_len =3D sve_vqm1_for_el(env, el); + int zcr_len =3D sve_vqm1_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { bool eol; @@ -1054,32 +1054,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FI= LE *f, int flags) } } =20 - for (i =3D 0; i < 32; i++) { - if (zcr_len =3D=3D 0) { + if (zcr_len =3D=3D 0) { + /* + * With vl=3D16, there are only 37 columns per register, + * so output two registers per line. + */ + for (i =3D 0; i < 32; i++) { qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", i, env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); - } else if (zcr_len =3D=3D 1) { - qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 - ":%016" PRIx64 ":%016" PRIx64 "\n", - i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].= d[2], - env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0= ]); - } else { + } + } else { + for (i =3D 0; i < 32; i++) { + qemu_fprintf(f, "Z%02d=3D", i); for (j =3D zcr_len; j >=3D 0; j--) { - bool odd =3D (zcr_len - j) % 2 !=3D 0; - if (j =3D=3D zcr_len) { - qemu_fprintf(f, "Z%02d[%x-%x]=3D", i, j, j - 1); - } else if (!odd) { - if (j > 0) { - qemu_fprintf(f, " [%x-%x]=3D", j, j - 1); - } else { - qemu_fprintf(f, " [%x]=3D", j); - } - } qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", env->vfp.zregs[i].d[j * 2 + 1], - env->vfp.zregs[i].d[j * 2], - odd || j =3D=3D 0 ? "\n" : ":"); + env->vfp.zregs[i].d[j * 2 + 0], + j ? ":" : "\n"); } } } --=20 2.34.1 From nobody Mon May 13 12:25:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688488691; cv=none; d=zohomail.com; s=zohoarc; b=dr+SubE5rjA7EgVcwFPyowEx/FxmMuFynQoCHq4E1hZ5IIUYQ3RU3ZSo6KZXtVrSHFsQ+le3Vg4Th6dLD/Qlj4dVfN8R+exRrgq+UKLlGoPdR8bkLEGJPmnjSEA26zFPSdNg/aqbMwG63mkfYBfNDF39mhO5wQ/k1hSgyRNG5v4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688488691; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kTYABhSkRPbMfHK4MqNnIuIncwaUJ0xXtOeHrnGp338=; b=iLiyCSBNQo6FPYYR/D3TvnItnW+0bI/dXqSv0UYCw/Zmx6GLBiz/RvzFSFOURCrj/oSrwD4RdpgpJAIAkpgAyykJCEF9aV7hE9z4H3jEZqo2hxbhr4w4lZ3LKYTDsLUVz1Y26FJXaTAaRONHVK8fWfqqW8tXdeocs59ng1ExAjM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688488691806812.0850899445472; Tue, 4 Jul 2023 09:38:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGj1D-0001J1-7a; Tue, 04 Jul 2023 12:36:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGj1B-0001HQ-J3 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:45 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGj15-0001o5-1T for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:40 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3fbca8935bfso44744545e9.3 for ; Tue, 04 Jul 2023 09:36:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488597; x=1691080597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kTYABhSkRPbMfHK4MqNnIuIncwaUJ0xXtOeHrnGp338=; b=h5wSPoS2/Q/8BMCP0t4cxH/SMk5RnztokAaememdIDeTUgep8lanNs04LwOUQFqhJQ UjjuWPQW2M5lYyzKrHq8m0touV6v5VD/qJiRyj4hC8nFyDNckIOjeNdkFgpQtnNcYZI8 m14qkhHCxaQuhEU4PMnlT3ac3IGknDrt/FOXmKg0EoS6m8TLBoKWMiYwD7woJK6PWYxs ExzJanKZHhAeSWG+75PthCRMsomDOtansZ1Et3uaKVutMfYxPv+gT4xEVf8R9pFshzo2 gF3WRTNTakV4v5aTPcYm8Ybzu6ZnoU30+jfItUPsuzVMi4zqHRJCoWSsMDAlWNTagM8y guSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488597; x=1691080597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kTYABhSkRPbMfHK4MqNnIuIncwaUJ0xXtOeHrnGp338=; b=XGcBztFg0jTd7dWe81sy7WvvXDP7XmQJRiVQyO1rKEjYmfdY+ZK7ZOEVjP1bibjYoo GO5b87Mx+XzjJ62XISO7S0UW5Uxezv01rqjL4WAzIW29FXO1nExkVHRHjQr5WEOn4Zp3 PruEIJiHnFtFsP8HHqFd1tMqUzVzxXUj3+gI5+cyWFgz2JEP9mJGEgZyCLRao3uto7Zo 3SUYcW36KRUUz6XDqj73mPWpcG49+bo2SfMsXXYnpTgbeRUPg54j1SZWgLdZXik6Mchu j3m2gMeoZq/SZL2dLdI6g/M3y3RWMwDA9A5Y1u3Hg7bRqjdtS6rBlnqd9EzHvEV268EB 63/w== X-Gm-Message-State: ABy/qLYr2v70PhbxowQz2g3pE1cAmwbIy/dnzXVbUq8HSxDpZ3Dol1bX aWM1jW6nhpjXvQKbjHThZOs4AZj3MCyUV2E0W7E= X-Google-Smtp-Source: APBJJlEwts7PqVPNBOwainE2KZ+y+T9P7iK2mtiZwr0U+Mmho09YVmXkd8Ti+jv/VjRhs8InS8uLjQ== X-Received: by 2002:a1c:e913:0:b0:3fb:e356:b60d with SMTP id q19-20020a1ce913000000b003fbe356b60dmr1513784wmc.38.1688488597475; Tue, 04 Jul 2023 09:36:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/11] target/arm: Dump ZA[] when active Date: Tue, 4 Jul 2023 17:36:27 +0100 Message-Id: <20230704163634.3188465-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488693614100013 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Always print each matrix row whole, one per line, so that we get the entire matrix in the proper shape. Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f12c714bc43..adf84f96860 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1082,6 +1082,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FIL= E *f, int flags) i, q[1], q[0], (i & 1 ? "\n" : " ")); } } + + if (cpu_isar_feature(aa64_sme, cpu) && + FIELD_EX64(env->svcr, SVCR, ZA) && + sme_exception_el(env, el) =3D=3D 0) { + int zcr_len =3D sve_vqm1_for_el_sm(env, el, true); + int svl =3D (zcr_len + 1) * 16; + int svl_lg10 =3D svl < 100 ? 2 : 3; + + for (i =3D 0; i < svl; i++) { + qemu_fprintf(f, "ZA[%0*d]=3D", svl_lg10, i); + for (j =3D zcr_len; j >=3D 0; --j) { + qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", + env->zarray[i].d[2 * j + 1], + env->zarray[i].d[2 * j], + j ? ':' : '\n'); + } + } + } } =20 #else --=20 2.34.1 From nobody Mon May 13 12:25:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688488674; cv=none; d=zohomail.com; s=zohoarc; b=PJgZ8ZNDczS4g+rVB2BjzX3qLE+B9dsez1jjEoXFe5wniefjO0/FIvROzUK8RsMvMUkyFoqUcTmCDVXUV58MiQPfeeyJD2YDIx6LnNTGXSKsFYVeripcsIpWC30ZYojHrjIvUazYHQSw/FqqwWoZ4bLrRMJjgBqJXR7ONz9ZAOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688488674; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6iQY7+PhbnjlrKHmBY15bJBqwm1HUFH2IaULsHG+tok=; b=OtFuuPRtE2W6nHsa9pP87Q6hy5Gk9mlMhdVSJNMJBS5z69BxxVQhGS2607FNhMH3BJBHkNeYtklHl1qBKoQhF5GtItp+xeBYk5z2OeOlxJsZLDBYteHmHTTEsLMQYJ3/F/4hazIY1lj0kga5zXoIkRnczFWgwo11i8pDG7Xk8lY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688488674364348.97364874417985; Tue, 4 Jul 2023 09:37:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGj1G-0001MF-J3; Tue, 04 Jul 2023 12:36:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGj1B-0001HT-L8 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:45 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGj15-0001oI-Sw for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:41 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-314319c0d3eso3393156f8f.0 for ; Tue, 04 Jul 2023 09:36:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488598; x=1691080598; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6iQY7+PhbnjlrKHmBY15bJBqwm1HUFH2IaULsHG+tok=; b=gFpqnzVlkmZIVpxif7WEj1Z+J7mtBAzYl8f2Rf35AWa5knQtly1pUcL02hbsWV6tut ZDJzL0wCamaLfA9ryxJPbhWothY8cCWIGeSWR/AUHYr9FKC4XM3xsslzCWckAc+T6bOo iq0MQK2qbHBmCgUX93tZoW3xT04OO+Ym9XHUl8D7/4H9agtIeixcmGcpLEqVq4nhERV8 cTYWzz2aZ6oQ0/TVq0sV/U0us1DtrDWYSgH4wu/4o9BxiAnrzdkidiWu0B4RWmlmE9sT mCh4i5nMfTvgYeZaacW0PMbdVJ/tOfIdUC+O3PMtqQI+xCb/1Pftm7YD2TzHqpFRAf8S VQSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488598; x=1691080598; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6iQY7+PhbnjlrKHmBY15bJBqwm1HUFH2IaULsHG+tok=; b=JSkU/WP+xbBT60tO/2kpOfn042RUS66U7R64trVcryZTZM3TT8JbRY70hVKv0FDZRT uZ3QkABtWzl4/EgnBQr0XEF6G1Lh52JtoXd3I3NJd7B6iJQouJqkPKfsKLAwZ284OYRz NHsQwtlpRhXcAHfW6I0/CpaGNGoFoKsQMZEc207SiUm5CRHSiS+lF7crTyVYwuqm8cCs CeJiAOW8QB7BJjipysrlmO0pZePmbqlJG4sR6+VYPga25HkM77nqdsC3TLsD6kJy6IFy drOPhkoEAs5nG6PrlVkm+nVfE4Ty9RZWas/Yx4sn0KeIvki1DRO9eByxm8pb46FcMhc9 YULA== X-Gm-Message-State: ABy/qLYXXDsB1VLTdS037jRnCK/LOEMK4GxR3nS58X3mMQdJwADlAsmE T0o4NRLGfTMUmCt//JLVUAeFAPaqTLFS1z1CZJE= X-Google-Smtp-Source: APBJJlF/+0LUlQcwJMY+WuwZYOe1DsGq14W5AyNBkDtsGKoOyOYGlCqOIasearAk6ciyYSU3YmnTCQ== X-Received: by 2002:a5d:4534:0:b0:314:2c7a:d100 with SMTP id j20-20020a5d4534000000b003142c7ad100mr8835329wra.42.1688488597936; Tue, 04 Jul 2023 09:36:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/11] target/arm: Fix SME full tile indexing Date: Tue, 4 Jul 2023 17:36:28 +0100 Message-Id: <20230704163634.3188465-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488675392100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson For the outer product set of insns, which take an entire matrix tile as output, the argument is not a combined tile+column. Therefore using get_tile_rowcol was incorrect, as we extracted the tile number from itself. The test case relies only on assembler support for SME, since no release of GCC recognizes -march=3Darmv9-a+sme yet. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620 Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sme.c | 24 ++++++--- tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 10 ++-- 3 files changed, 108 insertions(+), 9 deletions(-) create mode 100644 tests/tcg/aarch64/sme-outprod1.c diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index d0054e3f775..6038b0a06f1 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -95,6 +95,21 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz= , int rs, return addr; } =20 +/* + * Resolve tile.size[0] to a host pointer. + * Used by e.g. outer product insns where we require the entire tile. + */ +static TCGv_ptr get_tile(DisasContext *s, int esz, int tile) +{ + TCGv_ptr addr =3D tcg_temp_new_ptr(); + int offset; + + offset =3D tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray); + + tcg_gen_addi_ptr(addr, cpu_env, offset); + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -260,8 +275,7 @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp= esz, return true; } =20 - /* Sum XZR+zad to find ZAd. */ - za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + za =3D get_tile(s, esz, a->zad); zn =3D vec_full_reg_ptr(s, a->zn); pn =3D pred_full_reg_ptr(s, a->pn); pm =3D pred_full_reg_ptr(s, a->pm); @@ -286,8 +300,7 @@ static bool do_outprod(DisasContext *s, arg_op *a, MemO= p esz, return true; } =20 - /* Sum XZR+zad to find ZAd. */ - za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + za =3D get_tile(s, esz, a->zad); zn =3D vec_full_reg_ptr(s, a->zn); zm =3D vec_full_reg_ptr(s, a->zm); pn =3D pred_full_reg_ptr(s, a->pn); @@ -308,8 +321,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,= MemOp esz, return true; } =20 - /* Sum XZR+zad to find ZAd. */ - za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + za =3D get_tile(s, esz, a->zad); zn =3D vec_full_reg_ptr(s, a->zn); zm =3D vec_full_reg_ptr(s, a->zm); pn =3D pred_full_reg_ptr(s, a->pn); diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outpr= od1.c new file mode 100644 index 00000000000..6e5972d75e3 --- /dev/null +++ b/tests/tcg/aarch64/sme-outprod1.c @@ -0,0 +1,83 @@ +/* + * SME outer product, 1 x 1. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +extern void foo(float *dst); + +asm( +" .arch_extension sme\n" +" .type foo, @function\n" +"foo:\n" +" stp x29, x30, [sp, -80]!\n" +" mov x29, sp\n" +" stp d8, d9, [sp, 16]\n" +" stp d10, d11, [sp, 32]\n" +" stp d12, d13, [sp, 48]\n" +" stp d14, d15, [sp, 64]\n" +" smstart\n" +" ptrue p0.s, vl4\n" +" fmov z0.s, #1.0\n" +/* + * An outer product of a vector of 1.0 by itself should be a matrix of 1.0. + * Note that we are using tile 1 here (za1.s) rather than tile 0. + */ +" zero {za}\n" +" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n" +/* + * Read the first 4x4 sub-matrix of elements from tile 1: + * Note that za1h should be interchangable here. + */ +" mov w12, #0\n" +" mova z0.s, p0/m, za1v.s[w12, #0]\n" +" mova z1.s, p0/m, za1v.s[w12, #1]\n" +" mova z2.s, p0/m, za1v.s[w12, #2]\n" +" mova z3.s, p0/m, za1v.s[w12, #3]\n" +/* + * And store them to the input pointer (dst in the C code): + */ +" st1w {z0.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z1.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z2.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z3.s}, p0, [x0]\n" +" smstop\n" +" ldp d8, d9, [sp, 16]\n" +" ldp d10, d11, [sp, 32]\n" +" ldp d12, d13, [sp, 48]\n" +" ldp d14, d15, [sp, 64]\n" +" ldp x29, x30, [sp], 80\n" +" ret\n" +" .size foo, . - foo" +); + +int main() +{ + float dst[16]; + int i, j; + + foo(dst); + + for (i =3D 0; i < 16; i++) { + if (dst[i] !=3D 1.0f) { + break; + } + } + + if (i =3D=3D 16) { + return 0; /* success */ + } + + /* failure */ + for (i =3D 0; i < 4; ++i) { + for (j =3D 0; j < 4; ++j) { + printf("%f ", (double)dst[i * 4 + j]); + } + printf("\n"); + } + return 1; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index cec1d4b2875..97cfc43600a 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -26,7 +26,7 @@ config-cc.mak: Makefile $(call cc-option,-march=3Darmv8.5-a, CROSS_CC_HAS_ARMV8_= 5); \ $(call cc-option,-mbranch-protection=3Dstandard, CROSS_CC_HAS_ARMV8_= BTI); \ $(call cc-option,-march=3Darmv8.5-a+memtag, CROSS_CC_HAS_ARMV8_= MTE); \ - $(call cc-option,-march=3Darmv9-a+sme, CROSS_CC_HAS_ARMV9_= SME)) 3> config-cc.mak + $(call cc-option,-Wa$(COMMA)-march=3Darmv9-a+sme, CROSS_AS_HAS_ARMV9_= SME)) 3> config-cc.mak -include config-cc.mak =20 ifneq ($(CROSS_CC_HAS_ARMV8_2),) @@ -61,11 +61,15 @@ AARCH64_TESTS +=3D mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 = mte-7 mte-%: CFLAGS +=3D -march=3Darmv8.5-a+memtag endif =20 +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +AARCH64_TESTS +=3D sme-outprod1 +endif + ifneq ($(CROSS_CC_HAS_SVE),) # System Registers Tests AARCH64_TESTS +=3D sysregs -ifneq ($(CROSS_CC_HAS_ARMV9_SME),) -sysregs: CFLAGS+=3D-march=3Darmv9-a+sme -DHAS_ARMV9_SME +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +sysregs: CFLAGS+=3D-Wa,-march=3Darmv9-a+sme -DHAS_ARMV9_SME else sysregs: CFLAGS+=3D-march=3Darmv8.1-a+sve endif --=20 2.34.1 From nobody Mon May 13 12:25:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488598; x=1691080598; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=J5PRaqRDbG1q7cJ7k1FBCGAtKCCwmrJ591DUA034EE4=; b=Twz5jQTd7UrJ4r6NbtKEKyiDfhDd/7qO8sFkT07NbSspsJRVYraVLs7+8OiH1Nll6D ZpR7EVE/X9I7hRFeJf7NIdPwO+rb6h+v2o3yGWgnPts5hjs39iJUsV1CEGHAMIEoAfvX T2QaYpZMKr2Itz/Qe+0xvEXFrzVvrJ3YofQL6EpOOXiTFECzyMrBR9wgPMppvOpSfBM/ iqs2sxFLtx+av2CSOZMx0hC38UFJaC7YGR96beJ17TMCiWLVyxyvcTDAc+beLAB7oGp8 iumx+OvqS0zVj6MI/fkasvN/59W4X8WI/GfGqhJPUvOzdzShoNHzPpf3LeFALgbqFGDz UPxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488598; x=1691080598; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J5PRaqRDbG1q7cJ7k1FBCGAtKCCwmrJ591DUA034EE4=; b=ZbYgc6YgJl3yWjeVc7cInusQgILcaOOc4ZdiA29T4GhLmu8W+o9iiv8kC0+ubC3GpJ /VPwh1e+qNlQylIa+PjyesSLuO1cgLcxR3zT8mspHbu3OnArFMMUXniI+iYw0N8VE3cA zxUKao/aUx6+HGzCHWEv4Zc7hcZIfODwmFnhROx/gnj4JtEFnQquWYsA1HGJsEJlS/Z5 f9LU5JoDFAVF9Id0FvfOdF3TQY6D27ZfadYICX+5kxkuuymmSy2jdB/YcX7wI7L5jJZ4 GY0RrBtY3aPcVgCzSXC4c6Vvp5dkO48+Wd+HGybCBfQYEEHXjEyzKHehs2sZPkfwEHme gNmQ== X-Gm-Message-State: AC+VfDxFzsO65pIBGvlPG/EnI9H3IWKzP3/iQu8OO/NvtMZutF6CrkJo YtmoitTCavq1QpjpU1Wi20h69gPjnZIdTuDlGqM= X-Google-Smtp-Source: ACHHUZ6saCjGWpvFIsFAGERC+J93P/EHbEj2fMK3BrlSXu6skv5rVnke8HK8DespuMnJhiL1nrS4mw== X-Received: by 2002:a05:600c:b53:b0:3fb:416d:6358 with SMTP id k19-20020a05600c0b5300b003fb416d6358mr11402817wmr.16.1688488598346; Tue, 04 Jul 2023 09:36:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/11] target/arm: Handle IC IVAU to improve compatibility with JITs Date: Tue, 4 Jul 2023 17:36:29 +0100 Message-Id: <20230704163634.3188465-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488698075100001 From: John H=C3=B6gberg Unlike architectures with precise self-modifying code semantics (e.g. x86) ARM processors do not maintain coherency for instruction execution and memory, requiring an instruction synchronization barrier on every core that will execute the new code, and on many models also the explicit use of cache management instructions. While this is required to make JITs work on actual hardware, QEMU has gotten away with not handling this since it does not emulate caches, and unconditionally invalidates code whenever the softmmu or the user-mode page protection logic detects that code has been modified. Unfortunately the latter does not work in the face of dual-mapped code (a common W^X workaround), where one page is executable and the other is writable: user-mode has no way to connect one with the other as that is only known to the kernel and the emulated application. This commit works around the issue by telling software that instruction cache invalidation is required by clearing the CPR_EL0.DIC flag (regardless of whether the emulated processor needs it), and then invalidating code in IC IVAU instructions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034 Co-authored-by: Richard Henderson Signed-off-by: John H=C3=B6gberg Reviewed-by: Richard Henderson Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht [PMM: removed unnecessary AArch64 feature check; moved "clear CTR_EL1.DIC" code up a bit so it's not in the middle of the vfp/neon related tests] Signed-off-by: Peter Maydell --- target/arm/cpu.c | 11 +++++++++++ target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index adf84f96860..822efa5b2c1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1694,6 +1694,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 +#ifdef CONFIG_USER_ONLY + /* + * User mode relies on IC IVAU instructions to catch modification of + * dual-mapped code. + * + * Clear CTR_EL0.DIC to ensure that software that honors these flags u= ses + * IC IVAU even if the emulated processor does not normally require it. + */ + cpu->ctr =3D FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); +#endif + if (arm_feature(env, ARM_FEATURE_AARCH64) && cpu->has_vfp !=3D cpu->has_neon) { /* diff --git a/target/arm/helper.c b/target/arm/helper.c index a0b84efab52..8e836aaee13 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5234,6 +5234,36 @@ static void mdcr_el2_write(CPUARMState *env, const A= RMCPRegInfo *ri, } } =20 +#ifdef CONFIG_USER_ONLY +/* + * `IC IVAU` is handled to improve compatibility with JITs that dual-map t= heir + * code to get around W^X restrictions, where one region is writable and t= he + * other is executable. + * + * Since the executable region is never written to we cannot detect code + * changes when running in user mode, and rely on the emulated JIT telling= us + * that the code has changed by executing this instruction. + */ +static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t icache_line_mask, start_address, end_address; + const ARMCPU *cpu; + + cpu =3D env_archcpu(env); + + icache_line_mask =3D (4 << extract32(cpu->ctr, 0, 4)) - 1; + start_address =3D value & ~icache_line_mask; + end_address =3D value | icache_line_mask; + + mmap_lock(); + + tb_invalidate_phys_range(start_address, end_address); + + mmap_unlock(); +} +#endif + static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* * Minimal set of EL0-visible registers. This will need to be expanded @@ -5273,7 +5303,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 4, .crm =3D 2, .access =3D PL1_R, .type =3D ARM_CP_CURRENTEL }, - /* Cache ops: all NOPs since we don't emulate caches */ + /* + * Instruction cache ops. All of these except `IC IVAU` NOP because we + * don't emulate caches. + */ { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, @@ -5286,9 +5319,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D access_tocu }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, + .access =3D PL0_W, .fgt =3D FGT_ICIVAU, - .accessfn =3D access_tocu }, + .accessfn =3D access_tocu, +#ifdef CONFIG_USER_ONLY + .type =3D ARM_CP_NO_RAW, + .writefn =3D ic_ivau_write +#else + .type =3D ARM_CP_NOP +#endif + }, + /* Cache ops: all NOPs since we don't emulate caches */ { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, --=20 2.34.1 From nobody Mon May 13 12:25:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688488718; cv=none; d=zohomail.com; s=zohoarc; b=NLL20nlI/xcDY6Avvoxs+dGlY7VjpOHkXwgfE4M+mcozyjS9vberHhK052qQZOPxIIYsUIuI7VMtQIAg2w9rVps7vgrXKTyhFOvovkpF4YFSZaRW1CGteaiU5oKL9LyJqbhNSEW9vHelGu2ZxfJBvtL02wJGxZVTSwKTnpqBOh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688488718; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1+5gA5Gx3OWByEd+ONnCyhPvuTERrBtfW0lccmJX71g=; b=UNzFrgBOKyUMjayLTYGV1Alpr2sq7Z4anuXQ+ZFk2+dvXcZ6xaewkKdgpLTkCyWKjLYvD3S60NowWJg2gxfO56AZPnbqB1fV5zgxkqJLkOhgxgnJj2VDjuQ039oRB5CsxEAx7umXfpOdAPv0p7X2MOwqfwOaYvWJ4aT7/4WN7jw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688488718670500.1758215584091; Tue, 4 Jul 2023 09:38:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGj1D-0001Jv-Rx; Tue, 04 Jul 2023 12:36:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGj1B-0001HU-L3 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:45 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGj16-0001oQ-Dn for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:42 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3094910b150so6599627f8f.0 for ; Tue, 04 Jul 2023 09:36:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488719643100001 From: John H=C3=B6gberg https://gitlab.com/qemu-project/qemu/-/issues/1034 Signed-off-by: John H=C3=B6gberg Message-id: 168778890374.24232.3402138851538068785-2@git.sr.ht Reviewed-by: Peter Maydell [PMM: fixed typo in comment] Signed-off-by: Peter Maydell --- tests/tcg/aarch64/icivau.c | 189 ++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 3 +- 2 files changed, 191 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/icivau.c diff --git a/tests/tcg/aarch64/icivau.c b/tests/tcg/aarch64/icivau.c new file mode 100644 index 00000000000..77b9e98d5e5 --- /dev/null +++ b/tests/tcg/aarch64/icivau.c @@ -0,0 +1,189 @@ +/* + * Tests the IC IVAU-driven workaround for catching changes made to dual-m= apped + * code that would otherwise go unnoticed in user mode. + * + * Copyright (c) 2023 Ericsson AB + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_CODE_SIZE 128 + +typedef int (SelfModTest)(uint32_t, uint32_t*); +typedef int (BasicTest)(int); + +static void mark_code_modified(const uint32_t *exec_data, size_t length) +{ + int dc_required, ic_required; + unsigned long ctr_el0; + + /* + * Clear the data/instruction cache, as indicated by the CTR_ELO.{DIC,= IDC} + * flags. + * + * For completeness we might be tempted to assert that we should fail = when + * the whole code update sequence is omitted, but that would make the = test + * flaky as it can succeed by coincidence on actual hardware. + */ + asm ("mrs %0, ctr_el0\n" : "=3Dr"(ctr_el0)); + + /* CTR_EL0.IDC */ + dc_required =3D !((ctr_el0 >> 28) & 1); + + /* CTR_EL0.DIC */ + ic_required =3D !((ctr_el0 >> 29) & 1); + + if (dc_required) { + size_t dcache_stride, i; + + /* + * Step according to the minimum cache size, as the cache maintena= nce + * instructions operate on the cache line of the given address. + * + * We assume that exec_data is properly aligned. + */ + dcache_stride =3D (4 << ((ctr_el0 >> 16) & 0xF)); + + for (i =3D 0; i < length; i +=3D dcache_stride) { + const char *dc_addr =3D &((const char *)exec_data)[i]; + asm volatile ("dc cvau, %x[dc_addr]\n" + : /* no outputs */ + : [dc_addr] "r"(dc_addr) + : "memory"); + } + + asm volatile ("dmb ish\n"); + } + + if (ic_required) { + size_t icache_stride, i; + + icache_stride =3D (4 << (ctr_el0 & 0xF)); + + for (i =3D 0; i < length; i +=3D icache_stride) { + const char *ic_addr =3D &((const char *)exec_data)[i]; + asm volatile ("ic ivau, %x[ic_addr]\n" + : /* no outputs */ + : [ic_addr] "r"(ic_addr) + : "memory"); + } + + asm volatile ("dmb ish\n"); + } + + asm volatile ("isb sy\n"); +} + +static int basic_test(uint32_t *rw_data, const uint32_t *exec_data) +{ + /* + * As user mode only misbehaved for dual-mapped code when previously + * translated code had been changed, we'll start off with this basic t= est + * function to ensure that there's already some translated code at + * exec_data before the next test. This should cause the next test to = fail + * if `mark_code_modified` fails to invalidate the code. + * + * Note that the payload is in binary form instead of inline assembler + * because we cannot use __attribute__((naked)) on this platform and t= he + * workarounds are at least as ugly as this is. + */ + static const uint32_t basic_payload[] =3D { + 0xD65F03C0 /* 0x00: RET */ + }; + + BasicTest *copied_ptr =3D (BasicTest *)exec_data; + + memcpy(rw_data, basic_payload, sizeof(basic_payload)); + mark_code_modified(exec_data, sizeof(basic_payload)); + + return copied_ptr(1234) =3D=3D 1234; +} + +static int self_modification_test(uint32_t *rw_data, const uint32_t *exec_= data) +{ + /* + * This test is self-modifying in an attempt to cover an edge case whe= re + * the IC IVAU instruction invalidates itself. + * + * Note that the IC IVAU instruction is 16 bytes into the function, in= what + * will be the same cache line as the modified instruction on machines= with + * a cache line size >=3D 16 bytes. + */ + static const uint32_t self_mod_payload[] =3D { + /* Overwrite the placeholder instruction with the new one. */ + 0xB9001C20, /* 0x00: STR w0, [x1, 0x1C] */ + + /* Get the executable address of the modified instruction. */ + 0x100000A8, /* 0x04: ADR x8, <0x1C> */ + + /* Mark the modified instruction as updated. */ + 0xD50B7B28, /* 0x08: DC CVAU x8 */ + 0xD5033BBF, /* 0x0C: DMB ISH */ + 0xD50B7528, /* 0x10: IC IVAU x8 */ + 0xD5033BBF, /* 0x14: DMB ISH */ + 0xD5033FDF, /* 0x18: ISB */ + + /* Placeholder instruction, overwritten above. */ + 0x52800000, /* 0x1C: MOV w0, 0 */ + + 0xD65F03C0 /* 0x20: RET */ + }; + + SelfModTest *copied_ptr =3D (SelfModTest *)exec_data; + int i; + + memcpy(rw_data, self_mod_payload, sizeof(self_mod_payload)); + mark_code_modified(exec_data, sizeof(self_mod_payload)); + + for (i =3D 1; i < 10; i++) { + /* Replace the placeholder instruction with `MOV w0, i` */ + uint32_t new_instr =3D 0x52800000 | (i << 5); + + if (copied_ptr(new_instr, rw_data) !=3D i) { + return 0; + } + } + + return 1; +} + +int main(int argc, char **argv) +{ + const char *shm_name =3D "qemu-test-tcg-aarch64-icivau"; + int fd; + + fd =3D shm_open(shm_name, O_CREAT | O_RDWR, S_IRUSR | S_IWUSR); + + if (fd < 0) { + return EXIT_FAILURE; + } + + /* Unlink early to avoid leaving garbage in case the test crashes. */ + shm_unlink(shm_name); + + if (ftruncate(fd, MAX_CODE_SIZE) =3D=3D 0) { + const uint32_t *exec_data; + uint32_t *rw_data; + + rw_data =3D mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + exec_data =3D mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_EXEC, + MAP_SHARED, fd, 0); + + if (rw_data && exec_data) { + if (basic_test(rw_data, exec_data) && + self_modification_test(rw_data, exec_data)) { + return EXIT_SUCCESS; + } + } + } + + return EXIT_FAILURE; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 97cfc43600a..bf9d21d72fb 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -9,9 +9,10 @@ AARCH64_SRC=3D$(SRC_PATH)/tests/tcg/aarch64 VPATH +=3D $(AARCH64_SRC) =20 # Base architecture tests -AARCH64_TESTS=3Dfcvt pcalign-a64 +AARCH64_TESTS=3Dfcvt pcalign-a64 icivau =20 fcvt: LDFLAGS+=3D-lm +icivau: LDFLAGS+=3D-lrt =20 run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") --=20 2.34.1 From nobody Mon May 13 12:25:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488599; x=1691080599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eZRfw+Y+qoCHkLPcJJixub5r6MA4gHrUcY1/kPyyLV8=; b=SL8Nrpcw5kNmqXkEYA6axmI+XtxoWUkl7qvZZDQ5XBUsVmZlTEXmbcXs8fZKIFFmzF ejSVO7dDT9M442Uk1Ln7WR2kBMNZq2Lmy3FdPOvBaSgwaoNjeHN4PnS0kU4DKnx0pgGo +eLRlfrBoWT2PC7YgmHUCOZNq587IAh9K2TwARDnh2JzwG/pV8AzsMpT2RcwNzvziyUx oE5CmQXjfRH48zqxtWtBMMsb/yhIlCYg2ZAOz5tp2uKKZY3JSnk+pVcenwQXQMjT8Q+Y RNc7lVCtReZwUlPvEcUv1br5BpmY871zZyk6lyTHZzBPEKdSpAoMVEMxWElUdsgXlVXn /qOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488599; x=1691080599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eZRfw+Y+qoCHkLPcJJixub5r6MA4gHrUcY1/kPyyLV8=; b=dfD1xpDQ04djsFRet3EIrW+rnUKR3L8bj3dXvlJ7+ebYSf4UnJXNLIDsybgdgY17rz QSnxoo39XgP/+c0QrMEA+WKljfyX+A0h2CyIg+MX9AgUQ7u3jql3P0v2Z6LP2Gs2y3dA lBfZtTNiKNEKJxcHHmfd9k2a1td/84reUS6Q+f7T53B0tw28IeNN1GcSNR5gPKVfLHVu hGcgss8BRa+M+/ReZX98yYd35eBNxPncMTlXb27l5aDdVy6DdMaGUrRvIt6gDGJdbX+V mxPRs/6k5uOWrF1hUjs0RbmnOE3ubm/LpYNU3Hjnr8FqvOu89e5u3ODniDP+Xq6xilBk HqdA== X-Gm-Message-State: AC+VfDwA5YdfsMADilC6f1/Gm04IZ+JIAaQH0kH6KeO8RyxcBKtCnPTU UXzSZ8C0bF2+KQTI75sgcHKislTnq7g4cjhSP1I= X-Google-Smtp-Source: ACHHUZ7l4n+R9CcWMjga2lSG9GPDCWpmP9XmYWz5aO9SVIknbAu9LTDcwmwXrDJxV0BUKf0P3oYnqw== X-Received: by 2002:a5d:6308:0:b0:30f:c050:88dd with SMTP id i8-20020a5d6308000000b0030fc05088ddmr16419155wru.8.1688488599139; Tue, 04 Jul 2023 09:36:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/11] tests/qtest: xlnx-canfd-test: Fix code coverity issues Date: Tue, 4 Jul 2023 17:36:31 +0100 Message-Id: <20230704163634.3188465-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488641620100003 Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal Following are done to fix the coverity issues: 1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN) 2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE) 3. Replace rand() in generate_random_data() with g_rand_int() Signed-off-by: Vikram Garhwal Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/xlnx-canfd-test.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/tests/qtest/xlnx-canfd-test.c b/tests/qtest/xlnx-canfd-test.c index 76ee106d4f4..78ec9ef2a76 100644 --- a/tests/qtest/xlnx-canfd-test.c +++ b/tests/qtest/xlnx-canfd-test.c @@ -170,23 +170,23 @@ static void generate_random_data(uint32_t *buf_tx, bo= ol is_canfd_frame) /* Generate random TX data for CANFD frame. */ if (is_canfd_frame) { for (int i =3D 0; i < CANFD_FRAME_SIZE - 2; i++) { - buf_tx[2 + i] =3D rand(); + buf_tx[2 + i] =3D g_random_int(); } } else { /* Generate random TX data for CAN frame. */ for (int i =3D 0; i < CAN_FRAME_SIZE - 2; i++) { - buf_tx[2 + i] =3D rand(); + buf_tx[2 + i] =3D g_random_int(); } } } =20 -static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *b= uf_rx) +static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *b= uf_rx, + uint32_t frame_size) { uint32_t int_status; uint32_t fifo_status_reg_value; /* At which RX FIFO the received data is stored. */ uint8_t store_ind =3D 0; - bool is_canfd_frame =3D false; =20 /* Read the interrupt on CANFD rx. */ int_status =3D qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RX= OK; @@ -207,16 +207,9 @@ static void read_data(QTestState *qts, uint64_t can_ba= se_addr, uint32_t *buf_rx) buf_rx[0] =3D qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET); buf_rx[1] =3D qtest_readl(qts, can_base_addr + R_RX0_DLC_OFFSET); =20 - is_canfd_frame =3D (buf_rx[1] >> DLC_FD_BIT_SHIFT) & 1; - - if (is_canfd_frame) { - for (int i =3D 0; i < CANFD_FRAME_SIZE - 2; i++) { - buf_rx[i + 2] =3D qtest_readl(qts, - can_base_addr + R_RX0_DATA1_OFFSET + 4= * i); - } - } else { - buf_rx[2] =3D qtest_readl(qts, can_base_addr + R_RX0_DATA1_OFFSET); - buf_rx[3] =3D qtest_readl(qts, can_base_addr + R_RX0_DATA2_OFFSET); + for (int i =3D 0; i < frame_size - 2; i++) { + buf_rx[i + 2] =3D qtest_readl(qts, + can_base_addr + R_RX0_DATA1_OFFSET + 4 * i= ); } =20 /* Clear the RX interrupt. */ @@ -272,10 +265,6 @@ static void match_rx_tx_data(const uint32_t *buf_tx, c= onst uint32_t *buf_rx, g_assert_cmpint((buf_rx[size] & DLC_FD_BIT_MASK), =3D=3D, (buf_tx[size] & DLC_FD_BIT_MASK)); } else { - if (!is_canfd_frame && size =3D=3D 4) { - break; - } - g_assert_cmpint(buf_rx[size], =3D=3D, buf_tx[size]); } =20 @@ -318,7 +307,7 @@ static void test_can_data_transfer(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, false); =20 send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CAN_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, false); =20 qtest_quit(qts); @@ -358,7 +347,7 @@ static void test_canfd_data_transfer(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, true); =20 send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); =20 qtest_quit(qts); @@ -397,7 +386,7 @@ static void test_can_loopback(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, true); =20 send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD0_BASE_ADDR, buf_rx); + read_data(qts, CANFD0_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); =20 generate_random_data(buf_tx, true); @@ -405,7 +394,7 @@ static void test_can_loopback(void) write_data(qts, CANFD1_BASE_ADDR, buf_tx, true); =20 send_data(qts, CANFD1_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); =20 qtest_quit(qts); --=20 2.34.1 From nobody Mon May 13 12:25:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688488691; cv=none; d=zohomail.com; s=zohoarc; b=Lp6tT8GXea2APS5OW5SxLoKHoK2S36YIxXMrhjoru+Ij8VzentqMmfjeE6rilpkJccZNfb9GOjpoSbt3aN6dFl2kJOuDxi6MTZle2CZs/zD9hOyO/7inWz7fK8qPOfsWxVOHI3aECtlUqHII51pN+HyV9Vso8Vn1xveiOXcnrEw= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488599; x=1691080599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VCXSlv9PBlqNWlv08FHro1sfFi0JArXLUvRt7UUYed4=; b=m4etLuyCJXHo8lsBDWWsCkVfJNGu5WCznPshiCzz32kHKxiPnaOGNUcuK55flcCzWl WJy5PfnXm6Fb5Rn1XhBTnUA+VVJfB435B59wVt7QtVN4HDwmIx2AXtVuEEphVi1+wK5C UCgL5llciq/MAT9XQ5wluppk6XzVCKGKJikpXdPNErhbR298uuK8n2Hh1edBJMQmSClY kbrp2uzeCexialr0DTKrmiypCP3Yb7hQy4Xp3A4ZG+/uY4so/KeLEmUeiRvDZ6AI1zxd ZS8zfF/botD4dTZ/q//Gg9zFgYFHsZzbUgYpgnfzBe8KzYVon3Ew2wu8mIKuKWFf4GHK p0BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488599; x=1691080599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VCXSlv9PBlqNWlv08FHro1sfFi0JArXLUvRt7UUYed4=; b=kfiisAEB5z6swM6kWcTYkdSSVniEcfy+OGezkbtWGmm/h7LgGVDKrsIZPgXIU7LTh/ H8VztuS1AqJihBxtMkwStZ2mvdaM5wdv3VOUsBqgFRPe8Yq7Xc4bJGe7p5YDaYDfaznm Su5ZX2N79xgizTj6kEe07BZXAJ8zldsLEqIEeYUVOj182pJfWHapsPxxbO4awJIfPYNl lg+AZbhHiBspeUoV4PBUr4+Uf4YkxcZMttHOiswafWdylCs9RtmT+hfaBq5UT7DggdyW DIzW6BDIAmN1vtVnBNms7kdRAIP8DfcWCOTfGingBsxty8Cxb88suf04QF9tvUUXLDgG jYJQ== X-Gm-Message-State: ABy/qLYdaR2dzkEkPmBfe/bdAWudwq8MYp5S9moud7zmcvlsG7P9f5BQ HUVTrZupUF7fjVJ2JXGK2BsdEpGQ4vmbQWGCWxw= X-Google-Smtp-Source: APBJJlGDj86lO/74E5DZ+KK/ZHsk2VH2UWzSvl5stCtsA7Bon6+A9hQNm3p2TJzC28stIHtKnV2pUw== X-Received: by 2002:adf:e483:0:b0:30a:f030:8637 with SMTP id i3-20020adfe483000000b0030af0308637mr11570491wrm.22.1688488599547; Tue, 04 Jul 2023 09:36:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/11] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG Date: Tue, 4 Jul 2023 17:36:32 +0100 Message-Id: <20230704163634.3188465-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488691631100009 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas This code is only relevant when TCG is present in the build. Building with --disable-tcg --enable-xen on an x86 host we get: $ ../configure --target-list=3Dx86_64-softmmu,aarch64-softmmu --disable-tcg= --enable-xen $ make -j$(nproc) ... libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_= ptr': ../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr' ../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr' libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `arm_gdb_g= et_m_systemreg': ../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control' Signed-off-by: Fabiano Rosas Message-id: 20230628164821.16771-1-farosas@suse.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/gdbstub.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 03b17c814f6..f421c5d041c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -324,6 +324,7 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int= base_reg) return cpu->dyn_sysreg_xml.num; } =20 +#ifdef CONFIG_TCG typedef enum { M_SYSREG_MSP, M_SYSREG_PSP, @@ -481,6 +482,7 @@ static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs= , int orig_base_reg) return cpu->dyn_m_secextreg_xml.num; } #endif +#endif /* CONFIG_TCG */ =20 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { @@ -561,6 +563,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), "system-registers.xml", 0); =20 +#ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, @@ -575,4 +578,5 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) } #endif } +#endif /* CONFIG_TCG */ } --=20 2.34.1 From nobody Mon May 13 12:25:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688488690; cv=none; d=zohomail.com; s=zohoarc; b=eqzIjd55TVyn4BUV31uL7znZkNxMc1trX0ZjxZQAE0gOS+ixB8NMVYhrlYcTnE6WmTIaiKk1hb759Adfk0/9A7TmF/rZZgspGagKvMw4gDW4X+mOg6xcCv8k/GONYoZ2RMZLY4VelA9Pr2k30QuIKpnK+Uywf/UvOXbC0GrDPOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688488690; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ljXuz5WdOwWpxwvCuXAlprlm5SQ6d0e/c1sdlk1yWik=; b=J1lnPLZkLUPkRQgb0WlQDRKBLPJUUBoe8mHwVD2VQj5uWtn+2h7lldpE5/XgVtgM6kxAzEyKBkMFEacuXkhT+64J3bERS9aFqo12sahFPnTXrgP5zpPZ845mBzwdHufdnhW+vJ6R8IX3mEeZ3wkP+uSvlzBT20XPC+ZZQKXzO+k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688488690626858.5083095270854; Tue, 4 Jul 2023 09:38:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGj1H-0001Nw-QM; Tue, 04 Jul 2023 12:36:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGj1E-0001K0-B2 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:48 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGj1B-0001pp-9B for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:48 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-314319c0d3eso3393189f8f.0 for ; Tue, 04 Jul 2023 09:36:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488600; x=1691080600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ljXuz5WdOwWpxwvCuXAlprlm5SQ6d0e/c1sdlk1yWik=; b=iXQM3l4hIFS+7AgtV7coajaTKojqc5SP+UnAAVjX2oNehd7JUbojq/oa1H12WjV09a JzPapmmFQbwhq2+QJRsaS6GPDTvpkfdpjk7X6L/Y0RSa+wCRX9+WK+ZDn0LZpGvPBM0j y1ufWMvL8ky/OT8yMqHtnAsqSK+3r8X/PdJRrgga2vDmOzXfkgYuOgU8e0Xv2+fQl5J7 zJB0k0DDNHlUZCHcps8TJtrZCapbpUhpzKOTJkQLk+lEAoE0sBCB+awN+nB0qR2jdxyO 5AI9/ctuoCf5wVJ43Abh9+2tHSU/AjvvYoHruQG+3TVQeJaP7kZ/74YdIvDDUjWJx932 d/Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488600; x=1691080600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ljXuz5WdOwWpxwvCuXAlprlm5SQ6d0e/c1sdlk1yWik=; b=TUoi/d7Hg5lndLRGVRBaQrJ3bGoCRjUe73p0Ivcubwxet/9ZQyR3Pc9tD4Qus6q+qV kJim6peHlLH5moGuOpZmJiXZyWADfn6lLBzlDWzh4SO6P+4/K1oVGfKDZR2q8poZL+p0 XQO4TQbX7/E6J/b4yJGRbKGch8yZ3oN8e6bKrc4GAkvQaBG7PcrAyMCsyAbkOXKFOLr4 48mIl7Qs5eBzMwHcxRpQaPBrQ8HvS4FtOM83LPrPYXkJr4Ura8dCpi6ICGDfVblk0a8m Ezm3Gw7anYafeyhepxbteZRbEe7tfvHoEOS5XcNFe43hJRHYdQrI2nwreq64+1qjHsn6 ZhzQ== X-Gm-Message-State: ABy/qLYrF7j5ivbgxvazxqKJZD8UcHfJIRxOwzqFRvYW4/7xT53dG526 MUPjnqNDv00yj4EEOCrxyXcP0T4ImAs5C/D3Rvk= X-Google-Smtp-Source: APBJJlF2Milc/X+BkhYVTPEkKqKlfiL63NxEES8z/o0ze5k/XgXSeaLkaO85QYKyFoN0+YxDu3aCaQ== X-Received: by 2002:adf:efca:0:b0:314:3587:ec72 with SMTP id i10-20020adfefca000000b003143587ec72mr6508721wrp.69.1688488600149; Tue, 04 Jul 2023 09:36:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/11] hw: arm: allwinner-sramc: Set class_size Date: Tue, 4 Jul 2023 17:36:33 +0100 Message-Id: <20230704163634.3188465-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488691427100005 From: Akihiko Odaki AwSRAMCClass is larger than SysBusDeviceClass so the class size must be advertised accordingly. Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support f= or R40") Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com Signed-off-by: Peter Maydell --- hw/misc/allwinner-sramc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c index a8b731f8f28..d76c24d081f 100644 --- a/hw/misc/allwinner-sramc.c +++ b/hw/misc/allwinner-sramc.c @@ -159,6 +159,7 @@ static const TypeInfo allwinner_sramc_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_init =3D allwinner_sramc_init, .instance_size =3D sizeof(AwSRAMCState), + .class_size =3D sizeof(AwSRAMCClass), .class_init =3D allwinner_sramc_class_init, }; =20 --=20 2.34.1 From nobody Mon May 13 12:25:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688488689; cv=none; d=zohomail.com; s=zohoarc; b=E/QFP57YdxGa+vC+AG2rdw6fHsz2sdd+QbowUtb5aEeOmJbXPgGY97pfv9yGXqr+PLxvFIQgCksiPKBZBKqudRZ0RzBlzf1SGvIiQhkgFzIIWFywMDjN9KohQNRNRa5Tygu1R5Rv4kuksX/9lgpOUrI/d1z5gpmZo5dXfFbpB+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688488689; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=REQxdvHqMD5dtevjQjK3Wnx/HFYuQ118HppndU5qJ5M=; b=XOGKA90ZEGtQsGSStzzbmkjfzQ+Sg0SLMlLX1/L0lJp9pjKOy2lzRiM1aTOA2kJ6xBJXf3rFdt1nGqsGCag1LKy6i666H4IMK8IPySVdX3NQG2WK4eIBtEtiR1SWd+GLtCZE9DlpU5YnsgCcVR5b7IaVW24Y+v0RMaqVegCF0FI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168848868965985.85207237087855; Tue, 4 Jul 2023 09:38:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGj1H-0001MV-7N; Tue, 04 Jul 2023 12:36:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGj1E-0001Jy-9I for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:48 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGj1B-0001q0-7y for qemu-devel@nongnu.org; Tue, 04 Jul 2023 12:36:48 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3143ccb0f75so1564019f8f.0 for ; Tue, 04 Jul 2023 09:36:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688488600; x=1691080600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=REQxdvHqMD5dtevjQjK3Wnx/HFYuQ118HppndU5qJ5M=; b=CRa2WQ7kV4gpM/nsg/Kd4DyhiYAfcXKhsZFfcOQa8ILOkYJSdX+GN3PifsLNC+VIlg pn+tRnqo7CY9H4JRmR/Gmtp+HQbNgsrjZBsyVhZoOMpWQ6WH0YELj26jBS5ZiCg6fmn/ /gAfkYfrOIBlxaPdyBzpq58SdZUeKjUxvcufw/2kX9WqeofT06TaIRYJqEktyHMNjED9 LG3l0O5CSm99Nv/aqSnoPWnvyAziI27eCRW5sjDe0Serut7tuMnqRkHDjPcihsb3rUZA E50KKbiS0jw6fZF9nSZfm11xwKlV05Ca9OM4Mmkhs0iNwuZAHpzI+bDeTn5yp2B2M0CU hJ0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688488600; x=1691080600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=REQxdvHqMD5dtevjQjK3Wnx/HFYuQ118HppndU5qJ5M=; b=JE6KifgbcyvJx3QZmnoLI93h4K/vV0pquAmXvu+0o5JCHvZLTbY9lYEUPfJz4UVRAH Ldbs13hmx6Dlp1IZRUCMNAMj3Vd6cNgcW+Fp5w3EIBw9vxw4bMeaeJC+mtWxjwRXW0KL OufxlH0Y8SkEaiTymchhhE/CGKPX3hYBsYXdyCOvY76MYwBJwS22ywpA5mwFExqpXhPk DyHPEPNhb+MxdWD6G8txU8UQZZV/G+gUyRATaQbn6VAEal6eEf9j9NfqvFC/fKRTP57L rEu9faYD3vuTV08PdLa4N/rfvI4W1R397XSKfokKTA/S7tbPcNeNG24WP5kgbClVk1RV VhqQ== X-Gm-Message-State: ABy/qLbdQN7/DeTrx6bhJtIT+jrALZ7VI8IF1qg6ox3Ups2H+/86gyzo yctXB2eqDl0KNjfosINdOMeNQYjQCnh6zRzYQhg= X-Google-Smtp-Source: APBJJlGk2gX1pgqWsYCB335htuXRe5A6WQDnI5mLoI4tRuUOF9poypIftj7xriuQs4N9vV8M0j6ejg== X-Received: by 2002:a5d:4529:0:b0:314:388b:361b with SMTP id j9-20020a5d4529000000b00314388b361bmr7870389wra.12.1688488600526; Tue, 04 Jul 2023 09:36:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/11] target/xtensa: Assert that interrupt level is within bounds Date: Tue, 4 Jul 2023 17:36:34 +0100 Message-Id: <20230704163634.3188465-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688488691303100001 Content-Type: text/plain; charset="utf-8" In handle_interrupt() we use level as an index into the interrupt_vector[] array. This is safe because we have checked it against env->config->nlevel, but Coverity can't see that (and it is only true because each CPU config sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it complains about a possible array overrun (CID 1507131) Add an assert() which will make Coverity happy and catch the unlikely case of a mis-set XCHAL_NUM_INTLEVELS in future. Signed-off-by: Peter Maydell Acked-by: Max Filippov Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org --- target/xtensa/exc_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index d4823a65cda..43f6a862de2 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -169,6 +169,9 @@ static void handle_interrupt(CPUXtensaState *env) CPUState *cs =3D env_cpu(env); =20 if (level > 1) { + /* env->config->nlevel check should have ensured this */ + assert(level < sizeof(env->config->interrupt_vector)); + env->sregs[EPC1 + level - 1] =3D env->pc; env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; env->sregs[PS] =3D --=20 2.34.1