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Tue, 04 Jul 2023 07:51:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/19] hw/timer/arm_timer: Convert read/write handlers to MemoryRegionOps ones Date: Tue, 4 Jul 2023 16:50:02 +0200 Message-Id: <20230704145012.49870-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688482377166100001 In order to simplify the QOM convertion of ARM_TIMER in a few commits, start converting the read/write() handlers to follow the MemoryRegionOps::read/write() prototypes. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 0d7fac4d78..cbd82e8365 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -50,7 +50,7 @@ static void arm_timer_update(ArmTimer *s) } } =20 -static uint32_t arm_timer_read(void *opaque, hwaddr offset) +static uint64_t arm_timer_read(void *opaque, hwaddr offset, unsigned size) { ArmTimer *s =3D opaque; =20 @@ -97,7 +97,7 @@ static void arm_timer_recalibrate(ArmTimer *s, int reload) } =20 static void arm_timer_write(void *opaque, hwaddr offset, - uint32_t value) + uint64_t value, unsigned size) { ArmTimer *s =3D opaque; int freq; @@ -233,10 +233,10 @@ static uint64_t sp804_read(void *opaque, hwaddr offse= t, SP804Timer *s =3D opaque; =20 if (offset < 0x20) { - return arm_timer_read(s->timer[0], offset); + return arm_timer_read(&s->timer[0], offset, size); } if (offset < 0x40) { - return arm_timer_read(s->timer[1], offset - 0x20); + return arm_timer_read(&s->timer[1], offset - 0x20, size); } =20 /* TimerPeriphID */ @@ -265,12 +265,12 @@ static void sp804_write(void *opaque, hwaddr offset, SP804Timer *s =3D opaque; =20 if (offset < 0x20) { - arm_timer_write(s->timer[0], offset, value); + arm_timer_write(&s->timer[0], offset, value, size); return; } =20 if (offset < 0x40) { - arm_timer_write(s->timer[1], offset - 0x20, value); + arm_timer_write(&s->timer[1], offset - 0x20, value, size); return; } =20 @@ -356,7 +356,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offse= t, return 0; } =20 - return arm_timer_read(s->timer[n], offset & 0xff); + return arm_timer_read(&s->timer[n], offset & 0xff, size); } =20 static void icp_pit_write(void *opaque, hwaddr offset, @@ -371,7 +371,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, return; } =20 - arm_timer_write(s->timer[n], offset & 0xff, value); + arm_timer_write(&s->timer[n], offset & 0xff, value, size); } =20 static const MemoryRegionOps icp_pit_ops =3D { --=20 2.38.1