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Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen , Akihiko Odaki Subject: [PATCH v4 1/2] pcie: Use common ARI next function number Date: Tue, 4 Jul 2023 21:22:13 +0900 Message-ID: <20230704122215.23270-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230704122215.23270-1-akihiko.odaki@daynix.com> References: <20230704122215.23270-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::436; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1688473391682100009 Content-Type: text/plain; charset="utf-8" Currently the only implementers of ARI is SR-IOV devices, and they behave similar. Share the ARI next function number. Signed-off-by: Akihiko Odaki --- docs/pcie_sriov.txt | 4 ++-- include/hw/pci/pcie.h | 2 +- hw/net/igb.c | 2 +- hw/net/igbvf.c | 2 +- hw/nvme/ctrl.c | 2 +- hw/pci/pcie.c | 4 +++- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt index 7eff7f2703..a47aad0bfa 100644 --- a/docs/pcie_sriov.txt +++ b/docs/pcie_sriov.txt @@ -48,7 +48,7 @@ setting up a BAR for a VF. ... int ret =3D pcie_endpoint_cap_init(d, 0x70); ... - pcie_ari_init(d, 0x100, 1); + pcie_ari_init(d, 0x100); ... =20 /* Add and initialize the SR/IOV capability */ @@ -78,7 +78,7 @@ setting up a BAR for a VF. ... int ret =3D pcie_endpoint_cap_init(d, 0x60); ... - pcie_ari_init(d, 0x100, 1); + pcie_ari_init(d, 0x100); ... memory_region_init(mr, ... ) pcie_sriov_vf_register_bar(d, bar_nr, mr); diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 3cc2b15957..bf7dc5d685 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -134,7 +134,7 @@ void pcie_sync_bridge_lnk(PCIDevice *dev); void pcie_acs_init(PCIDevice *dev, uint16_t offset); void pcie_acs_reset(PCIDevice *dev); =20 -void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); +void pcie_ari_init(PCIDevice *dev, uint16_t offset); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_n= um); void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); =20 diff --git a/hw/net/igb.c b/hw/net/igb.c index 1c989d7677..8ff832acfc 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -431,7 +431,7 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error *= *errp) hw_error("Failed to initialize AER capability"); } =20 - pcie_ari_init(pci_dev, 0x150, 1); + pcie_ari_init(pci_dev, 0x150); =20 pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, TYPE_IGBVF, IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS, diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c index 284ea61184..d55e1e8a6a 100644 --- a/hw/net/igbvf.c +++ b/hw/net/igbvf.c @@ -270,7 +270,7 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **e= rrp) hw_error("Failed to initialize AER capability"); } =20 - pcie_ari_init(dev, 0x150, 1); + pcie_ari_init(dev, 0x150); } =20 static void igbvf_pci_uninit(PCIDevice *dev) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index fd917fcda1..8b7168a266 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8088,7 +8088,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) pcie_endpoint_cap_init(pci_dev, 0x80); pcie_cap_flr_init(pci_dev); if (n->params.sriov_max_vfs) { - pcie_ari_init(pci_dev, 0x100, 1); + pcie_ari_init(pci_dev, 0x100); } =20 /* add one to max_ioqpairs to account for the admin queue pair */ diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index b8c24cf45f..9a3f6430e8 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1028,8 +1028,10 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) */ =20 /* ARI */ -void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) +void pcie_ari_init(PCIDevice *dev, uint16_t offset) { + uint16_t nextfn =3D 1; + pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, offset, PCI_ARI_SIZEOF); pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); --=20 2.41.0