From nobody Fri May 10 12:05:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1688473390; cv=none; d=zohomail.com; s=zohoarc; b=YBMpkLJsTp1ZskuyazsyJeVotiQ0mMv5kZ9fonCv0zaAFMZ3H7/Kz1NEYWKL/wU80RHPrkw++b1MTrTPUbH2LzzOYUa1BeAd+un9gqUtoh6DRnbE+wyHiyuwCucDXcOKf3FIaLFNTLInBqC9AIS7rjMBx/KQNvEe0An3DjyHuiY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688473390; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=s02o4ecEeuNUThWPP1l7HSPv9qpDPaUhEuBGwN7hbWw=; b=NJXAjuQBUSGMcM3WlkG+hf/4sAO9msQIixOeQBRwMioiORhDUDFbEBULQmAvXUxBud6zuOAPEk6cDe8Ey3kHMFrzGyJAd97vb2F6rBhhXwZrlo+c/WIwI0TjK4Z79AOianzoiTm8ftSvy184YF5X4ZB/7G8yG3KQRbczppw5KS8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688473390406172.500274146092; Tue, 4 Jul 2023 05:23:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGf3H-0001v8-HB; Tue, 04 Jul 2023 08:22:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGf39-0001t8-Ju for qemu-devel@nongnu.org; Tue, 04 Jul 2023 08:22:32 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGf32-0007hr-RQ for qemu-devel@nongnu.org; Tue, 04 Jul 2023 08:22:27 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6686c74183cso4213292b3a.1 for ; Tue, 04 Jul 2023 05:22:24 -0700 (PDT) Received: from alarm.flets-east.jp ([2400:4050:a840:1e00:78d2:b862:10a7:d486]) by smtp.gmail.com with ESMTPSA id x48-20020a056a000bf000b0064d32771fa8sm11009743pfu.134.2023.07.04.05.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 05:22:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20221208.gappssmtp.com; s=20221208; t=1688473343; x=1691065343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s02o4ecEeuNUThWPP1l7HSPv9qpDPaUhEuBGwN7hbWw=; b=woiuYKY8I1A5KV8XKmaNiYng44z9CI4Sggm2B3N5dhvtuWBGZPpFkxYl00SisoTQVm 1iZSW+o0tdeovR72I5j3TiRO+fwNpbjpukZcV7GR4JfB6IvWWq9zhcv5Y612wXZ4UF2s rAKGGui5sF6jj0KF8iSrHvERA9Pv9Ag7OwdDTZ3IWQZQSQJvnnp/B3ww/lMeosxg3aqA FWYkSIkv0s/CaXVKPsAxrx8ZD0KHOgx/koi/FxwZeRKowMF4FNsNfwvWdGlPso/m0OOg yTDSgCTIhYflLbVJJPffBOcg389nEmedKn0kfjqtLHjeiUDoHqFTwDvBuoDexTKYy/Ko +o/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688473343; x=1691065343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s02o4ecEeuNUThWPP1l7HSPv9qpDPaUhEuBGwN7hbWw=; b=YykvnkSxlCWBZL2sF/pIZDgiF73pzQunCMzQ3Pqo0rX7yneTLCiOdLJw0FTAF2LOdE v8VHuq1pxOWGpXqCorgYRLyHOq/qEA6eC4aQmS4VtMqQPmt6Qq0AngpEXHEZI8ZypPs9 HHk29fi4CxTMZKpKexbnwcEeIL1CK4rPH7yz1xzK529jCYUYvpKMe2V+S7Twg5lWZ/sp OzPygo8e53tgiCgvYfNFBgb43Aqa8YPEUXz0GQ8iqlFr5t0Q8U0fB2r4giz318EoJamd P9ytXyEqWaa9utmQjbk7PdLTdHmIZmx0THvH2tigUQJufq3MQ026d4s/nIg+y+xD3fEU cGgw== X-Gm-Message-State: ABy/qLaDkM5zFyFp7vogpjbG/n5vp8d7z9ZPHf4t0pB5H99Hh035q73L V6JzzeTuVeZ8RMkxZNh49rZiievBvJoztaMDccU= X-Google-Smtp-Source: APBJJlGx0lQRi4rWSH6A9DDCY2ygvWObfz5ygpjcutdToTpfplLtVPek1bnwHl0RPL+HI4Ca6nisKQ== X-Received: by 2002:a05:6a00:1506:b0:668:97bf:5ed7 with SMTP id q6-20020a056a00150600b0066897bf5ed7mr19413219pfu.22.1688473343382; Tue, 04 Jul 2023 05:22:23 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Igor Mammedov , Ani Sinha , "Michael S . Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen , Akihiko Odaki Subject: [PATCH v4 1/2] pcie: Use common ARI next function number Date: Tue, 4 Jul 2023 21:22:13 +0900 Message-ID: <20230704122215.23270-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230704122215.23270-1-akihiko.odaki@daynix.com> References: <20230704122215.23270-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::436; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1688473391682100009 Content-Type: text/plain; charset="utf-8" Currently the only implementers of ARI is SR-IOV devices, and they behave similar. Share the ARI next function number. Signed-off-by: Akihiko Odaki --- docs/pcie_sriov.txt | 4 ++-- include/hw/pci/pcie.h | 2 +- hw/net/igb.c | 2 +- hw/net/igbvf.c | 2 +- hw/nvme/ctrl.c | 2 +- hw/pci/pcie.c | 4 +++- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt index 7eff7f2703..a47aad0bfa 100644 --- a/docs/pcie_sriov.txt +++ b/docs/pcie_sriov.txt @@ -48,7 +48,7 @@ setting up a BAR for a VF. ... int ret =3D pcie_endpoint_cap_init(d, 0x70); ... - pcie_ari_init(d, 0x100, 1); + pcie_ari_init(d, 0x100); ... =20 /* Add and initialize the SR/IOV capability */ @@ -78,7 +78,7 @@ setting up a BAR for a VF. ... int ret =3D pcie_endpoint_cap_init(d, 0x60); ... - pcie_ari_init(d, 0x100, 1); + pcie_ari_init(d, 0x100); ... memory_region_init(mr, ... ) pcie_sriov_vf_register_bar(d, bar_nr, mr); diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 3cc2b15957..bf7dc5d685 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -134,7 +134,7 @@ void pcie_sync_bridge_lnk(PCIDevice *dev); void pcie_acs_init(PCIDevice *dev, uint16_t offset); void pcie_acs_reset(PCIDevice *dev); =20 -void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); +void pcie_ari_init(PCIDevice *dev, uint16_t offset); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_n= um); void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); =20 diff --git a/hw/net/igb.c b/hw/net/igb.c index 1c989d7677..8ff832acfc 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -431,7 +431,7 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error *= *errp) hw_error("Failed to initialize AER capability"); } =20 - pcie_ari_init(pci_dev, 0x150, 1); + pcie_ari_init(pci_dev, 0x150); =20 pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, TYPE_IGBVF, IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS, diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c index 284ea61184..d55e1e8a6a 100644 --- a/hw/net/igbvf.c +++ b/hw/net/igbvf.c @@ -270,7 +270,7 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **e= rrp) hw_error("Failed to initialize AER capability"); } =20 - pcie_ari_init(dev, 0x150, 1); + pcie_ari_init(dev, 0x150); } =20 static void igbvf_pci_uninit(PCIDevice *dev) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index fd917fcda1..8b7168a266 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8088,7 +8088,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) pcie_endpoint_cap_init(pci_dev, 0x80); pcie_cap_flr_init(pci_dev); if (n->params.sriov_max_vfs) { - pcie_ari_init(pci_dev, 0x100, 1); + pcie_ari_init(pci_dev, 0x100); } =20 /* add one to max_ioqpairs to account for the admin queue pair */ diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index b8c24cf45f..9a3f6430e8 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1028,8 +1028,10 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) */ =20 /* ARI */ -void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) +void pcie_ari_init(PCIDevice *dev, uint16_t offset) { + uint16_t nextfn =3D 1; + pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, offset, PCI_ARI_SIZEOF); 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Tue, 04 Jul 2023 05:22:26 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Igor Mammedov , Ani Sinha , "Michael S . Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen , Akihiko Odaki Subject: [PATCH v4 2/2] pcie: Specify 0 for ARI next function numbers Date: Tue, 4 Jul 2023 21:22:14 +0900 Message-ID: <20230704122215.23270-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230704122215.23270-1-akihiko.odaki@daynix.com> References: <20230704122215.23270-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::530; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1688473392359100011 Content-Type: text/plain; charset="utf-8" The current implementers of ARI are all SR-IOV devices. The ARI next function number field is undefined for VF. The PF should end the linked list formed with the field by specifying 0. For migration, the field will keep having 1 as its value on the old virt models. Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in docs/pcie_sr= iov.txt") Fixes: 44c2c09488 ("hw/nvme: Add support for SR-IOV") Fixes: 3a977deebe ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h | 2 ++ hw/core/machine.c | 1 + hw/pci/pci.c | 2 ++ hw/pci/pcie.c | 2 +- 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e6d0574a29..9c5b5eb206 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -209,6 +209,8 @@ enum { QEMU_PCIE_CAP_CXL =3D (1 << QEMU_PCIE_CXL_BITNR), #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 QEMU_PCIE_ERR_UNC_MASK =3D (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), +#define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 + QEMU_PCIE_ARI_NEXTFN_1 =3D (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), }; =20 typedef struct PCIINTxRoute { diff --git a/hw/core/machine.c b/hw/core/machine.c index 46f8f9a2b0..f0d35c6401 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -41,6 +41,7 @@ =20 GlobalProperty hw_compat_8_0[] =3D { { "migration", "multifd-flush-after-each-section", "on"}, + { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, }; const size_t hw_compat_8_0_len =3D G_N_ELEMENTS(hw_compat_8_0); =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e2eb4c3b4a..45a9bc0da8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -82,6 +82,8 @@ static Property pci_props[] =3D { DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present, QEMU_PCIE_ERR_UNC_MASK_BITNR, true), + DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present, + QEMU_PCIE_ARI_NEXTFN_1_BITNR, false), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 9a3f6430e8..cf09e03a10 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1030,7 +1030,7 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) /* ARI */ void pcie_ari_init(PCIDevice *dev, uint16_t offset) { - uint16_t nextfn =3D 1; + uint16_t nextfn =3D dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0; =20 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, offset, PCI_ARI_SIZEOF); --=20 2.41.0