From nobody Wed Feb 11 03:02:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688409297; cv=none; d=zohomail.com; s=zohoarc; b=Z6a6VU9wUXXn0BUiQSf2tnRpMdINC5nuFBIAcItaz3Xi5Adlzo8WQNr7icnUJzwjDg01/+WCc6wiLra4/JJX6Ep3IX6eYt+rEvL+irmNxeabjEwD0qatwZGuQxbz0KzyNI8hAt4sWBR9LZgxGr1wHXL7X3pMENNrEasHTfIvQVc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688409297; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HaANU2OE+dOsUg4Qmvd15nGlRm3AOspQfp2v6+k0l68=; b=UOragr/T4a+taBAlrtYB5F1lD4Y70tICfpdybctH+KaRX91BbwQ7xN38fpQby+OoYMjA+FV+EeinuJXrdqYOyR4EUPEFNpASyJ8sOErvAnSWOpfiPO9it64Y9pQZXtdGXO+kbTB/1iHKvaiutw5xXdjoJnrSH4FPqB9klBHhPZY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688409297159946.1296725158809; Mon, 3 Jul 2023 11:34:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGOLu-0007ue-6Z; Mon, 03 Jul 2023 14:32:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGOLs-0007s9-3F for qemu-devel@nongnu.org; Mon, 03 Jul 2023 14:32:44 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGOLq-0000KW-4a for qemu-devel@nongnu.org; Mon, 03 Jul 2023 14:32:43 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3fbd33a57b6so34628415e9.2 for ; Mon, 03 Jul 2023 11:32:41 -0700 (PDT) Received: from localhost.localdomain ([176.176.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a1c7c05000000b003fbcf032c55sm7858298wmc.7.2023.07.03.11.32.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 03 Jul 2023 11:32:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688409160; x=1691001160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HaANU2OE+dOsUg4Qmvd15nGlRm3AOspQfp2v6+k0l68=; b=dBhqYCuSIEzANCxUAXby9VlxIR34zpNZ8YeMQorO4zF0KBBs1HfJOrAJvxcOjfT/Pw O2I8wq7ETsewUBimRDYGCRNrcjNChzFO+55y5HsykqOCmbchimowB0hbVw0mDB17UITh nfHY3nXQGzjWC7mNL7ggw52QTzK1VHxhAkWP65EBSp3HcZugl+ylTpW3cikJxJXjEeAf Zc5MOrxdgESwox5ntYodT32TU5B9x8KUmj7jp5SGHLIw+QP/CWbMaDBBmiFim2U3jKzh vMBkWHLLuwh/JmHz9lH264kXTzro4/g2eOwdyx+v0rmmUYszHUZrGesA9sVipiWatMhY e7dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688409160; x=1691001160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HaANU2OE+dOsUg4Qmvd15nGlRm3AOspQfp2v6+k0l68=; b=LoEZN5H/LJt9Fr+ODPn6QjhLUCQPVGtOM0lp493kRZ/J7H0QMG3J3aO0Ni1aJHBg4i 9a50Opb9BA0cMcgdrikWqIjYTyG6SrXE2zEr12CW6gqngyp+6XPTcsrcX6L9d+9ywGFo e0w6KlNSLQCxy61NxXptKrLuc4Nd4T9BwS7L7f9Psgdjr/1z4iQbiXNEXgad+I/TlWXT 6pFAlXXKrH5KXvMMkQf14ew6CtD3pvZLuiDDsONooIe6+7hU4tsM+gZfF4PRycvMxwjM rzBtw3itwo0C6EaZqIYDt6gT8XuVIGpKCkPMlMLhiurKTcSmRTnNwImfpNEdaIZOVZDG PDVA== X-Gm-Message-State: AC+VfDxENdpvjhay6CNDWcv+jnGZQaNV9KF10jzjqfim7tVwL7T6ZKg9 Jd42tMZ9EBewuVNK6cnQEjcUAe2vp8tfu3JzM9TEwA== X-Google-Smtp-Source: ACHHUZ461NN5mRHTbffGl+xf2Uo0+6rvuiaU6Ezwkrcd60e6xF8WSn7HX4bWp04sDxtrhLUWfvRy7Q== X-Received: by 2002:a1c:7405:0:b0:3fa:935e:e185 with SMTP id p5-20020a1c7405000000b003fa935ee185mr14601140wmc.22.1688409160319; Mon, 03 Jul 2023 11:32:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 08/16] target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c Date: Mon, 3 Jul 2023 20:31:37 +0200 Message-Id: <20230703183145.24779-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409297417100001 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu_helper.c | 84 ------------------------------- target/riscv/tcg/cpu.c | 98 ++++++++++++++++++++++++++++++++++++ target/riscv/tcg/meson.build | 1 + 3 files changed, 99 insertions(+), 84 deletions(-) create mode 100644 target/riscv/tcg/cpu.c diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 597c47bc56..6f8778c6d3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -64,90 +64,6 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - RISCVExtStatus fs, vs; - uint32_t flags =3D 0; - - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - - if (cpu->cfg.ext_zve32f) { - /* - * If env->vl equals to VLMAX, we can use generic vector operation - * expanders (GVEC) to accerlate the vector operations. - * However, as LMUL could be a fractional number. The maximum - * vector size can be operated might be less than 8 bytes, - * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue - * only when maxsz >=3D 8 bytes. - */ - uint32_t vlmax =3D vext_get_vlmax(cpu, env->vtype); - uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t maxsz =3D vlmax << sew; - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && - (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); - flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); - } else { - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - fs =3D EXT_STATUS_DIRTY; - vs =3D EXT_STATUS_DIRTY; -#else - flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - - flags |=3D cpu_mmu_index(env, 0); - fs =3D get_field(env->mstatus, MSTATUS_FS); - vs =3D get_field(env->mstatus, MSTATUS_VS); - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } - - /* With Zfinx, floating point is enabled/disabled by Smstateen. */ - if (!riscv_has_ext(env, RVF)) { - fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) - ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; - } - - if (cpu->cfg.debug && !icount_enabled()) { - flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); - } -#endif - - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); - flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - if (env->cur_pmmask !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); - } - if (env->cur_pmbase !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); - } - - *pflags =3D flags; -} - void riscv_cpu_update_mask(CPURISCVState *env) { target_ulong mask =3D 0, base =3D 0; diff --git a/target/riscv/tcg/cpu.c b/target/riscv/tcg/cpu.c new file mode 100644 index 0000000000..2ae6919b80 --- /dev/null +++ b/target/riscv/tcg/cpu.c @@ -0,0 +1,98 @@ +/* + * RISC-V CPU helpers (TCG specific) + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#ifndef CONFIG_USER_ONLY +#include "sysemu/cpu-timers.h" +#endif + +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + RISCVExtStatus fs, vs; + uint32_t flags =3D 0; + + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; + *cs_base =3D 0; + + if (cpu->cfg.ext_zve32f) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ + uint32_t vlmax =3D vext_get_vlmax(cpu, env->vtype); + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz =3D vlmax << sew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && + (maxsz >=3D 8); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); + } else { + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; +#else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + + flags |=3D cpu_mmu_index(env, 0); + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); + + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } + + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + + if (cpu->cfg.debug && !icount_enabled()) { + flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); + } +#endif + + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + if (env->cur_pmmask !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); + } + if (env->cur_pmbase !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); + } + + *pflags =3D flags; +} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index 65670493b1..a615aafd9a 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -8,6 +8,7 @@ gen =3D [ riscv_ss.add(when: 'CONFIG_TCG', if_true: gen) =20 riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cpu.c', 'fpu_helper.c', 'op_helper.c', 'vector_helper.c', --=20 2.38.1