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Fri, 30 Jun 2023 23:55:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 07/11] target/alpha: Use float64_to_int64_modulo for CVTTQ Date: Sat, 1 Jul 2023 08:55:06 +0200 Message-Id: <20230701065510.514743-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230701065510.514743-1-richard.henderson@linaro.org> References: <20230701065510.514743-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688194633729100003 For the most part we can use the new generic routine, though exceptions need some post-processing to sort invalid from integer overflow. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230527141910.1885950-4-richard.henderson@linaro.org> --- target/alpha/fpu_helper.c | 85 +++++++++------------------------------ 1 file changed, 18 insertions(+), 67 deletions(-) diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 3ff8bb456d..63d9e9ce39 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -453,78 +453,29 @@ uint64_t helper_cvtqs(CPUAlphaState *env, uint64_t a) =20 static uint64_t do_cvttq(CPUAlphaState *env, uint64_t a, int roundmode) { - uint64_t frac, ret =3D 0; - uint32_t exp, sign, exc =3D 0; - int shift; + float64 fa; + int64_t ret; + uint32_t exc; =20 - sign =3D (a >> 63); - exp =3D (uint32_t)(a >> 52) & 0x7ff; - frac =3D a & 0xfffffffffffffull; + fa =3D t_to_float64(a); + ret =3D float64_to_int64_modulo(fa, roundmode, &FP_STATUS); =20 - if (exp =3D=3D 0) { - if (unlikely(frac !=3D 0) && !env->fp_status.flush_inputs_to_zero)= { - goto do_underflow; - } - } else if (exp =3D=3D 0x7ff) { - exc =3D FPCR_INV; - } else { - /* Restore implicit bit. */ - frac |=3D 0x10000000000000ull; + exc =3D get_float_exception_flags(&FP_STATUS); + if (unlikely(exc)) { + set_float_exception_flags(0, &FP_STATUS); =20 - shift =3D exp - 1023 - 52; - if (shift >=3D 0) { - /* In this case the number is so large that we must shift - the fraction left. There is no rounding to do. */ - if (shift < 64) { - ret =3D frac << shift; - } - /* Check for overflow. Note the special case of -0x1p63. */ - if (shift >=3D 11 && a !=3D 0xC3E0000000000000ull) { + /* We need to massage the resulting exceptions. */ + if (exc & float_flag_invalid_cvti) { + /* Overflow, either normal or infinity. */ + if (float64_is_infinity(fa)) { + exc =3D FPCR_INV; + } else { exc =3D FPCR_IOV | FPCR_INE; } - } else { - uint64_t round; - - /* In this case the number is smaller than the fraction as - represented by the 52 bit number. Here we must think - about rounding the result. Handle this by shifting the - fractional part of the number into the high bits of ROUND. - This will let us efficiently handle round-to-nearest. */ - shift =3D -shift; - if (shift < 63) { - ret =3D frac >> shift; - round =3D frac << (64 - shift); - } else { - /* The exponent is so small we shift out everything. - Leave a sticky bit for proper rounding below. */ - do_underflow: - round =3D 1; - } - - if (round) { - exc =3D FPCR_INE; - switch (roundmode) { - case float_round_nearest_even: - if (round =3D=3D (1ull << 63)) { - /* Fraction is exactly 0.5; round to even. */ - ret +=3D (ret & 1); - } else if (round > (1ull << 63)) { - ret +=3D 1; - } - break; - case float_round_to_zero: - break; - case float_round_up: - ret +=3D 1 - sign; - break; - case float_round_down: - ret +=3D sign; - break; - } - } - } - if (sign) { - ret =3D -ret; + } else if (exc & float_flag_invalid) { + exc =3D FPCR_INV; + } else if (exc & float_flag_inexact) { + exc =3D FPCR_INE; } } env->error_code =3D exc; --=20 2.34.1