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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1688005065058100001 Content-Type: text/plain; charset="utf-8" Set the TIR default value with the SMT thread index, and place some standard limits on SMT configurations. Now powernv is able to boot skiboot and Linux with a SMT topology, including booting a KVM guest. There are several other per-core SPRs, but they are not so important to run OPAL/Linux. Some important per-LPAR ones to convert before powernv could run in 1LPAR mode. Broadcast msgsnd is not yet implemented either, but skiboot/Linux does not use that. KVM uses an implementation-specific detail of POWER9/10 TLBs where TLBIEL invalidates translations of all threads on a core, but that is not required here because KVM does not cache translations across PID or LPID switch. Most of these I have or aren't too hard to implement, but I start with a small bare bones for comments. Not-yet-Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 12 ++++++++++++ hw/ppc/pnv_core.c | 13 +++++-------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fc083173f3..f599ccad1d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -887,6 +887,18 @@ static void pnv_init(MachineState *machine) =20 pnv->num_chips =3D machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads= ); + + if (machine->smp.threads > 8) { + error_report("Cannot support more than 8 threads/core " + "on a powernv machine"); + exit(1); + } + if (!is_power_of_2(machine->smp.threads)) { + error_report("Cannot support %d threads/core on a powernv" + "machine because it must be a power of 2", + machine->smp.threads); + exit(1); + } /* * TODO: should we decide on how many chips we can create based * on #cores and Venice vs. Murano vs. Naples chip type etc..., diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 0bc3ad41c8..acd83caee8 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -167,12 +167,13 @@ static const MemoryRegionOps pnv_core_power9_xscom_op= s =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **err= p) +static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **err= p, + int thread_index) { CPUPPCState *env =3D &cpu->env; int core_pir; - int thread_index =3D 0; /* TODO: TCG supports only one thread */ ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; + ppc_spr_t *tir =3D &env->spr_cb[SPR_TIR]; Error *local_err =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(pc->chip); =20 @@ -188,11 +189,7 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCC= PU *cpu, Error **errp) =20 core_pir =3D object_property_get_uint(OBJECT(pc), "pir", &error_abort); =20 - /* - * The PIR of a thread is the core PIR + the thread index. We will - * need to find a way to get the thread index when TCG supports - * more than 1. We could use the object name ? - */ + tir->default_value =3D thread_index; pir->default_value =3D core_pir + thread_index; =20 /* Set time-base frequency to 512 MHz */ @@ -241,7 +238,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) } =20 for (j =3D 0; j < cc->nr_threads; j++) { - pnv_core_cpu_realize(pc, pc->threads[j], &local_err); + pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j); if (local_err) { goto err; } --=20 2.40.1