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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687634877273100003 The 'kvm_sw_tlb' and 'tlb_dirty' fields introduced in commit 93dd5e852c ("kvm: ppc: booke206: use MMU API") are specific to KVM and shouldn't be accessed when it is not available. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Nicholas Piggin --- Since v1 https://lore.kernel.org/qemu-devel/20230405160454.97436-9-philmd@l= inaro.org/: - Restrict tlb_dirty field (C=C3=A9dric, thus drop Daniel's R-b). --- target/ppc/cpu.h | 2 ++ hw/ppc/e500.c | 2 ++ hw/ppc/ppce500_spin.c | 2 ++ target/ppc/mmu_common.c | 4 ++++ 4 files changed, 10 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0ee2adc105..60b15bfbe7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1147,8 +1147,10 @@ struct CPUArchState { int nb_pids; /* Number of available PID registers */ int tlb_type; /* Type of TLB we're dealing with */ ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ +#ifdef CONFIG_KVM bool tlb_dirty; /* Set to non-zero when modifying TLB */ bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ +#endif /* CONFIG_KVM */ uint32_t tlb_need_flush; /* Delayed flush needed */ #define TLB_NEED_LOCAL_FLUSH 0x1 #define TLB_NEED_GLOBAL_FLUSH 0x2 diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b6eb599751..67793a86f1 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -765,7 +765,9 @@ static void mmubooke_create_initial_mapping(CPUPPCState= *env) tlb->mas7_3 =3D 0; tlb->mas7_3 |=3D MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS= 3_SX; =20 +#ifdef CONFIG_KVM env->tlb_dirty =3D true; +#endif } =20 static void ppce500_cpu_reset_sec(void *opaque) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index d57b199797..bbce63e8a4 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -83,7 +83,9 @@ static void mmubooke_create_initial_mapping(CPUPPCState *= env, tlb->mas2 =3D (va & TARGET_PAGE_MASK) | MAS2_M; tlb->mas7_3 =3D pa & TARGET_PAGE_MASK; tlb->mas7_3 |=3D MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS= 3_SX; +#ifdef CONFIG_KVM env->tlb_dirty =3D true; +#endif } =20 static void spin_kick(CPUState *cs, run_on_cpu_data data) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index ae1db6e348..8c000e250d 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -930,10 +930,12 @@ static void mmubooke_dump_mmu(CPUPPCState *env) ppcemb_tlb_t *entry; int i; =20 +#ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { qemu_printf("Cannot access KVM TLB\n"); return; } +#endif =20 qemu_printf("\nTLB:\n"); qemu_printf("Effective Physical Size PID Prot = " @@ -1021,10 +1023,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env) int offset =3D 0; int i; =20 +#ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { qemu_printf("Cannot access KVM TLB\n"); return; } +#endif =20 for (i =3D 0; i < BOOKE206_MAX_TLBN; i++) { int size =3D booke206_tlb_size(env, i); --=20 2.38.1