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([91.223.100.38]) by smtp.gmail.com with ESMTPSA id v3-20020a2e9f43000000b002b47fc5219dsm1320276ljk.67.2023.06.22.08.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 08:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687446729; x=1690038729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0TccvH+qpCGtNsDlIDGjbT6JxihYcWpoZghsjPC3N3M=; b=K/GQfdbnhevSVCFKwc9gSTJ14WkcvQbsUzsoUKbwohkXnuJBABCceoGjiqXgd2+0M9 ghL5RP566+mUry9jKXs767YiqAUTn1NZCGryPR9HElEh5CgTbk+O8R7oiENoCE+qZaPc HGQQ6rT8uxEbtEHXdEyEsXD15lc6CfP6xFuyv3ZopAjywxnmo6dq/LptGEEcBH7Hwqh9 t1nROplahVet7hGhg2Mc+tJYoN3OJCmbSf/kb/khr7sqcbRAIKJIOsLjXB3MXuGjpuox G1ER+1AlsL0gs6upmI2/5OWJ3q+JzHByd8J1mpSFI/JIShFyW0cC+Z5z3gHeIXLH1WBc hAgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687446729; x=1690038729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0TccvH+qpCGtNsDlIDGjbT6JxihYcWpoZghsjPC3N3M=; b=EuvaKDTRF3aEz2gpgkHc3lXV0a82bPcTwJ6KZ/MRre7BukswHZa/pbknF9yzItFAPP /tu2cc5Tr0NtWzsR3ZN1jJjE5MCnLVZ1sdcGPoCsJP9sZVv0oZhTGOe2oS8eZLQZQUz3 EcvUPIy0GvMKXVrNHkrsoB2OxOQJMS5W6/Ncxj+Pz+gTRgmnnglaYV83+GuUXZLIOIu0 8gelvvCB9TbxcWeA+7LlV4MbctudYXE73cAcWAtjMVe2hoYQu2UHZulLFwjWj54OI/kp ZqYMH+IeCRwBGfnZj7o+xtzHoBPss0kuObKkQlJe1RxXab0RtyfxQKsldyb1kaDsJfDu xNew== X-Gm-Message-State: AC+VfDzqD9RJyiRV9xtHsjcfJSPr0kHux12SyO+ZI9Tp2k5QtLJ4mUBG BhSo63/rWPi8YJn39SkTtpqtvCVMgcxLUPl+tdTnegKW X-Google-Smtp-Source: ACHHUZ6cY91N81B0HBDL6OVMcQ1WWGoC0Logz0hwQ3wx6qaerxNS78YptZOEoWatB8dYuYHPbo1tLQ== X-Received: by 2002:a2e:8241:0:b0:2b5:84fb:5939 with SMTP id j1-20020a2e8241000000b002b584fb5939mr3641223ljh.30.1687446729573; Thu, 22 Jun 2023 08:12:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 3/4] target/arm: Support reading ZA[] from gdbstub Date: Thu, 22 Jun 2023 17:12:00 +0200 Message-Id: <20230622151201.1578522-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622151201.1578522-1-richard.henderson@linaro.org> References: <20230622151201.1578522-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687446796704100001 Content-Type: text/plain; charset="utf-8" Mirror the existing support for SVE. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 8 ++++ target/arm/gdbstub64.c | 88 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index af0119addf..082617cfc6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -877,6 +877,7 @@ struct ArchCPU { =20 DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; + DynamicGDBXMLInfo dyn_zareg_xml; DynamicGDBXMLInfo dyn_m_systemreg_xml; DynamicGDBXMLInfo dyn_m_secextreg_xml; =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index e3029bdc37..54d1f28992 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1362,12 +1362,15 @@ static inline uint64_t pmu_counter_mask(CPUARMState= *env) =20 #ifdef TARGET_AARCH64 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); +int arm_gen_dynamic_zareg_xml(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_za_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_za_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 03b17c814f..1204eb40d7 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -490,6 +490,8 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const= char *xmlname) return cpu->dyn_sysreg_xml.desc; } else if (strcmp(xmlname, "sve-registers.xml") =3D=3D 0) { return cpu->dyn_svereg_xml.desc; + } else if (strcmp(xmlname, "za-registers.xml") =3D=3D 0) { + return cpu->dyn_zareg_xml.desc; } else if (strcmp(xmlname, "arm-m-system.xml") =3D=3D 0) { return cpu->dyn_m_systemreg_xml.desc; #ifndef CONFIG_USER_ONLY @@ -532,6 +534,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) aarch64_gdb_set_pauth_reg, 4, "aarch64-pauth.xml", 0); } + if (cpu_isar_feature(aa64_sme, cpu)) { + int nreg =3D arm_gen_dynamic_zareg_xml(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_za_reg, + aarch64_gdb_set_za_reg, nreg, + "za-registers.xml", 0); + } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589..b76fac9bd0 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -247,6 +247,61 @@ int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_= t *buf, int reg) return 0; } =20 +static int max_svq(ARMCPU *cpu) +{ + return 32 - clz32(cpu->sme_vq.map); +} + +int aarch64_gdb_get_za_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + int max_vq =3D max_svq(cpu); + int cur_vq =3D EX_TBFLAG_A64(env->hflags, SVL) + 1; + int i; + + if (reg >=3D max_vq * 16) { + return 0; + } + + /* If ZA is unset, or reg out of range, the contents are zero. */ + if (FIELD_EX64(env->svcr, SVCR, ZA) && reg < cur_vq * 16) { + for (i =3D 0; i < cur_vq; i++) { + gdb_get_reg128(buf, env->zarray[reg].d[i * 2 + 1], + env->zarray[reg].d[i * 2]); + } + } else { + cur_vq =3D 0; + } + + for (i =3D cur_vq; i < max_vq; i++) { + gdb_get_reg128(buf, 0, 0); + } + + return max_vq * 16; +} + +int aarch64_gdb_set_za_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint64_t *p =3D (uint64_t *) buf; + int max_vq =3D max_svq(cpu); + int cur_vq =3D EX_TBFLAG_A64(env->hflags, SVL) + 1; + int i; + + if (reg >=3D max_vq * 16) { + return 0; + } + + /* If ZA is unset, or reg out of range, the contents are zero. */ + if (FIELD_EX64(env->svcr, SVCR, ZA) && reg < cur_vq * 16) { + for (i =3D 0; i < cur_vq; i++) { + env->zarray[reg].d[i * 2 + 1] =3D *p++; + env->zarray[reg].d[i * 2 + 0] =3D *p++; + } + } + return max_vq * 16; +} + static void output_vector_union_type(GString *s, int reg_width, const char *name) { @@ -379,3 +434,36 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_= base_reg) info->num =3D base_reg - orig_base_reg; return info->num; } + +/* + * Generate the xml for SME, with matrix size set to the maximum + * for the cpu. Returns the number of registers generated. + */ +int arm_gen_dynamic_zareg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GString *s =3D g_string_new(NULL); + int vq =3D max_svq(cpu); + int row_count =3D vq * 16; + int row_width =3D vq * 128; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, "= "); + g_string_append_printf(s, ""); + + output_vector_union_type(s, row_width, "zav"); + + for (i =3D 0; i < row_count; i++) { + g_string_append_printf(s, + "", + i, row_width, base_reg + i); + } + + g_string_append_printf(s, ""); + + cpu->dyn_zareg_xml.num =3D row_count; + cpu->dyn_zareg_xml.desc =3D g_string_free(s, false); + return row_count; +} --=20 2.34.1