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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id w6-20020a4aa446000000b00562f06fb5easm156677ool.11.2023.06.22.06.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 06:57:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1687442240; x=1690034240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SJQQ1L+QIqrO+QRyOETHpH3YJ7iCv70aVq9b92NcYKA=; b=RFzxdymEMmmPWTvtkZ3AcIwX5a72RTFh1SQlGMU74y+2mURfsj7vkWz8FeMk0126GG cFnT9BKoXRF7/nCzL4QhFg6/lxVqGgshFDvk0q8EXwl8poJAdi7QL4+HHv6nVOZJYevN w8GOB3QFODus2hiSNNhsl/xOdiRf79fWqBOD173OBSg6Qk/TFNDqp9QMhByJZnMT8puK XjEQe89Ba4iqQGVi7ToMQG+S9CWefgTIYadbCdCcb0ej6EwRfFQvDgcOnYkXwH/Mx5f4 gy4RmYMzsloIYBl4Tjq8+rmHrJJFfLr4i90ghTYPZ9/iCQivgSYDDvpmWHzLePQKh77i r23Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687442240; x=1690034240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SJQQ1L+QIqrO+QRyOETHpH3YJ7iCv70aVq9b92NcYKA=; b=Vyvg2zm/TSgzysJI1KPRRq3ex4qozsfFZJIyKw81qCG9g4r3eN805mKY1yRhtZLleM Ysb3tbPu4exM9tMYBEaZTcPcmYgtS/kPr0KH2xEfEdy0pij+P5TNXQhhClgYbmS90zWy jKnDj2aLolvLD3JQ4N5YLiT5/ERH8u+F6Hahnw6/p+ty9ngiSf2vxg7Sx6txq/yCwWSz bQnB8pwPsmOoIYwpAojHS4bgNWSnzfFXbU2CP1PyP0zEF0KeanbikQmdrUgpVYh6uvsq HiKtEz/bNuRI/8JNcy7ZOgvDwZcap2xla1nV97fsg6e1ItfmMLRCNoHktPq9s7ykTiGw QiBg== X-Gm-Message-State: AC+VfDwIwaJMQAwIoQudWaG8SOH3MtOGfmF6r8hgcyeqZhWGPO0Vnanc iFS0QrlGPj/pyAQt2E/x+2lwp9kn1gRv0nKAyeI= X-Google-Smtp-Source: ACHHUZ78cYbG4xlpuVp+0px2rpZtBHq6FI/1I99uKRL+C5J2l0x5KYyR01kTuN79319lgde4tnE7aQ== X-Received: by 2002:a05:6871:347:b0:19e:b8e0:1434 with SMTP id c7-20020a056871034700b0019eb8e01434mr8793422oag.8.1687442240322; Thu, 22 Jun 2023 06:57:20 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 04/19] target/riscv/cpu.c: restrict 'mimpid' value Date: Thu, 22 Jun 2023 10:56:45 -0300 Message-ID: <20230622135700.105383-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230622135700.105383-1-dbarboza@ventanamicro.com> References: <20230622135700.105383-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1687442482654100001 Content-Type: text/plain; charset="utf-8" Following the same logic used with 'mvendorid' let's also restrict 'mimpid' for named CPUs. Generic CPUs keep setting the value freely. Note that we're getting rid of the default RISCV_CPU_MARCHID value. The reason is that this is not a good default since it's dynamic, changing with with every QEMU version, regardless of whether the actual implementation of the CPU changed from one QEMU version to the other. Named CPU should set it to a meaningful value instead and generic CPUs can set whatever they want. This is the error thrown for an invalid 'mimpid' value for the veyron-v1 CPU: $ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=3D2 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=3D2: Unable to change veyron-v1-riscv-cpu mimpid (0x111) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b65958a887..33cc28acf1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,7 +42,6 @@ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ (QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MICRO)) -#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID =20 static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 @@ -1739,7 +1738,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -1858,6 +1856,35 @@ static void cpu_get_mvendorid(Object *obj, Visitor *= v, const char *name, visit_type_bool(v, name, &value, errp); } =20 +static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mimpid (0x%lx)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid =3D value; +} + +static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mimpid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -1892,6 +1919,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); =20 + object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, + cpu_set_mimpid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.41.0