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[193.116.203.37]) by smtp.gmail.com with ESMTPSA id x3-20020a1709027c0300b001ac2c3e54adsm4925662pll.118.2023.06.22.02.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 02:34:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687426456; x=1690018456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IJQeOCVTk4IYZUoWEWRQMehatOO+sQzn5G0/NFJ9jWQ=; b=gvzmWDnUt5FpVHiGh/YY4/xI/qL1lDzDQkdnt3Jan8BoGA2VfQB6brd3pRyoPtbJdy Hzhnn4kcD6PO3b4VGdwXlkfT51zf2qCLiTKY92YvdkDyo1uIT6dPy1oX08obMRUrJw79 LEb4LAUut144bZVV+cJNTb9AAQ0oo/virS1pEwRDNj9Rh0V+YOcTx7S37wlv4W8Dp/rl fH0hjDEE20Gxz+gqBm2iUyKsKUHqqhlb1z+RYfL6FzDIBVs7BWNomB4SDM4EAOHC/r5s 4ELiQB9duLBja9u/1ST4cIWNcJ96krSSsBDQYlhxpUJ4FrsWs7iXg36PdxD+pkSRXuSY 7SLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687426456; x=1690018456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJQeOCVTk4IYZUoWEWRQMehatOO+sQzn5G0/NFJ9jWQ=; b=hi76w8YMbT6vUVCDLvRTt2oh2M6zSRwnp+mLWXD0iF4tbK79ubHspmiYQa+xuFTp/Z nbUqftRWrac3yeh3PXE6ucbZ2XT8D/1GAxxu4o+1xjaztq6OPo1VdxHZ8QSDr5sJo+KI 6S/FmDyPvEYT+gXpj8GdFkyFkzgkBbkd0JhCH8j5HHcI0bR1Fgw/XjC/NdkA24jSrQtd N0crGhUwwS1NM+8DU1LqU+i3LW6g5lAj5sUySscU3zEza3HvWFM81dL92Z8LeLKO4yX8 k61IHBAbxJGZZN+Vt+KWlqraXF7DyQDrQz4Yvi3kOlvIor9APVgJZdy863dYvSbO6A0/ crFQ== X-Gm-Message-State: AC+VfDw5GzTE5Pd//JRnQnHefheiu1Tcj+ODbgnjb6/evGAgPs/OrZU3 q+aEeRxza482hzH+xlyukEYS5G3N1oM= X-Google-Smtp-Source: ACHHUZ5OvyE6D7Rmq/6sKGERS11n+uxp0bDn/UKuJXmnOx5U4QAXwnMGgAbNQGBLIyDu471Zd0snQA== X-Received: by 2002:a17:902:6b44:b0:1b5:3500:9e22 with SMTP id g4-20020a1709026b4400b001b535009e22mr16457820plt.63.1687426455951; Thu, 22 Jun 2023 02:34:15 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Harsh Prateek Bora , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/7] target/ppc: Add support for SMT CTRL register Date: Thu, 22 Jun 2023 19:33:52 +1000 Message-Id: <20230622093357.255649-3-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230622093357.255649-1-npiggin@gmail.com> References: <20230622093357.255649-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1687426573883100001 Content-Type: text/plain; charset="utf-8" A relatively simple case to begin with, CTRL is a SMT shared register where reads and writes need to synchronise against state changes by other threads in the core. Atomic serialisation operations are used to achieve this. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/helper.h | 2 ++ target/ppc/misc_helper.c | 25 +++++++++++++++++++++++++ target/ppc/translate.c | 18 +++++++++++++++++- 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 38efbc351c..fda40b8a60 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -704,6 +704,8 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl) =20 DEF_HELPER_2(load_dump_spr, void, env, i32) DEF_HELPER_2(store_dump_spr, void, env, i32) +DEF_HELPER_3(spr_write_CTRL, void, env, i32, tl) + DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32) DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32) DEF_HELPER_FLAGS_1(load_tbl, TCG_CALL_NO_RWG, tl, env) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 40ddc5c08c..a058eb24cd 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -43,6 +43,31 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sp= rn) env->spr[sprn]); } =20 +void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn, + target_ulong val) +{ + CPUState *cs =3D env_cpu(env); + CPUState *ccs; + uint32_t run =3D val & 1; + uint32_t ts, ts_mask; + + assert(sprn =3D=3D SPR_CTRL); + + env->spr[sprn] &=3D ~1U; + env->spr[sprn] |=3D run; + + ts_mask =3D ~(1U << (8 + env->spr[SPR_TIR])); + ts =3D run << (8 + env->spr[SPR_TIR]); + + THREAD_SIBLING_FOREACH(cs, ccs) { + CPUPPCState *cenv =3D &POWERPC_CPU(ccs)->env; + + cenv->spr[sprn] &=3D ts_mask; + cenv->spr[sprn] |=3D ts; + } +} + + #ifdef TARGET_PPC64 static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, const char *caller, uint32_t cause, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5d585393c5..41a8b800bd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -438,7 +438,7 @@ void spr_write_generic32(DisasContext *ctx, int sprn, i= nt gprn) #endif } =20 -void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) { /* This does not implement >1 thread */ TCGv t0 =3D tcg_temp_new(); @@ -447,6 +447,22 @@ void spr_write_CTRL(DisasContext *ctx, int sprn, int g= prn) tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ tcg_gen_or_tl(t1, t1, t0); gen_store_spr(sprn, t1); +} + +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +{ + if (!(ctx->flags & POWERPC_FLAG_SMT)) { + spr_write_CTRL_ST(ctx, sprn, gprn); + goto out; + } + + if (!gen_serialize(ctx)) { + return; + } + + gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), + cpu_gpr[gprn]); +out: spr_store_dump_spr(sprn); =20 /* --=20 2.40.1