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Tue, 20 Jun 2023 04:08:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: berrange@redhat.com, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 36/37] host/include/aarch64: Implement aes-round.h Date: Tue, 20 Jun 2023 13:07:57 +0200 Message-Id: <20230620110758.787479-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620110758.787479-1-richard.henderson@linaro.org> References: <20230620110758.787479-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687259833174100001 Content-Type: text/plain; charset="utf-8" Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson --- meson.build | 9 + host/include/aarch64/host/cpuinfo.h | 1 + host/include/aarch64/host/crypto/aes-round.h | 205 +++++++++++++++++++ util/cpuinfo-aarch64.c | 2 + 4 files changed, 217 insertions(+) create mode 100644 host/include/aarch64/host/crypto/aes-round.h diff --git a/meson.build b/meson.build index 6ef78ea278..a1e5f3c06d 100644 --- a/meson.build +++ b/meson.build @@ -2667,6 +2667,15 @@ config_host_data.set('CONFIG_AVX512BW_OPT', get_opti= on('avx512bw') \ int main(int argc, char *argv[]) { return bar(argv[0]); } '''), error_message: 'AVX512BW not available').allowed()) =20 +# For both AArch64 and AArch32, detect if builtins are available. +config_host_data.set('CONFIG_ARM_AES_BUILTIN', cc.compiles(''' + #include + #ifndef __ARM_FEATURE_AES + __attribute__((target("+crypto"))) + #endif + void foo(uint8x16_t *p) { *p =3D vaesmcq_u8(*p); } + ''')) + have_pvrdma =3D get_option('pvrdma') \ .require(rdma.found(), error_message: 'PVRDMA requires OpenFabrics libra= ries') \ .require(cc.compiles(gnu_source_prefix + ''' diff --git a/host/include/aarch64/host/cpuinfo.h b/host/include/aarch64/hos= t/cpuinfo.h index 82227890b4..05feeb4f43 100644 --- a/host/include/aarch64/host/cpuinfo.h +++ b/host/include/aarch64/host/cpuinfo.h @@ -9,6 +9,7 @@ #define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ #define CPUINFO_LSE (1u << 1) #define CPUINFO_LSE2 (1u << 2) +#define CPUINFO_AES (1u << 3) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/host/include/aarch64/host/crypto/aes-round.h b/host/include/aa= rch64/host/crypto/aes-round.h new file mode 100644 index 0000000000..8b5f88d50c --- /dev/null +++ b/host/include/aarch64/host/crypto/aes-round.h @@ -0,0 +1,205 @@ +/* + * AArch64 specific aes acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef AARCH64_HOST_CRYPTO_AES_ROUND_H +#define AARCH64_HOST_CRYPTO_AES_ROUND_H + +#include "host/cpuinfo.h" +#include + +#ifdef __ARM_FEATURE_AES +# define HAVE_AES_ACCEL true +#else +# define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_AES) +#endif +#if !defined(__ARM_FEATURE_AES) && defined(CONFIG_ARM_AES_BUILTIN) +# define ATTR_AES_ACCEL __attribute__((target("+crypto"))) +#else +# define ATTR_AES_ACCEL +#endif + +static inline uint8x16_t aes_accel_bswap(uint8x16_t x) +{ + return vqtbl1q_u8(x, (uint8x16_t){ 15, 14, 13, 12, 11, 10, 9, 8, + 7, 6, 5, 4, 3, 2, 1, 0, }); +} + +#ifdef CONFIG_ARM_AES_BUILTIN +# define aes_accel_aesd vaesdq_u8 +# define aes_accel_aese vaeseq_u8 +# define aes_accel_aesmc vaesmcq_u8 +# define aes_accel_aesimc vaesimcq_u8 +# define aes_accel_aesd_imc(S, K) vaesimcq_u8(vaesdq_u8(S, K)) +# define aes_accel_aese_mc(S, K) vaesmcq_u8(vaeseq_u8(S, K)) +#else +static inline uint8x16_t aes_accel_aesd(uint8x16_t d, uint8x16_t k) +{ + asm(".arch_extension aes\n\t" + "aesd %0.16b, %1.16b" : "+w"(d) : "w"(k)); + return d; +} + +static inline uint8x16_t aes_accel_aese(uint8x16_t d, uint8x16_t k) +{ + asm(".arch_extension aes\n\t" + "aese %0.16b, %1.16b" : "+w"(d) : "w"(k)); + return d; +} + +static inline uint8x16_t aes_accel_aesmc(uint8x16_t d) +{ + asm(".arch_extension aes\n\t" + "aesmc %0.16b, %1.16b" : "=3Dw"(d) : "w"(d)); + return d; +} + +static inline uint8x16_t aes_accel_aesimc(uint8x16_t d) +{ + asm(".arch_extension aes\n\t" + "aesimc %0.16b, %1.16b" : "=3Dw"(d) : "w"(d)); + return d; +} + +/* Most CPUs fuse AESD+AESIMC in the execution pipeline. */ +static inline uint8x16_t aes_accel_aesd_imc(uint8x16_t d, uint8x16_t k) +{ + asm(".arch_extension aes\n\t" + "aesd %0.16b, %1.16b\n\t" + "aesimc %0.16b, %0.16b" : "+w"(d) : "w"(k)); + return d; +} + +/* Most CPUs fuse AESE+AESMC in the execution pipeline. */ +static inline uint8x16_t aes_accel_aese_mc(uint8x16_t d, uint8x16_t k) +{ + asm(".arch_extension aes\n\t" + "aese %0.16b, %1.16b\n\t" + "aesmc %0.16b, %0.16b" : "+w"(d) : "w"(k)); + return d; +} +#endif /* CONFIG_ARM_AES_BUILTIN */ + +static inline void ATTR_AES_ACCEL +aesenc_MC_accel(AESState *ret, const AESState *st, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aesmc(t); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesmc(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aese(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aese(t, z); + } + ret->v =3D (AESStateVec)t ^ rk->v; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aese_mc(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aese_mc(t, z); + } + ret->v =3D (AESStateVec)t ^ rk->v; +} + +static inline void ATTR_AES_ACCEL +aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aesimc(t); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesimc(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aesd(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesd(t, z); + } + ret->v =3D (AESStateVec)t ^ rk->v; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_AK_IMC_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t k =3D (uint8x16_t)rk->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D aes_accel_aesd(t, z); + t ^=3D k; + t =3D aes_accel_aesimc(t); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesd(t, z); + t ^=3D k; + t =3D aes_accel_aesimc(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_IMC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aesd_imc(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesd_imc(t, z); + } + ret->v =3D (AESStateVec)t ^ rk->v; +} + +#endif /* AARCH64_HOST_CRYPTO_AES_ROUND_H */ diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c index f99acb7884..ababc39550 100644 --- a/util/cpuinfo-aarch64.c +++ b/util/cpuinfo-aarch64.c @@ -56,10 +56,12 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); info |=3D (hwcap & HWCAP_ATOMICS ? CPUINFO_LSE : 0); info |=3D (hwcap & HWCAP_USCAT ? CPUINFO_LSE2 : 0); + info |=3D (hwcap & HWCAP_AES ? CPUINFO_AES: 0); #endif #ifdef CONFIG_DARWIN info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE") * CPUINFO_LSE; info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE2") * CPUINFO_LSE2; + info |=3D sysctl_for_bool("hw.optional.arm.FEAT_AES") * CPUINFO_AES; #endif =20 cpuinfo =3D info; --=20 2.34.1