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Tue, 20 Jun 2023 04:08:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: berrange@redhat.com, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 35/37] host/include/i386: Implement aes-round.h Date: Tue, 20 Jun 2023 13:07:56 +0200 Message-Id: <20230620110758.787479-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620110758.787479-1-richard.henderson@linaro.org> References: <20230620110758.787479-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687259622802100002 Content-Type: text/plain; charset="utf-8" Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson --- host/include/i386/host/cpuinfo.h | 1 + host/include/i386/host/crypto/aes-round.h | 152 ++++++++++++++++++++ host/include/x86_64/host/crypto/aes-round.h | 1 + util/cpuinfo-i386.c | 3 + 4 files changed, 157 insertions(+) create mode 100644 host/include/i386/host/crypto/aes-round.h create mode 100644 host/include/x86_64/host/crypto/aes-round.h diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpui= nfo.h index a6537123cf..073d0a426f 100644 --- a/host/include/i386/host/cpuinfo.h +++ b/host/include/i386/host/cpuinfo.h @@ -26,6 +26,7 @@ #define CPUINFO_AVX512VBMI2 (1u << 15) #define CPUINFO_ATOMIC_VMOVDQA (1u << 16) #define CPUINFO_ATOMIC_VMOVDQU (1u << 17) +#define CPUINFO_AES (1u << 18) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/host/include/i386/host/crypto/aes-round.h b/host/include/i386/= host/crypto/aes-round.h new file mode 100644 index 0000000000..59a64130f7 --- /dev/null +++ b/host/include/i386/host/crypto/aes-round.h @@ -0,0 +1,152 @@ +/* + * x86 specific aes acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef X86_HOST_CRYPTO_AES_ROUND_H +#define X86_HOST_CRYPTO_AES_ROUND_H + +#include "host/cpuinfo.h" +#include + +#if defined(__AES__) && defined(__SSSE3__) +# define HAVE_AES_ACCEL true +# define ATTR_AES_ACCEL +#else +# define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_AES) +# define ATTR_AES_ACCEL __attribute__((target("aes,ssse3"))) +#endif + +static inline __m128i ATTR_AES_ACCEL +aes_accel_bswap(__m128i x) +{ + return _mm_shuffle_epi8(x, _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15)); +} + +static inline void ATTR_AES_ACCEL +aesenc_MC_accel(AESState *ret, const AESState *st, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i z =3D _mm_setzero_si128(); + + if (be) { + t =3D aes_accel_bswap(t); + t =3D _mm_aesdeclast_si128(t, z); + t =3D _mm_aesenc_si128(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdeclast_si128(t, z); + t =3D _mm_aesenc_si128(t, z); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesenclast_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesenclast_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesenc_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesenc_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) +{ + __m128i t =3D (__m128i)st->v; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D _mm_aesimc_si128(t); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesimc_si128(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesdeclast_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdeclast_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_AK_IMC_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesdeclast_si128(t, k); + t =3D _mm_aesimc_si128(t); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdeclast_si128(t, k); + t =3D _mm_aesimc_si128(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_IMC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesdec_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdec_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +#endif /* X86_HOST_CRYPTO_AES_ROUND_H */ diff --git a/host/include/x86_64/host/crypto/aes-round.h b/host/include/x86= _64/host/crypto/aes-round.h new file mode 100644 index 0000000000..2773cc9f10 --- /dev/null +++ b/host/include/x86_64/host/crypto/aes-round.h @@ -0,0 +1 @@ +#include "host/include/i386/host/crypto/aes-round.h" diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index ab6143d9e7..3a7b7e0ad1 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -40,6 +40,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) info |=3D (c & bit_MOVBE ? CPUINFO_MOVBE : 0); info |=3D (c & bit_POPCNT ? CPUINFO_POPCNT : 0); =20 + /* Our AES support requires PSHUFB as well. */ + info |=3D ((c & bit_AES) && (c & bit_SSSE3) ? CPUINFO_AES : 0); + /* For AVX features, we must check available and usable. */ if ((c & bit_AVX) && (c & bit_OSXSAVE)) { unsigned bv =3D xgetbv_low(0); --=20 2.34.1