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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wZtVgFV8GkDyXO4vsdUA6xljaLuLuyspVB+wnGanNt0=; b=n/L6FsN+ZHSU9rnRM8ff7hdiQkWfAKj88SEo3GaadMf+ckOHTAmc83lrZIgVb7Rml9 6EiEm7IqPYGrSHGv1+QJh3WyBwn3hu1JGadrTXkyDodo3N4/wSIPnxLkNK3ehufEtVYD keeKPjcFyEcWRogKpRtAi/WPA8NfGgSwYjcVuWG2GLcFtQWwLwAwZY4zFN2PWNEsx7ws F6Cx63m7FHFM2se3Gba9i5gV8SiJxXElZs99iZwxOjciao/REUn5awOdTyMzHgo8joTw sS/mB6PmAIwYS7rk9dR6sCaUdtPJOUbZ69XDA/dzFJ2KT+sOmsU4cEurN6iU4PrH4QWr cTgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wZtVgFV8GkDyXO4vsdUA6xljaLuLuyspVB+wnGanNt0=; b=AySdWtwxWqwdBWmfeQsjw4XPsA4KBj8Sdwa6aYYvKjq4pZApIHxqwNLtWaMYx91DGz yX/Q42qW432vtbIzKM9AHCNg47r95BSjGrS9a4+n4GQQxkJpliizELGJ+puRiJDxvwUH D5KlN5+fAQQ75sVEcUwCYE56iBAdpH2AAji3JEYqc1EfXFvEayQFP1XD+GpH4XO8sV0R rFLARoxz8XP5z3Zjl7mOqZgHT3SS09m8z01t5XYNu4SYg5LNQ81zXimgTX3xKUs5+/4u Or1vGx1cdv/VeMUeRk0yUWjE4UxCp5P6ac1fy1EbxDz2U/xi0dNJkxOnEkYnuq68/quh c7qA== X-Gm-Message-State: AC+VfDwywyX+2O97S9FIstiAB/vaS9+Ln2ufAwCFtp5osxXgCYPxfmuy LHpB8F6igi2IQE0+GCghyWNehOnt9yPRDkzybyE= X-Google-Smtp-Source: ACHHUZ6b1AMWFFT4LEt9OB6TlYnb48odo2nCazGXr7H2+f7ioRcq22V6FRU+IIKmc0+VhbeikZb99g== X-Received: by 2002:a7b:c38f:0:b0:3f8:ff4e:8ba3 with SMTP id s15-20020a7bc38f000000b003f8ff4e8ba3mr6719190wmj.38.1687184964723; Mon, 19 Jun 2023 07:29:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/33] target/arm: Convert load (pointer auth) insns to decodetree Date: Mon, 19 Jun 2023 15:29:00 +0100 Message-Id: <20230619142914.963184-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185019379100001 Convert the instructions in the load/store register (pointer authentication) group ot decodetree: LDRAA, LDRAB. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 83 +++++++--------------------------- 2 files changed, 23 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 799c5ecb77a..b80a17111e7 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -457,3 +457,10 @@ LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... = ..... @atomic SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic =20 LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 + +# Load/store register (pointer authentication) + +# LDRA immediate is 10 bits signed and scaled, but the bits aren't all con= tiguous +%ldra_imm 22:s1 12:9 !function=3Dtimes_2 + +LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=3D%ldra_= imm diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6dc8151c407..2bffb14e84e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3324,43 +3324,23 @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR = *a) return true; } =20 -/* - * PAC memory operations - * - * 31 30 27 26 24 22 21 12 11 10 5 0 - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * - * Rt: the result register - * Rn: base address or SP - * V: vector flag (always 0 as of v8.3) - * M: clear for key DA, set for key DB - * W: pre-indexing flag - * S: sign for imm9. - */ -static void disas_ldst_pac(DisasContext *s, uint32_t insn, - int size, int rt, bool is_vector) +static bool trans_LDRA(DisasContext *s, arg_LDRA *a) { - int rn =3D extract32(insn, 5, 5); - bool is_wback =3D extract32(insn, 11, 1); - bool use_key_a =3D !extract32(insn, 23, 1); - int offset; TCGv_i64 clean_addr, dirty_addr, tcg_rt; MemOp memop; =20 - if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { - unallocated_encoding(s); - return; + /* Load with pointer authentication */ + if (!dc_isar_feature(aa64_pauth, s)) { + return false; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); =20 if (s->pauth_active) { - if (use_key_a) { + if (!a->m) { gen_helper_autda(dirty_addr, cpu_env, dirty_addr, tcg_constant_i64(0)); } else { @@ -3369,25 +3349,23 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, } } =20 - /* Form the 10-bit signed, scaled offset. */ - offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); - offset =3D sextract32(offset << size, 0, 10 + size); - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); =20 - memop =3D finalize_memop(s, size); + memop =3D finalize_memop(s, MO_64); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, - is_wback || rn !=3D 31, memop); + a->w || a->rn !=3D 31, memop); =20 - tcg_rt =3D cpu_reg(s, rt); + tcg_rt =3D cpu_reg(s, a->rt); do_gpr_ld(s, tcg_rt, clean_addr, memop, - /* extend */ false, /* iss_valid */ !is_wback, - /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); + /* extend */ false, /* iss_valid */ !a->w, + /* iss_srt */ a->rt, /* iss_sf */ true, /* iss_ar */ false); =20 - if (is_wback) { - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + if (a->w) { + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } + return true; } =20 /* @@ -3474,31 +3452,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, u= int32_t insn) } } =20 -/* Load/store register (all forms) */ -static void disas_ldst_reg(DisasContext *s, uint32_t insn) -{ - int rt =3D extract32(insn, 0, 5); - bool is_vector =3D extract32(insn, 26, 1); - int size =3D extract32(insn, 30, 2); - - switch (extract32(insn, 24, 2)) { - case 0: - if (extract32(insn, 21, 1) =3D=3D 0) { - break; - } - switch (extract32(insn, 10, 2)) { - case 0: - case 2: - break; - default: - disas_ldst_pac(s, insn, size, rt, is_vector); - return; - } - break; - } - unallocated_encoding(s); -} - /* AdvSIMD load/store multiple structures * * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 @@ -4016,10 +3969,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x38: case 0x39: - case 0x3c: case 0x3d: /* Load/store register (all forms) */ - disas_ldst_reg(s, insn); - break; case 0x0c: /* AdvSIMD load/store multiple structures */ disas_ldst_multiple_struct(s, insn); break; --=20 2.34.1