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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OBnS252vauoaeLoGy2Pd1180Qv2s4Y9APpSeQJOp5Ss=; b=djTPCGVVL9+oUy5e2UYNBOYJTTyY93JAuVRAD7y6e1yGu2dvGEzdHVXYarbk90byqc o91WNpOf041OSE8qnawccwYUTo+U303LeJbepy7xGszgrRbt9YuyYS5F0S6ce3jN9lgE 61kJDqEO/hmaMzjtuNOnastsWWSmKf01/ZBAD71ST5wPA7OeeXMFZ4t1GGVrKYRTyv8f 1o9Gi2KqUBBIBQOvzhJt78JQfh/M3E4imFLZiXfjjYzHirl3uHcSoOTmP7D0xTSR/iTI 6/P9V1VI1jrqiCl8vDjIzy1Xo0D44+Slv9sKRbxFfmSFKMrPXbgzvXc5dmTly4b2N8q6 CHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OBnS252vauoaeLoGy2Pd1180Qv2s4Y9APpSeQJOp5Ss=; b=Udy/6DF789K7aJ5CsaoRqFZg/OfWEbZo9x8f+Vg12l9UH7jbX8BFOjXWse2w+qjy+v Ulod9qeYBRemOk7rBTvZ5pUn+rufmQ325iZ+bobj1vbNgyPkmE2SZhU2IpKYRPi6dJ/d J7TjemNGzYw2Oxk4L9hzLqM3F8WjSYcDtCRLO2HbT0hMc78VXJpPhpp3vuXdfeze5+5p 0J04i+USBbR6FzEnbUoqCsRnrKuh4PmthEfXY81zhqEIliUFr9rWxlQAfue+hI0E0FIG gOeADzGCX/obrOsdiduD+dzXJcOS6SXHcPBMowJcQ/HHijB6lKcPBtaPQCjlcK72stib YoKA== X-Gm-Message-State: AC+VfDyFPvXmzLdsWpyJh+LcYx7EX4YKPgF2G+SZUvD0XfmlqJxDyDk5 witP8U7N+N9VK0pyYdKfxD9A67OIhJ67LIh1Gic= X-Google-Smtp-Source: ACHHUZ6jDuhq/q8g50MuPTIzsX69w6aRh3BpmTWDylqCIaXs3F0MOKB8xFY6C/1Tywr+gRiR3tCbpg== X-Received: by 2002:a05:600c:2942:b0:3f7:5d:4a06 with SMTP id n2-20020a05600c294200b003f7005d4a06mr6826886wmd.1.1687184963147; Mon, 19 Jun 2023 07:29:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/33] target/arm: Convert ld/st reg+imm9 insns to decodetree Date: Mon, 19 Jun 2023 15:28:56 +0100 Message-Id: <20230619142914.963184-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185090143100005 Content-Type: text/plain; charset="utf-8" Convert the load and store instructions which use a 9-bit immediate offset to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-13-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 69 +++++++++++ target/arm/tcg/translate-a64.c | 206 ++++++++++++++------------------- 2 files changed, 153 insertions(+), 122 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index f5787919931..d55c09684a7 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -326,3 +326,72 @@ LDP_v 10 101 1 011 1 ....... ..... ..... ...= .. @ldstpair sz=3D4 sign=3D0 p STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 + +# Load/store register (unscaled immediate) +&ldst_imm rt rn imm sz sign w p unpriv ext +@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D0 +@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D1 +@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D1 w=3D1 +@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D1 = p=3D0 w=3D0 + +STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D1 + +# PRFM : prefetch memory: a no-op for QEMU +NOP 11 111 0 00 10 0 --------- 00 ----- ----- + +STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 103e54d0c49..a1ddb1a9cdd 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3037,134 +3037,101 @@ static bool trans_STGP(DisasContext *s, arg_ldstp= air *a) return true; } =20 -/* - * Load/store (immediate post-indexed) - * Load/store (immediate pre-indexed) - * Load/store (unscaled immediate) - * - * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * - * idx =3D 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeb= ack) - 10 -> unprivileged - * V =3D 0 -> non-vector - * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - */ -static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) +static void op_addr_ldst_imm_pre(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_add= r, + uint64_t offset, bool is_store, MemOp mop) { - int rn =3D extract32(insn, 5, 5); - int imm9 =3D sextract32(insn, 12, 9); - int idx =3D extract32(insn, 10, 2); - bool is_signed =3D false; - bool is_store =3D false; - bool is_extended =3D false; - bool is_unpriv =3D (idx =3D=3D 2); - bool iss_valid; - bool post_index; - bool writeback; int memidx; - MemOp memop; - TCGv_i64 clean_addr, dirty_addr; =20 - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4 || is_unpriv) { - unallocated_encoding(s); - return; - } - is_store =3D ((opc & 1) =3D=3D 0); - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - if (idx !=3D 0) { - unallocated_encoding(s); - return; - } - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D !is_store && extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - } - - switch (idx) { - case 0: - case 2: - post_index =3D false; - writeback =3D false; - break; - case 1: - post_index =3D true; - writeback =3D true; - break; - case 3: - post_index =3D false; - writeback =3D true; - break; - default: - g_assert_not_reached(); - } - - iss_valid =3D !is_vector && !writeback; - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - if (!post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } + memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, + a->w || a->rn !=3D 31, + mop, a->unpriv, memidx); +} =20 - memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); - - clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, - writeback || rn !=3D 31, - memop, is_unpriv, memidx); - - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, memop); - } else { - do_fp_ld(s, rt, clean_addr, memop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - - if (is_store) { - do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx, - iss_valid, rt, iss_sf, false); - } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop, - is_extended, memidx, - iss_valid, rt, iss_sf, false); +static void op_addr_ldst_imm_post(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 dirty_addr, uint64_t offset) +{ + if (a->w) { + if (a->p) { + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } +} =20 - if (writeback) { - TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); - if (post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); - } - tcg_gen_mov_i64(tcg_rn, dirty_addr); +static bool trans_STR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); + + tcg_rt =3D cpu_reg(s, a->rt); + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_st_memidx(s, tcg_rt, clean_addr, mop, memidx, + iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); + + tcg_rt =3D cpu_reg(s, a->rt); + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_ld_memidx(s, tcg_rt, clean_addr, mop, + a->ext, memidx, iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_STR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; } + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); + do_fp_st(s, a->rt, clean_addr, mop); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; + } + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); + do_fp_ld(s, a->rt, clean_addr, mop); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; } =20 /* @@ -3637,12 +3604,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t= insn) switch (extract32(insn, 24, 2)) { case 0: if (extract32(insn, 21, 1) =3D=3D 0) { - /* Load/store register (unscaled immediate) - * Load/store immediate pre/post-indexed - * Load/store register unprivileged - */ - disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); - return; + break; } switch (extract32(insn, 10, 2)) { case 0: --=20 2.34.1