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([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689967; x=1689281967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CLGO//MY4I5Oc61K3sYPrsApC28gAwnypQlxx+aTI6U=; b=BuUDnV2/qLNu+TAJKF2icXMpNp4zm9hhydfScStUVor0OORd6eo1VXO8SrKnfgjD6H jrEvYxmMdKalp1idZMZTEwsUErW9tuivxduEcFAqLitg1QOpIFKqNOwWHfaQ1iXCm/mp ZxjdcaQ7ZNvGqxvMsu/dH35c3gxQIR8Lv6XOWoQWwWpiIBPfCINcXWfC757CFp0BVnqQ Y4urPmzjUI15VncqL1LMvfsP6WCzSXKrRZrv4QiTyaiVnmkW+kRU/mtU03Wso1JAibnG MGHeK97ZZ2TgG3rN3qCaAbnfqukYggiI3eUPP8GhFFnGntayuHPKL7BmM7IadRXHyUbS kADQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689967; x=1689281967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CLGO//MY4I5Oc61K3sYPrsApC28gAwnypQlxx+aTI6U=; b=KlsTE6ne8d2Xk5Mof3hlKngFHmlQ4TFF0nbOa1BICrungyEMeuxKC2kXO8qr1aKU1b mNUxC7+MtxzYQbbbleVu9+cZpbGAMi5c4wQCVb967wfQwauin2qHxObpHJhK/ol2CbeY KHRNa7K9oLxmslFrfuEEv/CdMhXTafFM7aokpPfp9V3D11c/FnqR5THUwT3oiCpG1cE0 fknm/sGzHLqWdFaW/KbnDi5XJoK34Ajc7mj5s0KGK/nt45TqbM+h0W2qMELlFJ+xmn+P 9LZCvYpOXbcqNmCkVZFlF/yRUhZl4YeXJk4uWIJNZWuEitPgJxwXdZCqUReavj+9z6f+ kbEw== X-Gm-Message-State: AC+VfDyItS/+P45Q1JFCE1+ngLVJTbt0gLCQF6FfTS16mhyNNl6eqdY2 B/e8+6nX1BEhTfmkclYpMBGU1dzQbheJVDhVvWA= X-Google-Smtp-Source: ACHHUZ5XO23URy6JkJef5jIw0lVQz+4a3jtpJ04nHAYmxWUaVnsufOGuqkG+HiH5p718Hlr0oV7rkw== X-Received: by 2002:a05:6808:1c8:b0:39c:5d03:6a5a with SMTP id x8-20020a05680801c800b0039c5d036a5amr8050479oic.7.1686689966895; Tue, 13 Jun 2023 13:59:26 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 04/18] target/riscv/cpu.c: restrict 'mimpid' value Date: Tue, 13 Jun 2023 17:58:43 -0300 Message-Id: <20230613205857.495165-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690067557100005 Content-Type: text/plain; charset="utf-8" Following the same logic used with 'mvendorid' let's also restrict 'mimpid' for named CPUs. Generic CPUs keep setting the value freely. Note that we're getting rid of the default RISCV_CPU_MARCHID value. The reason is that this is not a good default since it's dynamic, changing with with every QEMU version, regardless of whether the actual implementation of the CPU changed from one QEMU version to the other. Named CPU should set it to a meaningful value instead and generic CPUs can set whatever they want. This is the error thrown for an invalid 'mimpid' value for the veyron-v1 CPU: $ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=3D2 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=3D2: Unable to change veyron-v1-riscv-cpu mimpid (0x111) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a9a6d34eb..39c550682a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,7 +42,6 @@ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ (QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MICRO)) -#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID =20 static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 @@ -1735,7 +1734,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -1854,6 +1852,35 @@ static void cpu_get_mvendorid(Object *obj, Visitor *= v, const char *name, visit_type_bool(v, name, &value, errp); } =20 +static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mimpid (0x%lx)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid =3D value; +} + +static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mimpid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -1888,6 +1915,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); =20 + object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, + cpu_set_mimpid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.40.1