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([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689958; x=1689281958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hdlVCgCsofoU3sFhayk2xbcE3ncEw8ypwrBf9jIXxPE=; b=IikGr5frSWPiVYu+iUe//e1Jj8dnqyz5eb4uGSZPilsNlK6JqRE78EHkrcfMxOmqMt LK7gOOLGgTL11iyuTBEW/VEvfgldH2F3vlulagjn1P274tCQOeg4ZEQTgOBb1IEXmQXD 44184uT1u41xjOLi4d8wIA7FQR0Of6J4ro8ucDSLoBAEj+on9L9BjtZ5lsGsXha69TZ1 dcqR786B4vW8VJsZUwkdiZSbWhSZ9gxCVUPc7JzFw5OLVSfUqn3GwvMniO10BuTwur7W 7y9GPGRgya9uY06GMWsiO/JYlI+P7JP8lkyvmYgOVAZSGSJmw75GDkZKqB9/Mgo4/Cwq s7sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689958; x=1689281958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hdlVCgCsofoU3sFhayk2xbcE3ncEw8ypwrBf9jIXxPE=; b=MbMKhr7IjZmEGjqR8NHI6H9HZL4iNBATgmc9QdnvlJIK1UYvaQANgP/9vr5qAYgjvj zR0fB9T3kCp4GCEkbq3OK/yFTCfpoj7ns0RFr2IXvLblb4xh7nTY7kKg+KJbxgxHBqvN h1/xAow7AS7EbRWXml1FisuzAmOAOx7g2wl3LNidv/wdtCJcxyEorof9FFZk9PqbhZt3 oQu52j7XbY6aCexrQx29vV1SQzpF1OCXydwnH2ck9Qf5cT0/7AMFryflNEkBmG/BGuWg +5q9pKvxMgVxZgcg1wanYBeqrYy5wvI3HydvHYauzBMwrvhD7CUJNPD0KIey9WIo3eF8 k2IQ== X-Gm-Message-State: AC+VfDygafRd9Ywb4+HcK/FAJqN1IfnBOvVELgGs2fX09g6z35yMSwLE HIHWxgswyyYSK5DWalr7EvGVQgPrpLdgN7SAIIA= X-Google-Smtp-Source: ACHHUZ46jxEeCBMk6z7agJztuoSYzJJmkWes2zncx0Xz3LKaHYu4/u6wiAbIihW5+BAcGZS/WisMRA== X-Received: by 2002:a05:6808:1881:b0:39c:7b95:ddc0 with SMTP id bi1-20020a056808188100b0039c7b95ddc0mr9937942oib.35.1686689958378; Tue, 13 Jun 2023 13:59:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 01/18] target/riscv: skip features setup for KVM CPUs Date: Tue, 13 Jun 2023 17:58:40 -0300 Message-Id: <20230613205857.495165-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690037213100003 Content-Type: text/plain; charset="utf-8" As it is today it's not possible to use '-cpu host' if the RISC-V host has RVH enabled. This is the resulting error: $ sudo ./qemu/build/qemu-system-riscv64 \ -machine virt,accel=3Dkvm -m 2G -smp 1 \ -nographic -snapshot -kernel ./guest_imgs/Image \ -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ -append "earlycon=3Dsbi root=3D/dev/ram rw" \ -cpu host qemu-system-riscv64: H extension requires priv spec 1.12.0 This happens because we're checking for priv spec for all CPUs, and since we're not setting env->priv_ver for the 'host' CPU, it's being default to zero (i.e. PRIV_SPEC_1_10_0). In reality env->priv_ver does not make sense when running with the KVM 'host' CPU. It's used to gate certain CSRs/extensions during translation to make them unavailable if the hart declares an older spec version. It doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs are available [1]. 'priv_ver' is just one example. We're doing a lot of feature validation and setup during riscv_cpu_realize() that it doesn't apply KVM CPUs. Validating the feature set for those CPUs is a KVM problem that should be handled in KVM specific code. The new riscv_cpu_realize_features() helper contains all validation logic that are not applicable to KVM CPUs. riscv_cpu_realize() verifies if we're dealing with a KVM CPU and, if not, execute the new helper to proceed with the usual realize() logic for all other CPUs. [1] lib/sbi/sbi_hart.c, hart_detect_features() Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 881bddf393..e904018644 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -331,6 +331,15 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 +static bool riscv_running_kvm(void) +{ +#ifndef CONFIG_USER_ONLY + return kvm_enabled(); +#else + return false; +#endif +} + static void riscv_any_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -1304,20 +1313,12 @@ static void riscv_cpu_validate_misa_priv(CPURISCVSt= ate *env, Error **errp) } } =20 -static void riscv_cpu_realize(DeviceState *dev, Error **errp) +static void riscv_cpu_realize_features(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - riscv_cpu_validate_misa_mxl(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1352,7 +1353,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 #ifndef CONFIG_USER_ONLY - cs->tcg_cflags |=3D CF_PCREL; + CPU(dev)->tcg_cflags |=3D CF_PCREL; =20 if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); @@ -1365,6 +1366,28 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } } #endif +} + +static void riscv_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs =3D CPU(dev); + RISCVCPU *cpu =3D RISCV_CPU(dev); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + Error *local_err =3D NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + if (!riscv_running_kvm()) { + riscv_cpu_realize_features(dev, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + } =20 riscv_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { --=20 2.40.1