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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499247; x=1689091247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=N3PW9VYsAGC1K2Fi7FePAHwlou4P1DBl1fvZGT4Ua6o=; b=R3EahtEMoyCM0Z+UROplgAYMMPCKNPfbwBnGvJKOfrWp5vOkPJbW8ZK9hJc3ZbUpVI 5+qqx618f7pY/7FbXgfn8CkyjwBbG0Jzdp/GlPrr618ap7R+HqFv2l9d+9tpFfIo46Xy bnfwPL67QDXA/nnDyryiQBW7OhM0OiRnelNdWlsyzgp4g+k230yOKmMb1Sz+rM8H3brs T/TRT/Jc6ud0kmsDgRoaPrzfrKiTh1YGVP1syU9xLaC0r2+siCc21hmE10kHn+To0591 ZoDUT9eeL5GqqdaaDvVkBevbZb+yZn/5K+CW2IXbP/GFL22m+tb+PaBdStjwr96JEAJW wv4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499247; x=1689091247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N3PW9VYsAGC1K2Fi7FePAHwlou4P1DBl1fvZGT4Ua6o=; b=h8b+kMgGeijlhj3F8xVGOMhhH/hkTQjHZFOx9aLcWAqAxTDZNMKystY7dhgPgYM/Dc 9Y1h+bVtKSOXLyw+Mm3EIk+TEUFCFodCdVlXDdAkqIV2wqigfaxj2gIV96f1B5IPzN2W oFasdfgjQcVIuNQDF5HG5rf1qqrgUTOKDvAYcWobvVG8Qduocn4RiFE3TYxNQfZVZg7R uzEXZlN924rKMEN3j8Y3XhWus2DLW3LD8wItB/2iSYoZbZrScLLXUkE3e1qe/WNgNOs3 1KAPAuHRHpKmxA6Zea7lro0VlVALGYvpiAe+UOaJe2IP5lVuhv4InOcgosh3WI2dPq7N mjmw== X-Gm-Message-State: AC+VfDx7/lb3ySo5Fvit0kv6JcXRHJd34x6A99Tz1rPClen7/+OwvJTF qhHK0n01MaHPekdRgJBnGteXEmlmInbctrnf5uY= X-Google-Smtp-Source: ACHHUZ5pisSMJqRMcubg0WtV4BPnLOVkSKOttbeHmK/73zLaIg878QB4u481/LEi+CRQ/qaXxe/FjA== X-Received: by 2002:adf:e906:0:b0:30f:be0f:fbf with SMTP id f6-20020adfe906000000b0030fbe0f0fbfmr1109970wrm.22.1686499247015; Sun, 11 Jun 2023 09:00:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 23/23] target/arm: Convert load/store tags insns to decodetree Date: Sun, 11 Jun 2023 17:00:32 +0100 Message-Id: <20230611160032.274823-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499594315100007 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store memory tags instruction group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-21-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 25 +++ target/arm/tcg/translate-a64.c | 360 ++++++++++++++++----------------- 2 files changed, 199 insertions(+), 186 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 4ffdc91865f..ef64a3f9cba 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -528,3 +528,28 @@ LD_single 0 . 001101 . 1 . ..... 10 . 001 ...= .. ..... @ldst_single_d =20 # Replicating load case LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem= =3D%ldst_single_selem + +%tag_offset 12:s9 !function=3Dscale_by_log2_tag_granule +&ldst_tag rn rt imm p w +@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=3D%tag_= offset +@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=3D0 + +STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6e7fe1f35cf..43963287a8c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -62,6 +62,12 @@ static int uimm_scaled(DisasContext *s, int x) return imm << scale; } =20 +/* For load/store memory tags: scale offset by LOG2_TAG_GRANULE */ +static int scale_by_log2_tag_granule(DisasContext *s, int x) +{ + return x << LOG2_TAG_GRANULE; +} + /* * Include the generated decoders. */ @@ -3712,185 +3718,184 @@ static bool trans_LD_single_repl(DisasContext *s,= arg_LD_single_repl *a) return true; } =20 -/* - * Load/Store memory tags - * - * 31 30 29 24 22 21 12 10 5 0 - * +-----+-------------+-----+---+------+-----+------+------+ - * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | - * +-----+-------------+-----+---+------+-----+------+------+ - */ -static void disas_ldst_tag(DisasContext *s, uint32_t insn) +static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; - int op2 =3D extract32(insn, 10, 2); - int op1 =3D extract32(insn, 22, 2); - bool is_load =3D false, is_pair =3D false, is_zero =3D false, is_mult = =3D false; - int index =3D 0; TCGv_i64 addr, clean_addr, tcg_rt; + int size =3D 4 << s->dcz_blocksize; =20 - /* We checked insn bits [29:24,21] in the caller. */ - if (extract32(insn, 30, 2) !=3D 3) { - goto do_unallocated; + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; } =20 - /* - * @index is a tri-state variable which has 3 states: - * < 0 : post-index, writeback - * =3D 0 : signed offset - * > 0 : pre-index, writeback - */ - switch (op1) { - case 0: - if (op2 !=3D 0) { - /* STG */ - index =3D op2 - 2; - } else { - /* STZGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_zero =3D true; - } - break; - case 1: - if (op2 !=3D 0) { - /* STZG */ - is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDG */ - is_load =3D true; - } - break; - case 2: - if (op2 !=3D 0) { - /* ST2G */ - is_pair =3D true; - index =3D op2 - 2; - } else { - /* STGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D true; - } - break; - case 3: - if (op2 !=3D 0) { - /* STZ2G */ - is_pair =3D is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_load =3D true; - } - break; - - default: - do_unallocated: - unallocated_encoding(s); - return; - } - - if (is_mult - ? !dc_isar_feature(aa64_mte, s) - : !dc_isar_feature(aa64_mte_insn_reg, s)) { - goto do_unallocated; - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - addr =3D read_cpu_reg_sp(s, rn, true); - if (index >=3D 0) { + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); + } + /* + * The non-tags portion of STZGM is mostly like DC_ZVA, + * except the alignment happens before the access. + */ + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_helper_dc_zva(cpu_env, clean_addr); + return true; +} + +static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stgm(cpu_env, addr, tcg_rt); + } else { + MMUAccessType acc =3D MMU_DATA_STORE; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + } + return true; +} + +static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_ldgm(tcg_rt, cpu_env, addr); + } else { + MMUAccessType acc =3D MMU_DATA_LOAD; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + /* The result tags are zeros. */ + tcg_gen_movi_i64(tcg_rt, 0); + } + return true; +} + +static bool trans_LDG(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { /* pre-index or signed offset */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } =20 - if (is_mult) { - tcg_rt =3D cpu_reg(s, rt); + tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); + tcg_rt =3D cpu_reg(s, a->rt); + if (s->ata) { + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + } else { + /* + * Tag access disabled: we must check for aborts on the load + * load from [rn+offset], and then insert a 0 tag into rt. + */ + clean_addr =3D clean_data_tbi(s, addr); + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); + gen_address_with_allocation_tag0(tcg_rt, tcg_rt); + } =20 - if (is_zero) { - int size =3D 4 << s->dcz_blocksize; - - if (s->ata) { - gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); - } - /* - * The non-tags portion of STZGM is mostly like DC_ZVA, - * except the alignment happens before the access. - */ - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_helper_dc_zva(cpu_env, clean_addr); - } else if (s->ata) { - if (is_load) { - gen_helper_ldgm(tcg_rt, cpu_env, addr); - } else { - gen_helper_stgm(cpu_env, addr, tcg_rt); - } - } else { - MMUAccessType acc =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; - int size =3D 4 << GMID_EL1_BS; - - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_probe_access(s, clean_addr, acc, size); - - if (is_load) { - /* The result tags are zeros. */ - tcg_gen_movi_i64(tcg_rt, 0); - } + if (a->w) { + /* pre-index or post-index */ + if (a->p) { + /* post-index */ + tcg_gen_addi_i64(addr, addr, a->imm); } - return; + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); + } + return true; +} + +static bool do_STG(DisasContext *s, arg_ldst_tag *a, bool is_zero, bool is= _pair) +{ + TCGv_i64 addr, tcg_rt; + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); } =20 - if (is_load) { - tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); - tcg_rt =3D cpu_reg(s, rt); - if (s->ata) { - gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(addr, addr, a->imm); + } + tcg_rt =3D cpu_reg_sp(s, a->rt); + if (!s->ata) { + /* + * For STG and ST2G, we need to check alignment and probe memory. + * TODO: For STZG and STZ2G, we could rely on the stores below, + * at least for system mode; user-only won't enforce alignment. + */ + if (is_pair) { + gen_helper_st2g_stub(cpu_env, addr); } else { - /* - * Tag access disabled: we must check for aborts on the load - * load from [rn+offset], and then insert a 0 tag into rt. - */ - clean_addr =3D clean_data_tbi(s, addr); - gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); - gen_address_with_allocation_tag0(tcg_rt, tcg_rt); + gen_helper_stg_stub(cpu_env, addr); + } + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, addr, tcg_rt); } } else { - tcg_rt =3D cpu_reg_sp(s, rt); - if (!s->ata) { - /* - * For STG and ST2G, we need to check alignment and probe memo= ry. - * TODO: For STZG and STZ2G, we could rely on the stores below, - * at least for system mode; user-only won't enforce alignment. - */ - if (is_pair) { - gen_helper_st2g_stub(cpu_env, addr); - } else { - gen_helper_stg_stub(cpu_env, addr); - } - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (is_pair) { - gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg_parallel(cpu_env, addr, tcg_rt); - } + if (is_pair) { + gen_helper_st2g(cpu_env, addr, tcg_rt); } else { - if (is_pair) { - gen_helper_st2g(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg(cpu_env, addr, tcg_rt); - } + gen_helper_stg(cpu_env, addr, tcg_rt); } } =20 @@ -3911,32 +3916,21 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) } } =20 - if (index !=3D 0) { + if (a->w) { /* pre-index or post-index */ - if (index < 0) { + if (a->p) { /* post-index */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); } + return true; } =20 -/* Loads and stores */ -static void disas_ldst(DisasContext *s, uint32_t insn) -{ - switch (extract32(insn, 24, 6)) { - case 0x19: - if (extract32(insn, 21, 1) !=3D 0) { - disas_ldst_tag(s, insn); - } else { - unallocated_encoding(s); - } - break; - default: - unallocated_encoding(s); - break; - } -} +TRANS_FEAT(STG, aa64_mte_insn_reg, do_STG, a, false, false) +TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true, false) +TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true) +TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true) =20 typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); =20 @@ -13832,12 +13826,6 @@ static bool btype_destination_ok(uint32_t insn, bo= ol bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0x4: - case 0x6: - case 0xc: - case 0xe: /* Loads and stores */ - disas_ldst(s, insn); - break; case 0x5: case 0xd: /* Data processing - register */ disas_data_proc_reg(s, insn); --=20 2.34.1