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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686473986800100005 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- plugins/core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/plugins/core.c b/plugins/core.c index 9912f2cfdb..3c4e26c7ed 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -25,7 +25,6 @@ =20 #include "exec/exec-all.h" #include "exec/tb-flush.h" -#include "exec/helper-proto.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "plugin.h" --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id u5-20020a5d5145000000b0030fa57d8064sm5839270wrt.52.2023.06.11.01.58.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:58:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473936; x=1689065936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fOqRAxEV8Qalm9ZgxaBgc+XRBEy5Pw0OdcKw70bIFoY=; b=b7WmROGZbK43nUXk0JH8LMzqlBm4OgfAfa5jsYJHAdo5N9juZ5f+v6DaNkUqfbhZYx qzShfc/V5vTPLeq3qPh1tEyulfDdOlxU4k+uco7UkF5zAOBQHLVoB50XnyWgfzZME583 iPejQ3/IrjnAAm9NXMxawlXIpq5exmdfGpo5j4n0K5LlCB7ebh7w92pVDk74HjfNQC9E hYLB6tL1N2OI0Ch7L4Z5hkhU2LDqhlCEjH0Cg6OeY44kscVhF0cK98cHsCe/P6Uaq4BV 405JgqN1//e179egrhH8bgHZJ30Ded9mU64d2IJLNjQ+Tp2y2teZxs+LwiGS+1bn3bM3 0xrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473936; x=1689065936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fOqRAxEV8Qalm9ZgxaBgc+XRBEy5Pw0OdcKw70bIFoY=; b=LZXHfzXLEdXn6A6DHjtYA+ne3ioeSwzsURf8TKuUsQoOeT+PG/tZBoweP+qeuHWuee QGvXJZ5Ne5NdShptBTYJkZLp24oIJuJOkSS194H+rBlkBeWnPbs6M+JZ7h0quultRnZJ +q1U6xz82t0GPnJbYhB3sJCH0oSd/84d/0ge6g7vgyrnNm9HRslw/zVOsXxIIJev7FQl 5kFQtqj/GmCgxfmKlZf7Hlv0CKuD55i8kegi9aWf6g/hbQAGx47oagChgoxZTRV72+y4 JeeB4WQqp5lWbBqUjRbzBKRBlV4yZES7u4iaHelCgkn04H13kEMaPu8fVXo+koR22hD2 yxZQ== X-Gm-Message-State: AC+VfDzOk7BEu32aHhWBVgb67lWHNefSDP0JidJq3OPPQzqShOYXWW9+ C89OpXy8rBr1TyyltxkiMuoLREF/Z6qIDUAAbOw= X-Google-Smtp-Source: ACHHUZ5ydqEvb3BC7ZEr5UdbF4T08B7bsVV7fb0CZzdagZCX5pSfkXHCQSeFqLHEQbCX4kt/0BLHvQ== X-Received: by 2002:a05:6000:1371:b0:30e:4254:2264 with SMTP id q17-20020a056000137100b0030e42542264mr2690517wrz.55.1686473936727; Sun, 11 Jun 2023 01:58:56 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 02/26] accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' header Date: Sun, 11 Jun 2023 10:58:22 +0200 Message-Id: <20230611085846.21415-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474041149100003 We only need lookup_tb_ptr() prototype. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cpu-exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 42086525d7..12362177af 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -38,7 +38,7 @@ #include "sysemu/cpu-timers.h" #include "exec/replay-core.h" #include "sysemu/tcg.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474105; cv=none; d=zohomail.com; s=zohoarc; b=nrJvIuPUPpEib48DKl5Gc6pKwg1lHQKT/lNk6P42FR59FHwoynPUBkPMdidwU8fG5filHC4nSHDLkL2tEcUMshU27yR15qUJcqrcWJg0l+tDigNpEZnegDIzr5wWFL6Ru+jVIdRSaFSLklp8DEyvQQ6L674udPI5U1VOOvPqw64= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474105; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8mp+80uEQkt8/jSa2bwpDOFe4dhC6+cPTb9ADdk/0oE=; b=mTg8TD8qLsCUwSI6Jqxn7HwewVouGtM25DWeEuB9ehjwMjEyaXh90WqQ0y3qPLhQpPiSEtw2O/0k4xMyyK8M2bucBLoJHlLadChcTceMVr6Ccfqymz/ZjCP/PvWuiS6Bs+AOGTZh3JtVTzfi7XlfrOZkcjKPdIEQYYHq5aWJPmE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474105322786.1778125609725; Sun, 11 Jun 2023 02:01:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Guf-0000ym-Bc; Sun, 11 Jun 2023 04:59:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gue-0000yQ-B7 for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:04 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Guc-0003Z7-QX for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:04 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f7378a74faso23262855e9.0 for ; Sun, 11 Jun 2023 01:59:02 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id f3-20020a7bc8c3000000b003f1958eeadcsm7734318wml.17.2023.06.11.01.59.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473941; x=1689065941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8mp+80uEQkt8/jSa2bwpDOFe4dhC6+cPTb9ADdk/0oE=; b=Lntpl/tLzwChIdrOT2922M1h4tmPmJZV1cT8TRyvzNukM0+uhmGpwoZ2gacfHy1dNx 4Qicjss9uEAchFDNmuru2VCqaECt6NnDDLNHOLIDmQ+DGAhZ+wu5/5M0j1O8/BCX6Wey SY1c1oa9kPVI4zr6RGh93rqoW+oF3Gff9hihZI/DqDa619SBlKQ81CDwPaC7LFlCrxnC lcZY2obeJU9ZZFx08nEOaorGi6BrAOhjsu4LdrQpie8gEKfHLdvc7cikR1Dd+1T3L/NG eX8klQ7zwMgBstw0S2t39ZEyooGR5SDyVqv3UXkCW/gTx/xE0pK4YFwmdsgU/NrEuhpn AaRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473941; x=1689065941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8mp+80uEQkt8/jSa2bwpDOFe4dhC6+cPTb9ADdk/0oE=; b=S1srw3Vaw8L70rqB1ddRYMYwuLgXivJueEA3S4fyHCm0bl7vL/M+Y/qwBrPhR6qNPO JMErrnmPwKA+C9eBd5RHXngSJAg2WYZ4FiNpwegBpMhzQt8FHeZYSFx4yY0PqG7Vi5HO sRO0T/S1t87Kfps1/EsQqE4ZwZU06YZDDw2n4PkA5R2nztOKkl4+Z8khMyJkYdIPRVS6 fV5/LFCTgq33izwjSMu28Qa7beub3qEyT5mCKvnz0xMFahqVp0s6C7hIH1PJ6gAtUcs/ WNrL6RwedeQNn0n5LWWKCrCMtTXEuyyRSP2W7EV+1c4qrOWv9KUkmhOMyJM8U62MEiva 2h8Q== X-Gm-Message-State: AC+VfDwW3r9mkKn6/VvRg030KhRFFxLvYzJF9dFBGguR4j8TUCZlrMZm o7Lu2iT6oYNJvZ4Q2blGW3UR7ImMn/k7SarepU4= X-Google-Smtp-Source: ACHHUZ6V1eUMyTy1/gr8TvXgt25o5O567Ye5QYeDsJj3B1dVFCILz5pb9SQrrrqnw8EP4HjU9BkXBw== X-Received: by 2002:a7b:c397:0:b0:3f6:688:f658 with SMTP id s23-20020a7bc397000000b003f60688f658mr3739595wmj.20.1686473941257; Sun, 11 Jun 2023 01:59:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/26] target/arm/tcg: Remove CONFIG_TCG #ifdef'ry check Date: Sun, 11 Jun 2023 10:58:23 +0200 Message-Id: <20230611085846.21415-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474106455100006 CONFIG_TCG is always defined within target/arm/tcg/. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/cpu32.c | 4 +--- target/arm/tcg/m_helper.c | 6 ------ 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 47d2e8e781..0672519b89 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -13,11 +13,9 @@ #include "hw/core/tcg-cpu-ops.h" #include "internals.h" #include "target/arm/idau.h" +#include "cpregs.h" #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" -#endif -#include "cpregs.h" -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) #include "hw/intc/armv7m_nvic.h" #endif =20 diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 9cef70e5c9..0891acc29c 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -15,10 +15,8 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "exec/exec-all.h" -#ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" -#endif #if !defined(CONFIG_USER_ONLY) #include "hw/intc/armv7m_nvic.h" #endif @@ -2345,11 +2343,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); -#ifdef CONFIG_TCG do_common_semihosting(cs); -#else - g_assert_not_reached(); -#endif env->regs[15] +=3D env->thumb ? 2 : 4; return; case EXCP_BKPT: --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686473986; cv=none; d=zohomail.com; s=zohoarc; b=JDYyt7kG/5o9KJePC5erJYVbvL5+wjasz5XI+CHhXRwaxsyuADtG403YPPZ24ykrvyWX8d+mfa6XtItTpxlkOcBL0/lKIlgAgdTUFiJH2o9YnGCwyqsic/BXIt2sXnQGV9TVtKY7r1E9zwl7tv4nCZgkvWr8KD9WZ+cX7ktPMqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686473986; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oIvtCmiWepPA7NXEFbXWWLePEDf5Lnkm5evgEG2zaNg=; b=cQxmkJSCEDwVaiyJ02EbjDj5t6PhDaEscN5zJVZXscfO+45Ehio0gfxMy+ztVjMy1w9eIU9YG/JlpdhDvH3Rh0i+ROH3b2qvIA6pSCqxtWdPi3Y7nAEMT3FneOVwNYECmSGm59Wr9Np3IxKlOWonapBtDKTKCoPGlhS9/qfKq5A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686473986430629.2283404124531; Sun, 11 Jun 2023 01:59:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Guk-000106-VG; Sun, 11 Jun 2023 04:59:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gui-0000zN-Uw for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:08 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Guh-0003a8-EB for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:08 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3f6d3f83d0cso33978215e9.2 for ; Sun, 11 Jun 2023 01:59:07 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id x22-20020a05600c21d600b003f70a7b4537sm7855052wmj.36.2023.06.11.01.59.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473946; x=1689065946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oIvtCmiWepPA7NXEFbXWWLePEDf5Lnkm5evgEG2zaNg=; b=sAhBNdzBBnGJ9+/VPT/pteV9lzaEYA4Lt5lf4FbDBG7Yg6IfQTllC7h/kvLmt+iRid V+FMxlJQulzydVThmgYHQmawz2YrYPrM8qOvnKEK+XLPqJ6jnAsWhPimyUkrF5u741qj pbSrpyofWKtTiExxETG6OUWsiJnhugMKpArYgkNcwZ2lLe45iJja1AYXzHhSpN0Lfjhv X6Gc9Y+sSmY3oOB8qgOMmPMag1BCbyMNl7WU8ImvKpo9KDoXSfdJAjEOT0dtABfCmNhb S4jxApj84y3r9zKU8qSBUPFoHt1z3r9FrJJtnplBStCNgSDlvvyfKNQ8VEMjpPyvcwRf /Jjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473946; x=1689065946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oIvtCmiWepPA7NXEFbXWWLePEDf5Lnkm5evgEG2zaNg=; b=DUtSoL00FCyC/39hqACKlWkzIRPz0UMqScNZ5JNCa23TbA16h6/sgodU2eNDupjKdE ggugHfo7bQoOMz5E6eNRXA2VQjV2+l65qchyFa+NCRIBMxuJtb2hy00oN088FHqIKuQz dqMORhR1rAnFcewQIOmr+mrHSi9S5Y4qrOkeZZh8T0i6BDGiOkGTMqs8hP0X1w4OK+Kr ypjB17u9QnJnDHa5kQN95JWiPVKNBZdzJqCDCwvooYWidlAd7rYolYE+WCcz79K/OR+3 lU2OEhqrDQobZuQD6UI0aF6baYi+MyTudXXuRBXN0aOdj+2vrd+hMQTbDpBsONRm+6d+ KjHg== X-Gm-Message-State: AC+VfDysH0NuwBcrXl3RJCCTKAdsIqKSNRjk8BjBpy/EPUro+MrK529d djmgljGrbDsTzrVWt8ZdG/8+UHXrFeIv1540Ji8= X-Google-Smtp-Source: ACHHUZ4S1tn+9L3uWD2Md3auZQa2H/ggSuQEhVnVzwBPIBlan7qdsA1q2/qIU/7VJ0Dke6pe3TSjfg== X-Received: by 2002:a1c:7203:0:b0:3f7:e800:abd2 with SMTP id n3-20020a1c7203000000b003f7e800abd2mr5404360wmc.35.1686473945911; Sun, 11 Jun 2023 01:59:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/26] target/arm/tcg: Rename helper template headers as '.h.inc' Date: Sun, 11 Jun 2023 10:58:24 +0200 Message-Id: <20230611085846.21415-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686473986831100006 Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename the included templates as '.h.inc'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 8 ++++---- target/arm/tcg/{helper-a64.h =3D> helper-a64.h.inc} | 0 target/arm/tcg/{helper-mve.h =3D> helper-mve.h.inc} | 0 target/arm/tcg/{helper-sme.h =3D> helper-sme.h.inc} | 0 target/arm/tcg/{helper-sve.h =3D> helper-sve.h.inc} | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename target/arm/tcg/{helper-a64.h =3D> helper-a64.h.inc} (100%) rename target/arm/tcg/{helper-mve.h =3D> helper-mve.h.inc} (100%) rename target/arm/tcg/{helper-sme.h =3D> helper-sme.h.inc} (100%) rename target/arm/tcg/{helper-sve.h =3D> helper-sve.h.inc} (100%) diff --git a/target/arm/helper.h b/target/arm/helper.h index 3335c2b10b..4218d98b51 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1039,9 +1039,9 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 #ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h" -#include "tcg/helper-sve.h" -#include "tcg/helper-sme.h" +#include "tcg/helper-a64.h.inc" +#include "tcg/helper-sve.h.inc" +#include "tcg/helper-sme.h.inc" #endif =20 -#include "tcg/helper-mve.h" +#include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h.inc similarity index 100% rename from target/arm/tcg/helper-a64.h rename to target/arm/tcg/helper-a64.h.inc diff --git a/target/arm/tcg/helper-mve.h b/target/arm/tcg/helper-mve.h.inc similarity index 100% rename from target/arm/tcg/helper-mve.h rename to target/arm/tcg/helper-mve.h.inc diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h.inc similarity index 100% rename from target/arm/tcg/helper-sme.h rename to target/arm/tcg/helper-sme.h.inc diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h.inc similarity index 100% rename from target/arm/tcg/helper-sve.h rename to target/arm/tcg/helper-sve.h.inc --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474348; cv=none; d=zohomail.com; s=zohoarc; b=h4AqloDHiXPzni7x0bqvglrv71Darwbf3/lAoW/j/qVC3/Jvp47/umZ+rW00vAIH1+XkEMDdKXr0cPojrVF9splGq3bh/JxduM0WDA7c1ZNGt45Ra47XUyR1gkMkIlWZTe0jHnUSnUu2KeFP4wjsOv/4NIli7S43ZcdmW4cQTxg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474348; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lhArNuatDNYVRkaFGuTDa+3jxPD4OXoWAoXbKpvzLCo=; b=K3sWxZ1fPR29EBoz0eIsGdqmeLN5+3U1SlySxXf6rQN6gphLJRPJWSWpCIHOPTWsIS49MF90rrLTay1sBD+1LDOYAQgMoHw80NGCvTJEa5kyvIXyEeLQeXqgHb3AJqZ8DiyiM/HTihdZSPwIQfRJmkLacNdXC+SZL6Gfb9yQhO4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474348044919.7951490327326; Sun, 11 Jun 2023 02:05:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Guq-00011b-OA; Sun, 11 Jun 2023 04:59:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Guo-00010n-Ns for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:14 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gum-0003bL-Ol for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:14 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f78a32266bso32980545e9.3 for ; Sun, 11 Jun 2023 01:59:12 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. 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To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/26] target/arm/tcg: Extract iwMMXt helpers from the generic 'helper.h' Date: Sun, 11 Jun 2023 10:58:25 +0200 Message-Id: <20230611085846.21415-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474349810100001 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 96 +-------------------------- target/arm/tcg/helper-iwmmxt.h.inc | 103 +++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 95 deletions(-) create mode 100644 target/arm/tcg/helper-iwmmxt.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index 4218d98b51..c4a321c0ea 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -445,101 +445,6 @@ DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr) DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr) =20 -/* iwmmxt_helper.c */ -DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) -DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) - -#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ -DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ - -DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) -DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) - -DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) - -DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) - -DEF_IWMMXT_HELPER_SIZE_ENV(mins) -DEF_IWMMXT_HELPER_SIZE_ENV(minu) -DEF_IWMMXT_HELPER_SIZE_ENV(maxs) -DEF_IWMMXT_HELPER_SIZE_ENV(maxu) - -DEF_IWMMXT_HELPER_SIZE_ENV(subn) -DEF_IWMMXT_HELPER_SIZE_ENV(addn) -DEF_IWMMXT_HELPER_SIZE_ENV(subu) -DEF_IWMMXT_HELPER_SIZE_ENV(addu) -DEF_IWMMXT_HELPER_SIZE_ENV(subs) -DEF_IWMMXT_HELPER_SIZE_ENV(adds) - -DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) -DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) - -DEF_HELPER_1(iwmmxt_bcstb, i64, i32) -DEF_HELPER_1(iwmmxt_bcstw, i64, i32) -DEF_HELPER_1(iwmmxt_bcstl, i64, i32) - -DEF_HELPER_1(iwmmxt_addcb, i64, i64) -DEF_HELPER_1(iwmmxt_addcw, i64, i64) -DEF_HELPER_1(iwmmxt_addcl, i64, i64) - -DEF_HELPER_1(iwmmxt_msbb, i32, i64) -DEF_HELPER_1(iwmmxt_msbw, i32, i64) -DEF_HELPER_1(iwmmxt_msbl, i32, i64) - -DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) - -DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) - DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) @@ -1044,4 +949,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif =20 +#include "tcg/helper-iwmmxt.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-iwmmxt.h.inc b/target/arm/tcg/helper-iwm= mxt.h.inc new file mode 100644 index 0000000000..955ab2365b --- /dev/null +++ b/target/arm/tcg/helper-iwmmxt.h.inc @@ -0,0 +1,103 @@ +/* + * XScale iwMMXt specific helper definitions + * + * Copyright (c) 2007 OpenedHand, Ltd. + * Written by Andrzej Zaborowski + * Copyright (c) 2008 CodeSourcery + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) +DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) + +#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ +DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ + +DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) +DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) + +DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) + +DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) + +DEF_IWMMXT_HELPER_SIZE_ENV(mins) +DEF_IWMMXT_HELPER_SIZE_ENV(minu) +DEF_IWMMXT_HELPER_SIZE_ENV(maxs) +DEF_IWMMXT_HELPER_SIZE_ENV(maxu) + +DEF_IWMMXT_HELPER_SIZE_ENV(subn) +DEF_IWMMXT_HELPER_SIZE_ENV(addn) +DEF_IWMMXT_HELPER_SIZE_ENV(subu) +DEF_IWMMXT_HELPER_SIZE_ENV(addu) +DEF_IWMMXT_HELPER_SIZE_ENV(subs) +DEF_IWMMXT_HELPER_SIZE_ENV(adds) + +DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) +DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) + +DEF_HELPER_1(iwmmxt_bcstb, i64, i32) +DEF_HELPER_1(iwmmxt_bcstw, i64, i32) +DEF_HELPER_1(iwmmxt_bcstl, i64, i32) + +DEF_HELPER_1(iwmmxt_addcb, i64, i64) +DEF_HELPER_1(iwmmxt_addcw, i64, i64) +DEF_HELPER_1(iwmmxt_addcl, i64, i64) + +DEF_HELPER_1(iwmmxt_msbb, i32, i64) +DEF_HELPER_1(iwmmxt_msbw, i32, i64) +DEF_HELPER_1(iwmmxt_msbl, i32, i64) + +DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) + +DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) +DEF_HELPER_3(iwmmxt_muladdsw, i64, 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686473985861100002 In order to be able to move the iwmmxt-related code, fix its style to avoid: ERROR: braces {} are necessary for all arms of this statement ERROR: space prohibited before that '++' (ctx:WxB) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/translate.c | 227 +++++++++++++++++++++++-------------- 1 file changed, 141 insertions(+), 86 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 13c88ba1b9..3238463f13 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -1441,10 +1441,11 @@ static inline int gen_iwmmxt_address(DisasContext *= s, uint32_t insn, offset =3D (insn & 0xff) << ((insn >> 7) & 2); if (insn & (1 << 24)) { /* Pre indexed */ - if (insn & (1 << 23)) + if (insn & (1 << 23)) { tcg_gen_addi_i32(tmp, tmp, offset); - else + } else { tcg_gen_addi_i32(tmp, tmp, -offset); + } tcg_gen_mov_i32(dest, tmp); if (insn & (1 << 21)) { store_reg(s, rd, tmp); @@ -1452,13 +1453,15 @@ static inline int gen_iwmmxt_address(DisasContext *= s, uint32_t insn, } else if (insn & (1 << 21)) { /* Post indexed */ tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 23)) + if (insn & (1 << 23)) { tcg_gen_addi_i32(tmp, tmp, offset); - else + } else { tcg_gen_addi_i32(tmp, tmp, -offset); + } store_reg(s, rd, tmp); - } else if (!(insn & (1 << 23))) + } else if (!(insn & (1 << 23))) { return 1; + } return 0; } =20 @@ -1483,8 +1486,10 @@ static inline int gen_iwmmxt_shift(uint32_t insn, ui= nt32_t mask, TCGv_i32 dest) return 0; } =20 -/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred - (ie. an undefined instruction). */ +/* + * Disassemble an iwMMXt instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) { int rd, wrd; @@ -1570,8 +1575,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) return 0; } =20 - if ((insn & 0x0f000000) !=3D 0x0e000000) + if ((insn & 0x0f000000) !=3D 0x0e000000) { return 1; + } =20 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { case 0x000: /* WOR */ @@ -1586,8 +1592,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_op_iwmmxt_set_cup(); break; case 0x011: /* TMCR */ - if (insn & 0xf) + if (insn & 0xf) { return 1; + } rd =3D (insn >> 12) & 0xf; wrd =3D (insn >> 16) & 0xf; switch (wrd) { @@ -1627,8 +1634,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_op_iwmmxt_set_cup(); break; case 0x111: /* TMRC */ - if (insn & 0xf) + if (insn & 0xf) { return 1; + } rd =3D (insn >> 12) & 0xf; wrd =3D (insn >> 16) & 0xf; tmp =3D iwmmxt_load_creg(wrd); @@ -1662,10 +1670,11 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) rd0 =3D (insn >> 0) & 0xf; rd1 =3D (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maddsq_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_madduq_M0_wRn(rd1); + } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -1718,12 +1727,14 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) rd0 =3D (insn >> 16) & 0xf; rd1 =3D (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) + if (insn & (1 << 22)) { gen_op_iwmmxt_sadw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_sadb_M0_wRn(rd1); - if (!(insn & (1 << 20))) + } + if (!(insn & (1 << 20))) { gen_op_iwmmxt_addl_M0_wRn(wrd); + } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -1733,15 +1744,17 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) rd1 =3D (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); if (insn & (1 << 21)) { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_mulshw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_mulslw_M0_wRn(rd1); + } } else { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_muluhw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_mululw_M0_wRn(rd1); + } } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); @@ -1751,10 +1764,11 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) rd0 =3D (insn >> 16) & 0xf; rd1 =3D (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_macsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_macuw_M0_wRn(rd1); + } if (!(insn & (1 << 20))) { iwmmxt_load_reg(cpu_V1, wrd); tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); @@ -1790,15 +1804,17 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) rd1 =3D (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); if (insn & (1 << 22)) { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_avgw1_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_avgw0_M0_wRn(rd1); + } } else { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_avgb1_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_avgb0_M0_wRn(rd1); + } } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); @@ -1817,8 +1833,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_op_iwmmxt_set_mup(); break; case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ - if (((insn >> 6) & 3) =3D=3D 3) + if (((insn >> 6) & 3) =3D=3D 3) { return 1; + } rd =3D (insn >> 12) & 0xf; wrd =3D (insn >> 16) & 0xf; tmp =3D load_reg(s, rd); @@ -1846,8 +1863,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ rd =3D (insn >> 12) & 0xf; wrd =3D (insn >> 16) & 0xf; - if (rd =3D=3D 15 || ((insn >> 22) & 3) =3D=3D 3) + if (rd =3D=3D 15 || ((insn >> 22) & 3) =3D=3D 3) { return 1; + } gen_op_iwmmxt_movq_M0_wRn(wrd); tmp =3D tcg_temp_new_i32(); switch ((insn >> 22) & 3) { @@ -1877,8 +1895,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) store_reg(s, rd, tmp); break; case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ - if ((insn & 0x000ff008) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) + if ((insn & 0x000ff008) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { return 1; + } tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); switch ((insn >> 22) & 3) { case 0: @@ -1895,8 +1914,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_set_nzcv(tmp); break; case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ - if (((insn >> 6) & 3) =3D=3D 3) + if (((insn >> 6) & 3) =3D=3D 3) { return 1; + } rd =3D (insn >> 12) & 0xf; wrd =3D (insn >> 16) & 0xf; tmp =3D load_reg(s, rd); @@ -1915,20 +1935,21 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_set_mup(); break; case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ - if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) + if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { return 1; + } tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); tmp2 =3D tcg_temp_new_i32(); tcg_gen_mov_i32(tmp2, tmp); switch ((insn >> 22) & 3) { case 0: - for (i =3D 0; i < 7; i ++) { + for (i =3D 0; i < 7; i++) { tcg_gen_shli_i32(tmp2, tmp2, 4); tcg_gen_and_i32(tmp, tmp, tmp2); } break; case 1: - for (i =3D 0; i < 3; i ++) { + for (i =3D 0; i < 3; i++) { tcg_gen_shli_i32(tmp2, tmp2, 8); tcg_gen_and_i32(tmp, tmp, tmp2); } @@ -1961,20 +1982,21 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_set_mup(); break; case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ - if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) + if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { return 1; + } tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); tmp2 =3D tcg_temp_new_i32(); tcg_gen_mov_i32(tmp2, tmp); switch ((insn >> 22) & 3) { case 0: - for (i =3D 0; i < 7; i ++) { + for (i =3D 0; i < 7; i++) { tcg_gen_shli_i32(tmp2, tmp2, 4); tcg_gen_or_i32(tmp, tmp, tmp2); } break; case 1: - for (i =3D 0; i < 3; i ++) { + for (i =3D 0; i < 3; i++) { tcg_gen_shli_i32(tmp2, tmp2, 8); tcg_gen_or_i32(tmp, tmp, tmp2); } @@ -1989,8 +2011,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ rd =3D (insn >> 12) & 0xf; rd0 =3D (insn >> 16) & 0xf; - if ((insn & 0xf) !=3D 0 || ((insn >> 22) & 3) =3D=3D 3) + if ((insn & 0xf) !=3D 0 || ((insn >> 22) & 3) =3D=3D 3) { return 1; + } gen_op_iwmmxt_movq_M0_wRn(rd0); tmp =3D tcg_temp_new_i32(); switch ((insn >> 22) & 3) { @@ -2014,22 +2037,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); + } break; case 3: return 1; @@ -2045,22 +2071,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpacklsb_M0(); - else + } else { gen_op_iwmmxt_unpacklub_M0(); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpacklsw_M0(); - else + } else { gen_op_iwmmxt_unpackluw_M0(); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpacklsl_M0(); - else + } else { gen_op_iwmmxt_unpacklul_M0(); + } break; case 3: return 1; @@ -2076,22 +2105,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpackhsb_M0(); - else + } else { gen_op_iwmmxt_unpackhub_M0(); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpackhsw_M0(); - else + } else { gen_op_iwmmxt_unpackhuw_M0(); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpackhsl_M0(); - else + } else { gen_op_iwmmxt_unpackhul_M0(); + } break; case 3: return 1; @@ -2102,8 +2134,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) break; case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ case 0x214: case 0x614: case 0xa14: case 0xe14: - if (((insn >> 22) & 3) =3D=3D 0) + if (((insn >> 22) & 3) =3D=3D 0) { return 1; + } wrd =3D (insn >> 12) & 0xf; rd0 =3D (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2128,8 +2161,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) break; case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ case 0x014: case 0x414: case 0x814: case 0xc14: - if (((insn >> 22) & 3) =3D=3D 0) + if (((insn >> 22) & 3) =3D=3D 0) { return 1; + } wrd =3D (insn >> 12) & 0xf; rd0 =3D (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2154,8 +2188,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) break; case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ case 0x114: case 0x514: case 0x914: case 0xd14: - if (((insn >> 22) & 3) =3D=3D 0) + if (((insn >> 22) & 3) =3D=3D 0) { return 1; + } wrd =3D (insn >> 12) & 0xf; rd0 =3D (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2180,8 +2215,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) break; case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ case 0x314: case 0x714: case 0xb14: case 0xf14: - if (((insn >> 22) & 3) =3D=3D 0) + if (((insn >> 22) & 3) =3D=3D 0) { return 1; + } wrd =3D (insn >> 12) & 0xf; rd0 =3D (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2218,22 +2254,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_minsb_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_minub_M0_wRn(rd1); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_minsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_minuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_minsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_minul_M0_wRn(rd1); + } break; case 3: return 1; @@ -2249,22 +2288,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maxsb_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_maxub_M0_wRn(rd1); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maxsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_maxuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maxsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_maxul_M0_wRn(rd1); + } break; case 3: return 1; @@ -2387,30 +2429,34 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) case 0x408: case 0x508: case 0x608: case 0x708: case 0x808: case 0x908: case 0xa08: case 0xb08: case 0xc08: case 0xd08: case 0xe08: case 0xf08: - if (!(insn & (1 << 20)) || ((insn >> 22) & 3) =3D=3D 0) + if (!(insn & (1 << 20)) || ((insn >> 22) & 3) =3D=3D 0) { return 1; + } wrd =3D (insn >> 12) & 0xf; rd0 =3D (insn >> 16) & 0xf; rd1 =3D (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_packsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_packuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_packsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_packul_M0_wRn(rd1); + } break; case 3: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_packsq_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_packuq_M0_wRn(rd1); + } break; } gen_op_iwmmxt_movq_wRn_M0(wrd); @@ -2424,8 +2470,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) wrd =3D (insn >> 5) & 0xf; rd0 =3D (insn >> 12) & 0xf; rd1 =3D (insn >> 0) & 0xf; - if (rd0 =3D=3D 0xf || rd1 =3D=3D 0xf) + if (rd0 =3D=3D 0xf || rd1 =3D=3D 0xf) { return 1; + } gen_op_iwmmxt_movq_M0_wRn(wrd); tmp =3D load_reg(s, rd0); tmp2 =3D load_reg(s, rd1); @@ -2437,10 +2484,12 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); break; case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy = */ - if (insn & (1 << 16)) + if (insn & (1 << 16)) { tcg_gen_shri_i32(tmp, tmp, 16); - if (insn & (1 << 17)) + } + if (insn & (1 << 17)) { tcg_gen_shri_i32(tmp2, tmp2, 16); + } gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); break; default: @@ -2456,8 +2505,10 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32= _t insn) return 0; } =20 -/* Disassemble an XScale DSP instruction. Returns nonzero if an error occ= urred - (ie. an undefined instruction). */ +/* + * Disassemble an XScale DSP instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ static int disas_dsp_insn(DisasContext *s, uint32_t insn) { int acc, rd0, rd1, rdhi, rdlo; @@ -2469,8 +2520,9 @@ static int disas_dsp_insn(DisasContext *s, uint32_t i= nsn) rd1 =3D insn & 0xf; acc =3D (insn >> 5) & 7; =20 - if (acc !=3D 0) + if (acc !=3D 0) { return 1; + } =20 tmp =3D load_reg(s, rd0); tmp2 =3D load_reg(s, rd1); @@ -2485,10 +2537,12 @@ static int disas_dsp_insn(DisasContext *s, uint32_t= insn) case 0xd: /* MIABT */ case 0xe: /* MIATB */ case 0xf: /* MIATT */ - if (insn & (1 << 16)) + if (insn & (1 << 16)) { tcg_gen_shri_i32(tmp, tmp, 16); - if (insn & (1 << 17)) + } + if (insn & (1 << 17)) { tcg_gen_shri_i32(tmp2, tmp2, 16); + } gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); break; default: @@ -2505,8 +2559,9 @@ static int disas_dsp_insn(DisasContext *s, uint32_t i= nsn) rdlo =3D (insn >> 12) & 0xf; acc =3D insn & 7; =20 - if (acc !=3D 0) + if (acc !=3D 0) { return 1; + } =20 if (insn & ARM_CP_RW_BIT) { /* MRA */ iwmmxt_load_reg(cpu_V0, acc); --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474417; cv=none; d=zohomail.com; s=zohoarc; b=V6Dap+x8CwSWEuqSaGqxSdDEXAPI72r67tWaIteg7Gp8Z64QtH3n5VauMm0ApT+TCfpekFxRCzDVGZF+pt7pDALLsvXpTdWAlBuGfSXLdR45Sn9EeP+0WtolvySGu6DBRZFp1dR40B9+iZNNZZBpCu4KmFZ2QQBF6Amclk+QhiU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474417; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PL1Zih1O88caRvf7sSFHzFYcTBs6PNvq9qmGaaGGlCI=; b=HIsD5qYP21H9ARGTGySKUq94IE9isSF+flZzY1fcmlM9U8/h8shi07ZZQIyu/kY1CVe7xD+ywPZJMjTcXxoEJ76Vl4GrlfWWDk5vQ2v7ZE4Q78bBz/Ys70V3FoL3EJBAUfcIcj3iupoFZhbnjv6CN6Tf3W4L98ihN55olIuQZAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474417226133.98812694422554; Sun, 11 Jun 2023 02:06:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gv1-0001Hs-Oe; Sun, 11 Jun 2023 04:59:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Guw-0001B9-CB for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:22 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Guu-0003dA-Lf for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:22 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-30ae61354fbso2112367f8f.3 for ; Sun, 11 Jun 2023 01:59:20 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id b5-20020adff905000000b0030aedb8156esm8998995wrr.102.2023.06.11.01.59.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473959; x=1689065959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PL1Zih1O88caRvf7sSFHzFYcTBs6PNvq9qmGaaGGlCI=; b=NdbJcpQTWNeNzxUJzNMqzfziVot6wUUXbgri+Zk8hF+ibBKv7X5zt+H/qIXtMuSOOv keRxjnlEZHbBys8qFKfytZBhrXZ5f9S/ZMaxMWlzHPHhYP8n6fY+MTvnNSzsiNGm5sT2 C5ZhjD3pP4kk4f+DtsH2UHMcBxWdFHEpHYmSQpISesoIqNL5ZKM5fRRBn4a6okHXf81d r1DwuGryrHkNmkkdupHqcHHBO6QB3DjyBDZo2fiYJsRRepNT/dKFtpb8NjiXsqEy4uLl jILkr5osaB3ok2Wji9tUOYjhYfnhLDbrL6hEQJt4rcNpFejQ1DqxREpDy7MilQowDHgF 57uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473959; x=1689065959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PL1Zih1O88caRvf7sSFHzFYcTBs6PNvq9qmGaaGGlCI=; b=QGo47h9IF6ynOXOP4Y/vkO+9XXktGQGkW1wuF0BjSNOMAzhKoORToA4GNw42cR+ZUp nVAPlgwlwIbExvNJxAtPwxK3RQoWdfd6t1WAZK82N404vgpXq40rcP9MipKPrrCejJy5 JAB95JcodP4zpc4f7EVj4OWEpZLxbep7dJXJqMMzRhXlKLw/NCTGT6s2jyVMG0IRKF0x E6/xSK1FpsP/9hfwMExQAVacFFANxxSxlCEEu1noOcz4og2+3pJ0x1MAdkgUWHB1Myq8 DrUsb7Iv4OOwHBxKmZfc6R6bwYM8R+4ZwBfzymgMBkEhZQChatW8nJEom5OCVi/6Mqui EPGw== X-Gm-Message-State: AC+VfDx3YeJ2rVnS8aQH5UE2lNS9LFUxBy75zwGhrSRQ5u/xZgMwwVxH 3ADNpRqj6au/cBlFmFYsCz5wrbXa55QCzuPx95I= X-Google-Smtp-Source: ACHHUZ7JcG2adSN6O9eCCOcted4zyrvQmu36Z7AMJH27kiAqNVR2L2Gwra0QFxZmPfDrzdzs/B/J6w== X-Received: by 2002:adf:dd07:0:b0:30f:bf01:b62a with SMTP id a7-20020adfdd07000000b0030fbf01b62amr495722wrm.24.1686473959060; Sun, 11 Jun 2023 01:59:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/26] target/arm/tcg: Expose some iwmmxt methods in 'translate.h' Date: Sun, 11 Jun 2023 10:58:27 +0200 Message-Id: <20230611085846.21415-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474418868100005 Expose a few methods and variables before extracting iwmmxt code from translate.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/translate.h | 6 ++++++ target/arm/tcg/translate.c | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d1cacff0b2..3d7c55d3b6 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -165,6 +165,7 @@ typedef struct DisasCompare { } DisasCompare; =20 /* Share the TCG temporaries common between 32 and 64 bit modes. */ +extern TCGv_i32 cpu_R[16]; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; @@ -298,6 +299,11 @@ static inline int curr_insn_len(DisasContext *s) /* CPU state was modified dynamically; no need to exit, but do not chain. = */ #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 =20 +/* These are TCG temporaries used only by the legacy iwMMXt decoder */ +extern TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn); +int disas_dsp_insn(DisasContext *s, uint32_t insn); + #ifdef TARGET_AARCH64 void a64_translate_init(void); void gen_a64_update_pc(DisasContext *s, target_long diff); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3238463f13..aaa479521e 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -45,9 +45,9 @@ #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) =20 /* These are TCG temporaries used only by the legacy iwMMXt decoder */ -static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ -static TCGv_i32 cpu_R[16]; +TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; @@ -1490,7 +1490,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uin= t32_t mask, TCGv_i32 dest) * Disassemble an iwMMXt instruction. * Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) { int rd, wrd; int rdhi, rdlo, rd0, rd1, i; @@ -2509,7 +2509,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) * Disassemble an XScale DSP instruction. * Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_dsp_insn(DisasContext *s, uint32_t insn) +int disas_dsp_insn(DisasContext *s, uint32_t insn) { int acc, rd0, rd1, rdhi, rdlo; TCGv_i32 tmp, tmp2; --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474348; cv=none; d=zohomail.com; s=zohoarc; b=SxSXcyB5WZZAY9d0BNCJ1bI3YD/ReOqZpMTZoWZl1wNbXbg2QBiHlM0c0HPG2+aLqR6sPo2D5jXV1VJY/7zLBixBzF7aDlbh+7tXPQxIPa5pCWHwLisZbTkOFl/B+n524rfHAJvOzogyc3ZjiNOld9zhQc0zLLl4rtsD5H4iuyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474348; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oMLss41euDQaVYpSruIudxIhxmIApSvQmPEdVJISz5I=; b=Q6u9djKLJtTv+HjWAr/u4EBVNOHm6ObiMaTbe4toRNwaj3zM+j8Y74k/3KFnFJTXOyTtNySodBJ2Ekbw1ON0UHfQc5NfgvtQsCQSQabYHsGjWak71KSmsz8kGEy+vVLhJHZ6RbsUXYylVWCXcvD9m/H1P+QywvTpWxgAm0KrUgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474348143528.883043233411; Sun, 11 Jun 2023 02:05:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gv6-0001cJ-QI; Sun, 11 Jun 2023 04:59:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gv4-0001UV-RS for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:30 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gv0-0003eJ-EK for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:30 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-30e56fc9fd2so3125345f8f.0 for ; Sun, 11 Jun 2023 01:59:26 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id f13-20020a056000036d00b0030aefa3a957sm9092135wrf.28.2023.06.11.01.59.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473965; x=1689065965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oMLss41euDQaVYpSruIudxIhxmIApSvQmPEdVJISz5I=; b=O5p/l2P015iyVESGgumoSuK6yuKZsZFUGZDHkYQQgO83a+jHPnridmapRaqq34JJe3 FtsjMZqmBW5/+Mx4JKh+GFKOsUaFogG1WEIDLPSopfUuWB6J8zUrFgi2lkhPt2o68C0S qs7sBBm5Nwsrmelur9IA3tkUwtsXxkmHsath44H24XLYJ/dLyazhrXoLBYjRCHt+7sXb 4RQmPlBKwl8hN8k/zPNgTAdNNoTpz3f1eSeY2zCrNWSx4OHB8ig9Z1E1rQsT0s/lsw1p adNm3qkuDQYsEKO0zcwNFan8xskdyYLqoFJwezPkXY5QvUwaeAPajbRxyj7tvOZUtm6V H5+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473965; x=1689065965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oMLss41euDQaVYpSruIudxIhxmIApSvQmPEdVJISz5I=; b=TDExKZF46Yc0BPUDUeSSUb+dHJoPpsfaupTTa68q7nmlZUkHc431hj+OzZus33t+jE kF7btw42PQq0ItXwd96XOKytUW+6FBVb7Jn7r//mhL7ELHa9UlqtD577ki0Ul4L0kYjk nuxIRrpxsSTJ4jfYuObPdCektPVY4MltcTRhk2w15nxBoD6ccgUmRj7fLYyk1dvtYvHI oYN9dFEhKlqHJ1c9n7KdKVkWxkw9HSZcFDCin3BxoI17HHaVL2oEj9v1fqL+rot738wk b+IaCrvOwNjoXxQrtEd+dOmV69a/oz9ONvpTp1m+hDGPhaJ1cYnUP0oi4EpnxVhs82Po rT1w== X-Gm-Message-State: AC+VfDzWzXa5usJZxwr4yiLs8iFkO4DLvLJr/bnXigHU1+hPJc2s7Psn Kk2dA5bjOYaxObcdE6Z65yZfHcHfNE5Z6B2fOas= X-Google-Smtp-Source: ACHHUZ7tJPcfqy/yJzET7qrwEf2V66miz4gTf9K4+uYYZDj9J5iD4UfLz+ngpdTY3uqNq+c2BQELow== X-Received: by 2002:a5d:6281:0:b0:30f:b7be:4089 with SMTP id k1-20020a5d6281000000b0030fb7be4089mr2126904wru.3.1686473963413; Sun, 11 Jun 2023 01:59:23 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/26] target/arm/tcg: Extract iwmmxt code to translate-iwmmxt.c Date: Sun, 11 Jun 2023 10:58:28 +0200 Message-Id: <20230611085846.21415-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474349909100007 Extract 1300 lines from the big enough translate.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate-iwmmxt.c | 1325 +++++++++++++++++++++++++++++ target/arm/tcg/translate.c | 1312 ---------------------------- target/arm/tcg/meson.build | 1 + 3 files changed, 1326 insertions(+), 1312 deletions(-) create mode 100644 target/arm/tcg/translate-iwmmxt.c diff --git a/target/arm/tcg/translate-iwmmxt.c b/target/arm/tcg/translate-i= wmmxt.c new file mode 100644 index 0000000000..57a924c578 --- /dev/null +++ b/target/arm/tcg/translate-iwmmxt.c @@ -0,0 +1,1325 @@ +/* + * XScale iwMMXt translation + * + * Copyright (c) 2007 OpenedHand, Ltd. + * Written by Andrzej Zaborowski + * Copyright (c) 2008 CodeSourcery + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" +#include "translate-a32.h" + +#define ARM_CP_RW_BIT (1 << 20) + +static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) +{ + tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); +} + +static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) +{ + tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); +} + +static inline TCGv_i32 iwmmxt_load_creg(int reg) +{ + TCGv_i32 var =3D tcg_temp_new_i32(); + tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); + return var; +} + +static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) +{ + tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); +} + +static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) +{ + iwmmxt_store_reg(cpu_M0, rn); +} + +static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_M0, rn); +} + +static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); +} + +static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); +} + +static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); +} + +#define IWMMXT_OP(name) \ +static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ +{ \ + iwmmxt_load_reg(cpu_V1, rn); \ + gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ +} + +#define IWMMXT_OP_ENV(name) \ +static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ +{ \ + iwmmxt_load_reg(cpu_V1, rn); \ + gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ +} + +#define IWMMXT_OP_ENV_SIZE(name) \ +IWMMXT_OP_ENV(name##b) \ +IWMMXT_OP_ENV(name##w) \ +IWMMXT_OP_ENV(name##l) + +#define IWMMXT_OP_ENV1(name) \ +static inline void gen_op_iwmmxt_##name##_M0(void) \ +{ \ + gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ +} + +IWMMXT_OP(maddsq) +IWMMXT_OP(madduq) +IWMMXT_OP(sadb) +IWMMXT_OP(sadw) +IWMMXT_OP(mulslw) +IWMMXT_OP(mulshw) +IWMMXT_OP(mululw) +IWMMXT_OP(muluhw) +IWMMXT_OP(macsw) +IWMMXT_OP(macuw) + +IWMMXT_OP_ENV_SIZE(unpackl) +IWMMXT_OP_ENV_SIZE(unpackh) + +IWMMXT_OP_ENV1(unpacklub) +IWMMXT_OP_ENV1(unpackluw) +IWMMXT_OP_ENV1(unpacklul) +IWMMXT_OP_ENV1(unpackhub) +IWMMXT_OP_ENV1(unpackhuw) +IWMMXT_OP_ENV1(unpackhul) +IWMMXT_OP_ENV1(unpacklsb) +IWMMXT_OP_ENV1(unpacklsw) +IWMMXT_OP_ENV1(unpacklsl) +IWMMXT_OP_ENV1(unpackhsb) +IWMMXT_OP_ENV1(unpackhsw) +IWMMXT_OP_ENV1(unpackhsl) + +IWMMXT_OP_ENV_SIZE(cmpeq) +IWMMXT_OP_ENV_SIZE(cmpgtu) +IWMMXT_OP_ENV_SIZE(cmpgts) + +IWMMXT_OP_ENV_SIZE(mins) +IWMMXT_OP_ENV_SIZE(minu) +IWMMXT_OP_ENV_SIZE(maxs) +IWMMXT_OP_ENV_SIZE(maxu) + +IWMMXT_OP_ENV_SIZE(subn) +IWMMXT_OP_ENV_SIZE(addn) +IWMMXT_OP_ENV_SIZE(subu) +IWMMXT_OP_ENV_SIZE(addu) +IWMMXT_OP_ENV_SIZE(subs) +IWMMXT_OP_ENV_SIZE(adds) + +IWMMXT_OP_ENV(avgb0) +IWMMXT_OP_ENV(avgb1) +IWMMXT_OP_ENV(avgw0) +IWMMXT_OP_ENV(avgw1) + +IWMMXT_OP_ENV(packuw) +IWMMXT_OP_ENV(packul) +IWMMXT_OP_ENV(packuq) +IWMMXT_OP_ENV(packsw) +IWMMXT_OP_ENV(packsl) +IWMMXT_OP_ENV(packsq) + +static void gen_op_iwmmxt_set_mup(void) +{ + TCGv_i32 tmp; + tmp =3D load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); + tcg_gen_ori_i32(tmp, tmp, 2); + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); +} + +static void gen_op_iwmmxt_set_cup(void) +{ + TCGv_i32 tmp; + tmp =3D load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); + tcg_gen_ori_i32(tmp, tmp, 1); + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); +} + +static void gen_op_iwmmxt_setpsr_nz(void) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); +} + +static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_ext32u_i64(cpu_V1, cpu_V1); + tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); +} + +static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, + TCGv_i32 dest) +{ + int rd; + uint32_t offset; + TCGv_i32 tmp; + + rd =3D (insn >> 16) & 0xf; + tmp =3D load_reg(s, rd); + + offset =3D (insn & 0xff) << ((insn >> 7) & 2); + if (insn & (1 << 24)) { + /* Pre indexed */ + if (insn & (1 << 23)) { + tcg_gen_addi_i32(tmp, tmp, offset); + } else { + tcg_gen_addi_i32(tmp, tmp, -offset); + } + tcg_gen_mov_i32(dest, tmp); + if (insn & (1 << 21)) { + store_reg(s, rd, tmp); + } + } else if (insn & (1 << 21)) { + /* Post indexed */ + tcg_gen_mov_i32(dest, tmp); + if (insn & (1 << 23)) { + tcg_gen_addi_i32(tmp, tmp, offset); + } else { + tcg_gen_addi_i32(tmp, tmp, -offset); + } + store_reg(s, rd, tmp); + } else if (!(insn & (1 << 23))) { + return 1; + } + return 0; +} + +static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 = dest) +{ + int rd =3D (insn >> 0) & 0xf; + TCGv_i32 tmp; + + if (insn & (1 << 8)) { + if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) { + return 1; + } else { + tmp =3D iwmmxt_load_creg(rd); + } + } else { + tmp =3D tcg_temp_new_i32(); + iwmmxt_load_reg(cpu_V0, rd); + tcg_gen_extrl_i64_i32(tmp, cpu_V0); + } + tcg_gen_andi_i32(tmp, tmp, mask); + tcg_gen_mov_i32(dest, tmp); + return 0; +} + +/* + * Disassemble an iwMMXt instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) +{ + int rd, wrd; + int rdhi, rdlo, rd0, rd1, i; + TCGv_i32 addr; + TCGv_i32 tmp, tmp2, tmp3; + + if ((insn & 0x0e000e00) =3D=3D 0x0c000000) { + if ((insn & 0x0fe00ff0) =3D=3D 0x0c400000) { + wrd =3D insn & 0xf; + rdlo =3D (insn >> 12) & 0xf; + rdhi =3D (insn >> 16) & 0xf; + if (insn & ARM_CP_RW_BIT) { /* TMRRC */ + iwmmxt_load_reg(cpu_V0, wrd); + tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); + tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); + } else { /* TMCRR */ + tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); + iwmmxt_store_reg(cpu_V0, wrd); + gen_op_iwmmxt_set_mup(); + } + return 0; + } + + wrd =3D (insn >> 12) & 0xf; + addr =3D tcg_temp_new_i32(); + if (gen_iwmmxt_address(s, insn, addr)) { + return 1; + } + if (insn & ARM_CP_RW_BIT) { + if ((insn >> 28) =3D=3D 0xf) { /* WLDRW wCx */ + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + iwmmxt_store_creg(wrd, tmp); + } else { + i =3D 1; + if (insn & (1 << 8)) { + if (insn & (1 << 22)) { /* WLDRD */ + gen_aa32_ld64(s, cpu_M0, addr, get_mem_index(s)); + i =3D 0; + } else { /* WLDRW wRd */ + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + } + } else { + tmp =3D tcg_temp_new_i32(); + if (insn & (1 << 22)) { /* WLDRH */ + gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + } else { /* WLDRB */ + gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); + } + } + if (i) { + tcg_gen_extu_i32_i64(cpu_M0, tmp); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + } + } else { + if ((insn >> 28) =3D=3D 0xf) { /* WSTRW wCx */ + tmp =3D iwmmxt_load_creg(wrd); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + } else { + gen_op_iwmmxt_movq_M0_wRn(wrd); + tmp =3D tcg_temp_new_i32(); + if (insn & (1 << 8)) { + if (insn & (1 << 22)) { /* WSTRD */ + gen_aa32_st64(s, cpu_M0, addr, get_mem_index(s)); + } else { /* WSTRW wRd */ + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + } + } else { + if (insn & (1 << 22)) { /* WSTRH */ + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + } else { /* WSTRB */ + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + } + } + } + } + return 0; + } + + if ((insn & 0x0f000000) !=3D 0x0e000000) { + return 1; + } + + switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { + case 0x000: /* WOR */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 0) & 0xf; + rd1 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + gen_op_iwmmxt_orq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x011: /* TMCR */ + if (insn & 0xf) { + return 1; + } + rd =3D (insn >> 12) & 0xf; + wrd =3D (insn >> 16) & 0xf; + switch (wrd) { + case ARM_IWMMXT_wCID: + case ARM_IWMMXT_wCASF: + break; + case ARM_IWMMXT_wCon: + gen_op_iwmmxt_set_cup(); + /* Fall through. */ + case ARM_IWMMXT_wCSSF: + tmp =3D iwmmxt_load_creg(wrd); + tmp2 =3D load_reg(s, rd); + tcg_gen_andc_i32(tmp, tmp, tmp2); + iwmmxt_store_creg(wrd, tmp); + break; + case ARM_IWMMXT_wCGR0: + case ARM_IWMMXT_wCGR1: + case ARM_IWMMXT_wCGR2: + case ARM_IWMMXT_wCGR3: + gen_op_iwmmxt_set_cup(); + tmp =3D load_reg(s, rd); + iwmmxt_store_creg(wrd, tmp); + break; + default: + return 1; + } + break; + case 0x100: /* WXOR */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 0) & 0xf; + rd1 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + gen_op_iwmmxt_xorq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x111: /* TMRC */ + if (insn & 0xf) { + return 1; + } + rd =3D (insn >> 12) & 0xf; + wrd =3D (insn >> 16) & 0xf; + tmp =3D iwmmxt_load_creg(wrd); + store_reg(s, rd, tmp); + break; + case 0x300: /* WANDN */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 0) & 0xf; + rd1 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tcg_gen_neg_i64(cpu_M0, cpu_M0); + gen_op_iwmmxt_andq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x200: /* WAND */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 0) & 0xf; + rd1 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + gen_op_iwmmxt_andq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x810: case 0xa10: /* WMADD */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 0) & 0xf; + rd1 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 21)) { + gen_op_iwmmxt_maddsq_M0_wRn(rd1); + } else { + gen_op_iwmmxt_madduq_M0_wRn(rd1); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_op_iwmmxt_unpacklb_M0_wRn(rd1); + break; + case 1: + gen_op_iwmmxt_unpacklw_M0_wRn(rd1); + break; + case 2: + gen_op_iwmmxt_unpackll_M0_wRn(rd1); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_op_iwmmxt_unpackhb_M0_wRn(rd1); + break; + case 1: + gen_op_iwmmxt_unpackhw_M0_wRn(rd1); + break; + case 2: + gen_op_iwmmxt_unpackhl_M0_wRn(rd1); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 22)) { + gen_op_iwmmxt_sadw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_sadb_M0_wRn(rd1); + } + if (!(insn & (1 << 20))) { + gen_op_iwmmxt_addl_M0_wRn(wrd); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 21)) { + if (insn & (1 << 20)) { + gen_op_iwmmxt_mulshw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_mulslw_M0_wRn(rd1); + } + } else { + if (insn & (1 << 20)) { + gen_op_iwmmxt_muluhw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_mululw_M0_wRn(rd1); + } + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 21)) { + gen_op_iwmmxt_macsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_macuw_M0_wRn(rd1); + } + if (!(insn & (1 << 20))) { + iwmmxt_load_reg(cpu_V1, wrd); + tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); + break; + case 1: + gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); + break; + case 2: + gen_op_iwmmxt_cmpeql_M0_wRn(rd1); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 22)) { + if (insn & (1 << 20)) { + gen_op_iwmmxt_avgw1_M0_wRn(rd1); + } else { + gen_op_iwmmxt_avgw0_M0_wRn(rd1); + } + } else { + if (insn & (1 << 20)) { + gen_op_iwmmxt_avgb1_M0_wRn(rd1); + } else { + gen_op_iwmmxt_avgb0_M0_wRn(rd1); + } + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); + tcg_gen_andi_i32(tmp, tmp, 7); + iwmmxt_load_reg(cpu_V1, rd1); + gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ + if (((insn >> 6) & 3) =3D=3D 3) { + return 1; + } + rd =3D (insn >> 12) & 0xf; + wrd =3D (insn >> 16) & 0xf; + tmp =3D load_reg(s, rd); + gen_op_iwmmxt_movq_M0_wRn(wrd); + switch ((insn >> 6) & 3) { + case 0: + tmp2 =3D tcg_constant_i32(0xff); + tmp3 =3D tcg_constant_i32((insn & 7) << 3); + break; + case 1: + tmp2 =3D tcg_constant_i32(0xffff); + tmp3 =3D tcg_constant_i32((insn & 3) << 4); + break; + case 2: + tmp2 =3D tcg_constant_i32(0xffffffff); + tmp3 =3D tcg_constant_i32((insn & 1) << 5); + break; + default: + g_assert_not_reached(); + } + gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ + rd =3D (insn >> 12) & 0xf; + wrd =3D (insn >> 16) & 0xf; + if (rd =3D=3D 15 || ((insn >> 22) & 3) =3D=3D 3) { + return 1; + } + gen_op_iwmmxt_movq_M0_wRn(wrd); + tmp =3D tcg_temp_new_i32(); + switch ((insn >> 22) & 3) { + case 0: + tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3); + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + if (insn & 8) { + tcg_gen_ext8s_i32(tmp, tmp); + } else { + tcg_gen_andi_i32(tmp, tmp, 0xff); + } + break; + case 1: + tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4); + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + if (insn & 8) { + tcg_gen_ext16s_i32(tmp, tmp); + } else { + tcg_gen_andi_i32(tmp, tmp, 0xffff); + } + break; + case 2: + tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5); + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + break; + } + store_reg(s, rd, tmp); + break; + case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ + if ((insn & 0x000ff008) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { + return 1; + } + tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); + switch ((insn >> 22) & 3) { + case 0: + tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); + break; + case 1: + tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4); + break; + case 2: + tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12); + break; + } + tcg_gen_shli_i32(tmp, tmp, 28); + gen_set_nzcv(tmp); + break; + case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ + if (((insn >> 6) & 3) =3D=3D 3) { + return 1; + } + rd =3D (insn >> 12) & 0xf; + wrd =3D (insn >> 16) & 0xf; + tmp =3D load_reg(s, rd); + switch ((insn >> 6) & 3) { + case 0: + gen_helper_iwmmxt_bcstb(cpu_M0, tmp); + break; + case 1: + gen_helper_iwmmxt_bcstw(cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_bcstl(cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ + if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { + return 1; + } + tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); + tmp2 =3D tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp2, tmp); + switch ((insn >> 22) & 3) { + case 0: + for (i =3D 0; i < 7; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 4); + tcg_gen_and_i32(tmp, tmp, tmp2); + } + break; + case 1: + for (i =3D 0; i < 3; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 8); + tcg_gen_and_i32(tmp, tmp, tmp2); + } + break; + case 2: + tcg_gen_shli_i32(tmp2, tmp2, 16); + tcg_gen_and_i32(tmp, tmp, tmp2); + break; + } + gen_set_nzcv(tmp); + break; + case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); + break; + case 1: + gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); + break; + case 2: + gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ + if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { + return 1; + } + tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); + tmp2 =3D tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp2, tmp); + switch ((insn >> 22) & 3) { + case 0: + for (i =3D 0; i < 7; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 4); + tcg_gen_or_i32(tmp, tmp, tmp2); + } + break; + case 1: + for (i =3D 0; i < 3; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 8); + tcg_gen_or_i32(tmp, tmp, tmp2); + } + break; + case 2: + tcg_gen_shli_i32(tmp2, tmp2, 16); + tcg_gen_or_i32(tmp, tmp, tmp2); + break; + } + gen_set_nzcv(tmp); + break; + case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ + rd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + if ((insn & 0xf) !=3D 0 || ((insn >> 22) & 3) =3D=3D 3) { + return 1; + } + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp =3D tcg_temp_new_i32(); + switch ((insn >> 22) & 3) { + case 0: + gen_helper_iwmmxt_msbb(tmp, cpu_M0); + break; + case 1: + gen_helper_iwmmxt_msbw(tmp, cpu_M0); + break; + case 2: + gen_helper_iwmmxt_msbl(tmp, cpu_M0); + break; + } + store_reg(s, rd, tmp); + break; + case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ + case 0x906: case 0xb06: case 0xd06: case 0xf06: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); + } else { + gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ + case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpacklsb_M0(); + } else { + gen_op_iwmmxt_unpacklub_M0(); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpacklsw_M0(); + } else { + gen_op_iwmmxt_unpackluw_M0(); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpacklsl_M0(); + } else { + gen_op_iwmmxt_unpacklul_M0(); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ + case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpackhsb_M0(); + } else { + gen_op_iwmmxt_unpackhub_M0(); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpackhsw_M0(); + } else { + gen_op_iwmmxt_unpackhuw_M0(); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpackhsl_M0(); + } else { + gen_op_iwmmxt_unpackhul_M0(); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ + case 0x214: case 0x614: case 0xa14: case 0xe14: + if (((insn >> 22) & 3) =3D=3D 0) { + return 1; + } + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp =3D tcg_temp_new_i32(); + if (gen_iwmmxt_shift(insn, 0xff, tmp)) { + return 1; + } + switch ((insn >> 22) & 3) { + case 1: + gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ + case 0x014: case 0x414: case 0x814: case 0xc14: + if (((insn >> 22) & 3) =3D=3D 0) { + return 1; + } + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp =3D tcg_temp_new_i32(); + if (gen_iwmmxt_shift(insn, 0xff, tmp)) { + return 1; + } + switch ((insn >> 22) & 3) { + case 1: + gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ + case 0x114: case 0x514: case 0x914: case 0xd14: + if (((insn >> 22) & 3) =3D=3D 0) { + return 1; + } + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp =3D tcg_temp_new_i32(); + if (gen_iwmmxt_shift(insn, 0xff, tmp)) { + return 1; + } + switch ((insn >> 22) & 3) { + case 1: + gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ + case 0x314: case 0x714: case 0xb14: case 0xf14: + if (((insn >> 22) & 3) =3D=3D 0) { + return 1; + } + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp =3D tcg_temp_new_i32(); + switch ((insn >> 22) & 3) { + case 1: + if (gen_iwmmxt_shift(insn, 0xf, tmp)) { + return 1; + } + gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { + return 1; + } + gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { + return 1; + } + gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ + case 0x916: case 0xb16: case 0xd16: case 0xf16: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_minsb_M0_wRn(rd1); + } else { + gen_op_iwmmxt_minub_M0_wRn(rd1); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_minsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_minuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_minsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_minul_M0_wRn(rd1); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ + case 0x816: case 0xa16: case 0xc16: case 0xe16: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_maxsb_M0_wRn(rd1); + } else { + gen_op_iwmmxt_maxub_M0_wRn(rd1); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_maxsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_maxuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_maxsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_maxul_M0_wRn(rd1); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ + case 0x402: case 0x502: case 0x602: case 0x702: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + iwmmxt_load_reg(cpu_V1, rd1); + gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, + tcg_constant_i32((insn >> 20) & 3)); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ + case 0x41a: case 0x51a: case 0x61a: case 0x71a: + case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: + case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 20) & 0xf) { + case 0x0: + gen_op_iwmmxt_subnb_M0_wRn(rd1); + break; + case 0x1: + gen_op_iwmmxt_subub_M0_wRn(rd1); + break; + case 0x3: + gen_op_iwmmxt_subsb_M0_wRn(rd1); + break; + case 0x4: + gen_op_iwmmxt_subnw_M0_wRn(rd1); + break; + case 0x5: + gen_op_iwmmxt_subuw_M0_wRn(rd1); + break; + case 0x7: + gen_op_iwmmxt_subsw_M0_wRn(rd1); + break; + case 0x8: + gen_op_iwmmxt_subnl_M0_wRn(rd1); + break; + case 0x9: + gen_op_iwmmxt_subul_M0_wRn(rd1); + break; + case 0xb: + gen_op_iwmmxt_subsl_M0_wRn(rd1); + break; + default: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ + case 0x41e: case 0x51e: case 0x61e: case 0x71e: + case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: + case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp =3D tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); + gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ + case 0x418: case 0x518: case 0x618: case 0x718: + case 0x818: case 0x918: case 0xa18: case 0xb18: + case 0xc18: case 0xd18: case 0xe18: case 0xf18: + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 20) & 0xf) { + case 0x0: + gen_op_iwmmxt_addnb_M0_wRn(rd1); + break; + case 0x1: + gen_op_iwmmxt_addub_M0_wRn(rd1); + break; + case 0x3: + gen_op_iwmmxt_addsb_M0_wRn(rd1); + break; + case 0x4: + gen_op_iwmmxt_addnw_M0_wRn(rd1); + break; + case 0x5: + gen_op_iwmmxt_adduw_M0_wRn(rd1); + break; + case 0x7: + gen_op_iwmmxt_addsw_M0_wRn(rd1); + break; + case 0x8: + gen_op_iwmmxt_addnl_M0_wRn(rd1); + break; + case 0x9: + gen_op_iwmmxt_addul_M0_wRn(rd1); + break; + case 0xb: + gen_op_iwmmxt_addsl_M0_wRn(rd1); + break; + default: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ + case 0x408: case 0x508: case 0x608: case 0x708: + case 0x808: case 0x908: case 0xa08: case 0xb08: + case 0xc08: case 0xd08: case 0xe08: case 0xf08: + if (!(insn & (1 << 20)) || ((insn >> 22) & 3) =3D=3D 0) { + return 1; + } + wrd =3D (insn >> 12) & 0xf; + rd0 =3D (insn >> 16) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_packsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_packuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_packsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_packul_M0_wRn(rd1); + } + break; + case 3: + if (insn & (1 << 21)) { + gen_op_iwmmxt_packsq_M0_wRn(rd1); + } else { + gen_op_iwmmxt_packuq_M0_wRn(rd1); + } + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x201: case 0x203: case 0x205: case 0x207: + case 0x209: case 0x20b: case 0x20d: case 0x20f: + case 0x211: case 0x213: case 0x215: case 0x217: + case 0x219: case 0x21b: case 0x21d: case 0x21f: + wrd =3D (insn >> 5) & 0xf; + rd0 =3D (insn >> 12) & 0xf; + rd1 =3D (insn >> 0) & 0xf; + if (rd0 =3D=3D 0xf || rd1 =3D=3D 0xf) { + return 1; + } + gen_op_iwmmxt_movq_M0_wRn(wrd); + tmp =3D load_reg(s, rd0); + tmp2 =3D load_reg(s, rd1); + switch ((insn >> 16) & 0xf) { + case 0x0: /* TMIA */ + gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0x8: /* TMIAPH */ + gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy = */ + if (insn & (1 << 16)) { + tcg_gen_shri_i32(tmp, tmp, 16); + } + if (insn & (1 << 17)) { + tcg_gen_shri_i32(tmp2, tmp2, 16); + } + gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); + break; + default: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + default: + return 1; + } + + return 0; +} + +/* + * Disassemble an XScale DSP instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ +int disas_dsp_insn(DisasContext *s, uint32_t insn) +{ + int acc, rd0, rd1, rdhi, rdlo; + TCGv_i32 tmp, tmp2; + + if ((insn & 0x0ff00f10) =3D=3D 0x0e200010) { + /* Multiply with Internal Accumulate Format */ + rd0 =3D (insn >> 12) & 0xf; + rd1 =3D insn & 0xf; + acc =3D (insn >> 5) & 7; + + if (acc !=3D 0) { + return 1; + } + + tmp =3D load_reg(s, rd0); + tmp2 =3D load_reg(s, rd1); + switch ((insn >> 16) & 0xf) { + case 0x0: /* MIA */ + gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0x8: /* MIAPH */ + gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0xc: /* MIABB */ + case 0xd: /* MIABT */ + case 0xe: /* MIATB */ + case 0xf: /* MIATT */ + if (insn & (1 << 16)) { + tcg_gen_shri_i32(tmp, tmp, 16); + } + if (insn & (1 << 17)) { + tcg_gen_shri_i32(tmp2, tmp2, 16); + } + gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); + break; + default: + return 1; + } + + gen_op_iwmmxt_movq_wRn_M0(acc); + return 0; + } + + if ((insn & 0x0fe00ff8) =3D=3D 0x0c400000) { + /* Internal Accumulator Access Format */ + rdhi =3D (insn >> 16) & 0xf; + rdlo =3D (insn >> 12) & 0xf; + acc =3D insn & 7; + + if (acc !=3D 0) { + return 1; + } + + if (insn & ARM_CP_RW_BIT) { /* MRA */ + iwmmxt_load_reg(cpu_V0, acc); + tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); + tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); + tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - = 1); + } else { /* MAR */ + tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); + iwmmxt_store_reg(cpu_V0, acc); + } + return 0; + } + + return 1; +} diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index aaa479521e..a352fced6e 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -1266,1318 +1266,6 @@ void write_neon_element64(TCGv_i64 src, int reg, i= nt ele, MemOp memop) } } =20 -#define ARM_CP_RW_BIT (1 << 20) - -static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) -{ - tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); -} - -static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) -{ - tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); -} - -static inline TCGv_i32 iwmmxt_load_creg(int reg) -{ - TCGv_i32 var =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); - return var; -} - -static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) -{ - tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); -} - -static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) -{ - iwmmxt_store_reg(cpu_M0, rn); -} - -static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_M0, rn); -} - -static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); -} - -#define IWMMXT_OP(name) \ -static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ -{ \ - iwmmxt_load_reg(cpu_V1, rn); \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ -} - -#define IWMMXT_OP_ENV(name) \ -static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ -{ \ - iwmmxt_load_reg(cpu_V1, rn); \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ -} - -#define IWMMXT_OP_ENV_SIZE(name) \ -IWMMXT_OP_ENV(name##b) \ -IWMMXT_OP_ENV(name##w) \ -IWMMXT_OP_ENV(name##l) - -#define IWMMXT_OP_ENV1(name) \ -static inline void gen_op_iwmmxt_##name##_M0(void) \ -{ \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ -} - -IWMMXT_OP(maddsq) -IWMMXT_OP(madduq) -IWMMXT_OP(sadb) -IWMMXT_OP(sadw) -IWMMXT_OP(mulslw) -IWMMXT_OP(mulshw) -IWMMXT_OP(mululw) -IWMMXT_OP(muluhw) -IWMMXT_OP(macsw) -IWMMXT_OP(macuw) - -IWMMXT_OP_ENV_SIZE(unpackl) -IWMMXT_OP_ENV_SIZE(unpackh) - -IWMMXT_OP_ENV1(unpacklub) -IWMMXT_OP_ENV1(unpackluw) -IWMMXT_OP_ENV1(unpacklul) -IWMMXT_OP_ENV1(unpackhub) -IWMMXT_OP_ENV1(unpackhuw) -IWMMXT_OP_ENV1(unpackhul) -IWMMXT_OP_ENV1(unpacklsb) -IWMMXT_OP_ENV1(unpacklsw) -IWMMXT_OP_ENV1(unpacklsl) -IWMMXT_OP_ENV1(unpackhsb) -IWMMXT_OP_ENV1(unpackhsw) -IWMMXT_OP_ENV1(unpackhsl) - -IWMMXT_OP_ENV_SIZE(cmpeq) -IWMMXT_OP_ENV_SIZE(cmpgtu) -IWMMXT_OP_ENV_SIZE(cmpgts) - -IWMMXT_OP_ENV_SIZE(mins) -IWMMXT_OP_ENV_SIZE(minu) -IWMMXT_OP_ENV_SIZE(maxs) -IWMMXT_OP_ENV_SIZE(maxu) - -IWMMXT_OP_ENV_SIZE(subn) -IWMMXT_OP_ENV_SIZE(addn) -IWMMXT_OP_ENV_SIZE(subu) -IWMMXT_OP_ENV_SIZE(addu) -IWMMXT_OP_ENV_SIZE(subs) -IWMMXT_OP_ENV_SIZE(adds) - -IWMMXT_OP_ENV(avgb0) -IWMMXT_OP_ENV(avgb1) -IWMMXT_OP_ENV(avgw0) -IWMMXT_OP_ENV(avgw1) - -IWMMXT_OP_ENV(packuw) -IWMMXT_OP_ENV(packul) -IWMMXT_OP_ENV(packuq) -IWMMXT_OP_ENV(packsw) -IWMMXT_OP_ENV(packsl) -IWMMXT_OP_ENV(packsq) - -static void gen_op_iwmmxt_set_mup(void) -{ - TCGv_i32 tmp; - tmp =3D load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); - tcg_gen_ori_i32(tmp, tmp, 2); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); -} - -static void gen_op_iwmmxt_set_cup(void) -{ - TCGv_i32 tmp; - tmp =3D load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); - tcg_gen_ori_i32(tmp, tmp, 1); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); -} - -static void gen_op_iwmmxt_setpsr_nz(void) -{ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); -} - -static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_ext32u_i64(cpu_V1, cpu_V1); - tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, - TCGv_i32 dest) -{ - int rd; - uint32_t offset; - TCGv_i32 tmp; - - rd =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rd); - - offset =3D (insn & 0xff) << ((insn >> 7) & 2); - if (insn & (1 << 24)) { - /* Pre indexed */ - if (insn & (1 << 23)) { - tcg_gen_addi_i32(tmp, tmp, offset); - } else { - tcg_gen_addi_i32(tmp, tmp, -offset); - } - tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 21)) { - store_reg(s, rd, tmp); - } - } else if (insn & (1 << 21)) { - /* Post indexed */ - tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 23)) { - tcg_gen_addi_i32(tmp, tmp, offset); - } else { - tcg_gen_addi_i32(tmp, tmp, -offset); - } - store_reg(s, rd, tmp); - } else if (!(insn & (1 << 23))) { - return 1; - } - return 0; -} - -static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 = dest) -{ - int rd =3D (insn >> 0) & 0xf; - TCGv_i32 tmp; - - if (insn & (1 << 8)) { - if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) { - return 1; - } else { - tmp =3D iwmmxt_load_creg(rd); - } - } else { - tmp =3D tcg_temp_new_i32(); - iwmmxt_load_reg(cpu_V0, rd); - tcg_gen_extrl_i64_i32(tmp, cpu_V0); - } - tcg_gen_andi_i32(tmp, tmp, mask); - tcg_gen_mov_i32(dest, tmp); - return 0; -} - -/* - * Disassemble an iwMMXt instruction. - * Returns nonzero if an error occurred (ie. an undefined instruction). - */ -int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) -{ - int rd, wrd; - int rdhi, rdlo, rd0, rd1, i; - TCGv_i32 addr; - TCGv_i32 tmp, tmp2, tmp3; - - if ((insn & 0x0e000e00) =3D=3D 0x0c000000) { - if ((insn & 0x0fe00ff0) =3D=3D 0x0c400000) { - wrd =3D insn & 0xf; - rdlo =3D (insn >> 12) & 0xf; - rdhi =3D (insn >> 16) & 0xf; - if (insn & ARM_CP_RW_BIT) { /* TMRRC */ - iwmmxt_load_reg(cpu_V0, wrd); - tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); - } else { /* TMCRR */ - tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); - iwmmxt_store_reg(cpu_V0, wrd); - gen_op_iwmmxt_set_mup(); - } - return 0; - } - - wrd =3D (insn >> 12) & 0xf; - addr =3D tcg_temp_new_i32(); - if (gen_iwmmxt_address(s, insn, addr)) { - return 1; - } - if (insn & ARM_CP_RW_BIT) { - if ((insn >> 28) =3D=3D 0xf) { /* WLDRW wCx */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - iwmmxt_store_creg(wrd, tmp); - } else { - i =3D 1; - if (insn & (1 << 8)) { - if (insn & (1 << 22)) { /* WLDRD */ - gen_aa32_ld64(s, cpu_M0, addr, get_mem_index(s)); - i =3D 0; - } else { /* WLDRW wRd */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - } - } else { - tmp =3D tcg_temp_new_i32(); - if (insn & (1 << 22)) { /* WLDRH */ - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* WLDRB */ - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - } - if (i) { - tcg_gen_extu_i32_i64(cpu_M0, tmp); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - } - } else { - if ((insn >> 28) =3D=3D 0xf) { /* WSTRW wCx */ - tmp =3D iwmmxt_load_creg(wrd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } else { - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp =3D tcg_temp_new_i32(); - if (insn & (1 << 8)) { - if (insn & (1 << 22)) { /* WSTRD */ - gen_aa32_st64(s, cpu_M0, addr, get_mem_index(s)); - } else { /* WSTRW wRd */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } - } else { - if (insn & (1 << 22)) { /* WSTRH */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); - } else { /* WSTRB */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); - } - } - } - } - return 0; - } - - if ((insn & 0x0f000000) !=3D 0x0e000000) { - return 1; - } - - switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { - case 0x000: /* WOR */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_orq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x011: /* TMCR */ - if (insn & 0xf) { - return 1; - } - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - switch (wrd) { - case ARM_IWMMXT_wCID: - case ARM_IWMMXT_wCASF: - break; - case ARM_IWMMXT_wCon: - gen_op_iwmmxt_set_cup(); - /* Fall through. */ - case ARM_IWMMXT_wCSSF: - tmp =3D iwmmxt_load_creg(wrd); - tmp2 =3D load_reg(s, rd); - tcg_gen_andc_i32(tmp, tmp, tmp2); - iwmmxt_store_creg(wrd, tmp); - break; - case ARM_IWMMXT_wCGR0: - case ARM_IWMMXT_wCGR1: - case ARM_IWMMXT_wCGR2: - case ARM_IWMMXT_wCGR3: - gen_op_iwmmxt_set_cup(); - tmp =3D load_reg(s, rd); - iwmmxt_store_creg(wrd, tmp); - break; - default: - return 1; - } - break; - case 0x100: /* WXOR */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_xorq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x111: /* TMRC */ - if (insn & 0xf) { - return 1; - } - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - tmp =3D iwmmxt_load_creg(wrd); - store_reg(s, rd, tmp); - break; - case 0x300: /* WANDN */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tcg_gen_neg_i64(cpu_M0, cpu_M0); - gen_op_iwmmxt_andq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x200: /* WAND */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_andq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x810: case 0xa10: /* WMADD */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) { - gen_op_iwmmxt_maddsq_M0_wRn(rd1); - } else { - gen_op_iwmmxt_madduq_M0_wRn(rd1); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_unpacklb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_unpacklw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_unpackll_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_unpackhb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_unpackhw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_unpackhl_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) { - gen_op_iwmmxt_sadw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_sadb_M0_wRn(rd1); - } - if (!(insn & (1 << 20))) { - gen_op_iwmmxt_addl_M0_wRn(wrd); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) { - if (insn & (1 << 20)) { - gen_op_iwmmxt_mulshw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_mulslw_M0_wRn(rd1); - } - } else { - if (insn & (1 << 20)) { - gen_op_iwmmxt_muluhw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_mululw_M0_wRn(rd1); - } - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) { - gen_op_iwmmxt_macsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_macuw_M0_wRn(rd1); - } - if (!(insn & (1 << 20))) { - iwmmxt_load_reg(cpu_V1, wrd); - tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_cmpeql_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) { - if (insn & (1 << 20)) { - gen_op_iwmmxt_avgw1_M0_wRn(rd1); - } else { - gen_op_iwmmxt_avgw0_M0_wRn(rd1); - } - } else { - if (insn & (1 << 20)) { - gen_op_iwmmxt_avgb1_M0_wRn(rd1); - } else { - gen_op_iwmmxt_avgb0_M0_wRn(rd1); - } - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); - tcg_gen_andi_i32(tmp, tmp, 7); - iwmmxt_load_reg(cpu_V1, rd1); - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ - if (((insn >> 6) & 3) =3D=3D 3) { - return 1; - } - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rd); - gen_op_iwmmxt_movq_M0_wRn(wrd); - switch ((insn >> 6) & 3) { - case 0: - tmp2 =3D tcg_constant_i32(0xff); - tmp3 =3D tcg_constant_i32((insn & 7) << 3); - break; - case 1: - tmp2 =3D tcg_constant_i32(0xffff); - tmp3 =3D tcg_constant_i32((insn & 3) << 4); - break; - case 2: - tmp2 =3D tcg_constant_i32(0xffffffff); - tmp3 =3D tcg_constant_i32((insn & 1) << 5); - break; - default: - g_assert_not_reached(); - } - gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - if (rd =3D=3D 15 || ((insn >> 22) & 3) =3D=3D 3) { - return 1; - } - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp =3D tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 0: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - if (insn & 8) { - tcg_gen_ext8s_i32(tmp, tmp); - } else { - tcg_gen_andi_i32(tmp, tmp, 0xff); - } - break; - case 1: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - if (insn & 8) { - tcg_gen_ext16s_i32(tmp, tmp); - } else { - tcg_gen_andi_i32(tmp, tmp, 0xffff); - } - break; - case 2: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - break; - } - store_reg(s, rd, tmp); - break; - case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ - if ((insn & 0x000ff008) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { - return 1; - } - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); - switch ((insn >> 22) & 3) { - case 0: - tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); - break; - case 1: - tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4); - break; - case 2: - tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12); - break; - } - tcg_gen_shli_i32(tmp, tmp, 28); - gen_set_nzcv(tmp); - break; - case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ - if (((insn >> 6) & 3) =3D=3D 3) { - return 1; - } - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rd); - switch ((insn >> 6) & 3) { - case 0: - gen_helper_iwmmxt_bcstb(cpu_M0, tmp); - break; - case 1: - gen_helper_iwmmxt_bcstw(cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_bcstl(cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ - if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { - return 1; - } - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - switch ((insn >> 22) & 3) { - case 0: - for (i =3D 0; i < 7; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 4); - tcg_gen_and_i32(tmp, tmp, tmp2); - } - break; - case 1: - for (i =3D 0; i < 3; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 8); - tcg_gen_and_i32(tmp, tmp, tmp2); - } - break; - case 2: - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_and_i32(tmp, tmp, tmp2); - break; - } - gen_set_nzcv(tmp); - break; - case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); - break; - case 1: - gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); - break; - case 2: - gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ - if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) { - return 1; - } - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - switch ((insn >> 22) & 3) { - case 0: - for (i =3D 0; i < 7; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 4); - tcg_gen_or_i32(tmp, tmp, tmp2); - } - break; - case 1: - for (i =3D 0; i < 3; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 8); - tcg_gen_or_i32(tmp, tmp, tmp2); - } - break; - case 2: - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_or_i32(tmp, tmp, tmp2); - break; - } - gen_set_nzcv(tmp); - break; - case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ - rd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - if ((insn & 0xf) !=3D 0 || ((insn >> 22) & 3) =3D=3D 3) { - return 1; - } - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 0: - gen_helper_iwmmxt_msbb(tmp, cpu_M0); - break; - case 1: - gen_helper_iwmmxt_msbw(tmp, cpu_M0); - break; - case 2: - gen_helper_iwmmxt_msbl(tmp, cpu_M0); - break; - } - store_reg(s, rd, tmp); - break; - case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ - case 0x906: case 0xb06: case 0xd06: case 0xf06: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); - } else { - gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ - case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpacklsb_M0(); - } else { - gen_op_iwmmxt_unpacklub_M0(); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpacklsw_M0(); - } else { - gen_op_iwmmxt_unpackluw_M0(); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpacklsl_M0(); - } else { - gen_op_iwmmxt_unpacklul_M0(); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ - case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpackhsb_M0(); - } else { - gen_op_iwmmxt_unpackhub_M0(); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpackhsw_M0(); - } else { - gen_op_iwmmxt_unpackhuw_M0(); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpackhsl_M0(); - } else { - gen_op_iwmmxt_unpackhul_M0(); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ - case 0x214: case 0x614: case 0xa14: case 0xe14: - if (((insn >> 22) & 3) =3D=3D 0) { - return 1; - } - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ - case 0x014: case 0x414: case 0x814: case 0xc14: - if (((insn >> 22) & 3) =3D=3D 0) { - return 1; - } - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ - case 0x114: case 0x514: case 0x914: case 0xd14: - if (((insn >> 22) & 3) =3D=3D 0) { - return 1; - } - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ - case 0x314: case 0x714: case 0xb14: case 0xf14: - if (((insn >> 22) & 3) =3D=3D 0) { - return 1; - } - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 1: - if (gen_iwmmxt_shift(insn, 0xf, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ - case 0x916: case 0xb16: case 0xd16: case 0xf16: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_minsb_M0_wRn(rd1); - } else { - gen_op_iwmmxt_minub_M0_wRn(rd1); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_minsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_minuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_minsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_minul_M0_wRn(rd1); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ - case 0x816: case 0xa16: case 0xc16: case 0xe16: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_maxsb_M0_wRn(rd1); - } else { - gen_op_iwmmxt_maxub_M0_wRn(rd1); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_maxsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_maxuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_maxsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_maxul_M0_wRn(rd1); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ - case 0x402: case 0x502: case 0x602: case 0x702: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - iwmmxt_load_reg(cpu_V1, rd1); - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, - tcg_constant_i32((insn >> 20) & 3)); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ - case 0x41a: case 0x51a: case 0x61a: case 0x71a: - case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: - case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 20) & 0xf) { - case 0x0: - gen_op_iwmmxt_subnb_M0_wRn(rd1); - break; - case 0x1: - gen_op_iwmmxt_subub_M0_wRn(rd1); - break; - case 0x3: - gen_op_iwmmxt_subsb_M0_wRn(rd1); - break; - case 0x4: - gen_op_iwmmxt_subnw_M0_wRn(rd1); - break; - case 0x5: - gen_op_iwmmxt_subuw_M0_wRn(rd1); - break; - case 0x7: - gen_op_iwmmxt_subsw_M0_wRn(rd1); - break; - case 0x8: - gen_op_iwmmxt_subnl_M0_wRn(rd1); - break; - case 0x9: - gen_op_iwmmxt_subul_M0_wRn(rd1); - break; - case 0xb: - gen_op_iwmmxt_subsl_M0_wRn(rd1); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ - case 0x41e: case 0x51e: case 0x61e: case 0x71e: - case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: - case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); - gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ - case 0x418: case 0x518: case 0x618: case 0x718: - case 0x818: case 0x918: case 0xa18: case 0xb18: - case 0xc18: case 0xd18: case 0xe18: case 0xf18: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 20) & 0xf) { - case 0x0: - gen_op_iwmmxt_addnb_M0_wRn(rd1); - break; - case 0x1: - gen_op_iwmmxt_addub_M0_wRn(rd1); - break; - case 0x3: - gen_op_iwmmxt_addsb_M0_wRn(rd1); - break; - case 0x4: - gen_op_iwmmxt_addnw_M0_wRn(rd1); - break; - case 0x5: - gen_op_iwmmxt_adduw_M0_wRn(rd1); - break; - case 0x7: - gen_op_iwmmxt_addsw_M0_wRn(rd1); - break; - case 0x8: - gen_op_iwmmxt_addnl_M0_wRn(rd1); - break; - case 0x9: - gen_op_iwmmxt_addul_M0_wRn(rd1); - break; - case 0xb: - gen_op_iwmmxt_addsl_M0_wRn(rd1); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ - case 0x408: case 0x508: case 0x608: case 0x708: - case 0x808: case 0x908: case 0xa08: case 0xb08: - case 0xc08: case 0xd08: case 0xe08: case 0xf08: - if (!(insn & (1 << 20)) || ((insn >> 22) & 3) =3D=3D 0) { - return 1; - } - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_packsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_packuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_packsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_packul_M0_wRn(rd1); - } - break; - case 3: - if (insn & (1 << 21)) { - gen_op_iwmmxt_packsq_M0_wRn(rd1); - } else { - gen_op_iwmmxt_packuq_M0_wRn(rd1); - } - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x201: case 0x203: case 0x205: case 0x207: - case 0x209: case 0x20b: case 0x20d: case 0x20f: - case 0x211: case 0x213: case 0x215: case 0x217: - case 0x219: case 0x21b: case 0x21d: case 0x21f: - wrd =3D (insn >> 5) & 0xf; - rd0 =3D (insn >> 12) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - if (rd0 =3D=3D 0xf || rd1 =3D=3D 0xf) { - return 1; - } - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp =3D load_reg(s, rd0); - tmp2 =3D load_reg(s, rd1); - switch ((insn >> 16) & 0xf) { - case 0x0: /* TMIA */ - gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0x8: /* TMIAPH */ - gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy = */ - if (insn & (1 << 16)) { - tcg_gen_shri_i32(tmp, tmp, 16); - } - if (insn & (1 << 17)) { - tcg_gen_shri_i32(tmp2, tmp2, 16); - } - gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - default: - return 1; - } - - return 0; -} - -/* - * Disassemble an XScale DSP instruction. - * Returns nonzero if an error occurred (ie. an undefined instruction). - */ -int disas_dsp_insn(DisasContext *s, uint32_t insn) -{ - int acc, rd0, rd1, rdhi, rdlo; - TCGv_i32 tmp, tmp2; - - if ((insn & 0x0ff00f10) =3D=3D 0x0e200010) { - /* Multiply with Internal Accumulate Format */ - rd0 =3D (insn >> 12) & 0xf; - rd1 =3D insn & 0xf; - acc =3D (insn >> 5) & 7; - - if (acc !=3D 0) { - return 1; - } - - tmp =3D load_reg(s, rd0); - tmp2 =3D load_reg(s, rd1); - switch ((insn >> 16) & 0xf) { - case 0x0: /* MIA */ - gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0x8: /* MIAPH */ - gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0xc: /* MIABB */ - case 0xd: /* MIABT */ - case 0xe: /* MIATB */ - case 0xf: /* MIATT */ - if (insn & (1 << 16)) { - tcg_gen_shri_i32(tmp, tmp, 16); - } - if (insn & (1 << 17)) { - tcg_gen_shri_i32(tmp2, tmp2, 16); - } - gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); - break; - default: - return 1; - } - - gen_op_iwmmxt_movq_wRn_M0(acc); - return 0; - } - - if ((insn & 0x0fe00ff8) =3D=3D 0x0c400000) { - /* Internal Accumulator Access Format */ - rdhi =3D (insn >> 16) & 0xf; - rdlo =3D (insn >> 12) & 0xf; - acc =3D insn & 7; - - if (acc !=3D 0) { - return 1; - } - - if (insn & ARM_CP_RW_BIT) { /* MRA */ - iwmmxt_load_reg(cpu_V0, acc); - tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); - tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - = 1); - } else { /* MAR */ - tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); - iwmmxt_store_reg(cpu_V0, acc); - } - return 0; - } - - return 1; -} - static void gen_goto_ptr(void) { tcg_gen_lookup_and_goto_ptr(); diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 130ed62fcd..fca9912a0a 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -21,6 +21,7 @@ arm_ss.add(gen) arm_ss.add(files( 'cpu32.c', 'translate.c', + 'translate-iwmmxt.c', 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id f10-20020adff8ca000000b0030fae7129e7sm3791910wrq.42.2023.06.11.01.59.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473967; x=1689065967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jPnCvSZ0LTnP+mwyCnVM/2nlrxmNit9JdtgjWZL7/t4=; b=lfGxV1Ki566549IaAA8d17ENQY4Dm9s/xfwMlcTMXHWycuhGkqRcZw/0wjxHE8I21k KvgCnLB0t0hHPkjLBt6ZJVvzchW1d1ELvChP021VkjbqmbKyQcP+3ISKEgofNd/RMxWe FprnTmIJjy/gowU1Kz0zq+SpyjKUsWyRDkQxnnmpxgCsmqemnguKVoMiZlaGX1u5g87B cr5NKYagDZgggiQZrZm9hV+oT28SuW23sBaZ/Koka4vHsKiOL9xQXcHhsjrnm+JE2fSb EBom5Luw95/YTxGbQm0uLIKe6pVEwvcAlsPK6zqy4La9voBNRWz96UQTbwBrpzv1pVho Ic3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473967; x=1689065967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jPnCvSZ0LTnP+mwyCnVM/2nlrxmNit9JdtgjWZL7/t4=; b=hov7PISaIq62QFnNLkY3x4rzlj3Lvx1Z0uxzUMSj8Rfsf14rBTLfu9FYH8VQYZkP+6 m0BK2gzMLUPL9Mo6UBMd3rBQ5MW+yyuzaL61npaNNOwnyn8TKuzFhF2CrHkk5MAHn0AS VuSPbnIho4tSpsyI4Wj8bIPewxfoEu5TfC4mFuYJFCNtMosoogIB/2NYqUNmoZ/Cs27L WEvPssVRpRm2tl43TL7ZR+TNXzQUo3wO6+mnqgiFIzvu1E2NPYKgvDVG+Dqyg2RfYoTj L+MH+BlQmoMsXkrer1M5j7A89aXE5Q4FvNSIrxGM9FWSW1GWciXII2KdWnUZgmnhqvTI Nhxg== X-Gm-Message-State: AC+VfDzsiiCk1JbmSV/RhLYXHolFAa42xghMaKZt4abcsDRD/1ZWfbfN 1Bh9CQ1vuKpVDZSBxlATrg0XoBnPYB/waaUxktY= X-Google-Smtp-Source: ACHHUZ6TviHxRg8WMXl8/t3lLFBITCf7MqdXFBzGuuj5bQSPNc2Gmd8vAGWaKHfNyO4Ot1NXLHrJZA== X-Received: by 2002:a05:600c:2297:b0:3f7:f544:4993 with SMTP id 23-20020a05600c229700b003f7f5444993mr5236269wmf.20.1686473967732; Sun, 11 Jun 2023 01:59:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/26] target/arm/tcg: Reduce 'helper-iwmmxt.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:29 +0200 Message-Id: <20230611085846.21415-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474359696100011 Instead of including helper-iwmmxt.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.h | 1 - target/arm/tcg/iwmmxt_helper.c | 5 ++++- target/arm/tcg/translate-iwmmxt.c | 6 ++++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index c4a321c0ea..dd12fee107 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -949,5 +949,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif =20 -#include "tcg/helper-iwmmxt.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c index 610b1b2103..ee607a3d3d 100644 --- a/target/arm/tcg/iwmmxt_helper.c +++ b/target/arm/tcg/iwmmxt_helper.c @@ -22,7 +22,10 @@ #include "qemu/osdep.h" =20 #include "cpu.h" -#include "exec/helper-proto.h" + +#define HELPER_H "tcg/helper-iwmmxt.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H =20 /* iwMMXt macros extracted from GNU gdb. */ =20 diff --git a/target/arm/tcg/translate-iwmmxt.c b/target/arm/tcg/translate-i= wmmxt.c index 57a924c578..9f6d717ee0 100644 --- a/target/arm/tcg/translate-iwmmxt.c +++ b/target/arm/tcg/translate-iwmmxt.c @@ -12,6 +12,12 @@ #include "translate.h" #include "translate-a32.h" =20 +#define HELPER_H "tcg/helper-iwmmxt.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define ARM_CP_RW_BIT (1 << 20) =20 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474044; cv=none; d=zohomail.com; s=zohoarc; b=iOxQQ1+hL0tVBTroiSEsi9Z5hRraJsCz6gn8mTTc7wHON41JaoUvMXP7A4DBFh7aETRniHQZ83XWx2crVCCebpgNoWdouUX59WyvGEb9OqztfPLHNjU9KofVKQQXRjnXiN1M8bYKTuosP76L0P054rBwW3Ni5sfmlJHNHTh9Agc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474044; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VDBF5f6g3ss6zXACl4FvMit7Sn+wQR849UpnWHsvJfE=; b=N7vvM5aMb0zH4Oo33LTCpM7sgGDEAyiuNaQaJ7M7giy/vsIAe9a8uGGAWJRW++6Ki8gS+mwER3eYTQEakvaN+Nnmb0b/WdM1Y/d8L/1mdxVCmFYA6soG2XKnVBuMFd0dGVxY9n+3fEX7eKmmw2M2WPhO/jo7DVbWVosCSBv1uP4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474044170499.0847362876855; Sun, 11 Jun 2023 02:00:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8GvC-00024J-Od; Sun, 11 Jun 2023 04:59:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8GvA-0001qv-HT for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:36 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gv8-0003hF-0l for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:36 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-30c55d2b9f3so2108005f8f.2 for ; Sun, 11 Jun 2023 01:59:33 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id m19-20020a7bcb93000000b003f7e75b053dsm7908106wmi.34.2023.06.11.01.59.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473972; x=1689065972; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VDBF5f6g3ss6zXACl4FvMit7Sn+wQR849UpnWHsvJfE=; b=jCg5Bxq90cv1t3gOfp2ZLsP9JY+o64XQK7AlXCqdMXBJ7i42Uc+C9EekEyJER5zcRC IJeQWHzBuewmvhU1VhIW0/OTf2Hy70yjlg7yG4ip5qn8kTzKgX3cL3tL7phYvbRo3eNg OXiRBKpfkwnQvALnIYxjGI6z6t+TfV7yT9fgSwV2qJD8ICRo/Vyrropi6f/nNBVZuvv4 GCYRI+pnxCCPIUOmubBHSghfBA33xnZJjjW3CfceHb2ArNhfhA3V6RwMpIryiLf1i+qG tRa/BLzqij6KMC7gxy+zuAX9QNzMGhI5fgiTrzwyVccSji2WD8ZQoOPxxpaQM51BheG8 9kpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473972; x=1689065972; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VDBF5f6g3ss6zXACl4FvMit7Sn+wQR849UpnWHsvJfE=; b=dNaBJv3Rmm9CJYZpXLENVV4Ho+Uoy4nhGzXKlMdbn74/6xZx/DRI83MxVFK90La2hg VGCFYYowvywD56vIFN9kAGCAPIC37gwpFZrvW3MOXvxEskNdmaL7JWw+svD3NR0as8cv zF1FtDs2PPO/QaInZM2nSXYcXcfjRLd7fjUxbivpqeLQ8mbuE/SKtnU8BCD/K6mRSZqf cMs+cZk+lp/awlR4ecFREZjjBQZZThPERhibfVhsqhE+A6fG46iit088nuD2hsnP7X7n wlzkYF6C1WCYzCTd/LlgevfEVlptSe0EUzq7v+UjqyWE5YyE1Y5/h0g6PcPdguUh/ijz mjpg== X-Gm-Message-State: AC+VfDySNVu4fqCDjQXdeyKOy/Lv9xQVXun4lJ57QbOlkE3+hIjCIKwz F+Dgo7VX7ATRf6qa4l5Vy7jzbu0gs8pGRnJvfbU= X-Google-Smtp-Source: ACHHUZ5wiCs97zHLws3N/EJQvPRpaM5WBV8Bg+Koy1/nb8p7hGKA4o6xevgnlw4gDOGb6Q078GLryQ== X-Received: by 2002:a5d:4c4f:0:b0:30a:e4f0:40f7 with SMTP id n15-20020a5d4c4f000000b0030ae4f040f7mr2637709wrt.2.1686473972018; Sun, 11 Jun 2023 01:59:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/26] target/arm/tcg: Extract VFP definitions to 'helper-vfp.h.inc' Date: Sun, 11 Jun 2023 10:58:30 +0200 Message-Id: <20230611085846.21415-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474046235100003 helper.h is used by all units, but not all require the VFP definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- TODO check recpe/rsqrte/rint* are VFP --- target/arm/helper.h | 155 +----------------------------- target/arm/tcg/helper-vfp.h.inc | 163 ++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+), 154 deletions(-) create mode 100644 target/arm/tcg/helper-vfp.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index dd12fee107..cdc453f040 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -103,155 +103,8 @@ DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RW= G, void, env, int) =20 DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, = i32) =20 -DEF_HELPER_1(vfp_get_fpscr, i32, env) -DEF_HELPER_2(vfp_set_fpscr, void, env, i32) - -DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr) -DEF_HELPER_1(vfp_negh, f16, f16) -DEF_HELPER_1(vfp_negs, f32, f32) -DEF_HELPER_1(vfp_negd, f64, f64) -DEF_HELPER_1(vfp_absh, f16, f16) -DEF_HELPER_1(vfp_abss, f32, f32) -DEF_HELPER_1(vfp_absd, f64, f64) -DEF_HELPER_2(vfp_sqrth, f16, f16, env) -DEF_HELPER_2(vfp_sqrts, f32, f32, env) -DEF_HELPER_2(vfp_sqrtd, f64, f64, env) -DEF_HELPER_3(vfp_cmph, void, f16, f16, env) -DEF_HELPER_3(vfp_cmps, void, f32, f32, env) -DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) -DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) -DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) -DEF_HELPER_3(vfp_cmped, void, f64, f64, env) - -DEF_HELPER_2(vfp_fcvtds, f64, f32, env) -DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) -DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr) -DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr) - -DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) -DEF_HELPER_2(vfp_uitos, f32, i32, ptr) -DEF_HELPER_2(vfp_uitod, f64, i32, ptr) -DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) -DEF_HELPER_2(vfp_sitos, f32, i32, ptr) -DEF_HELPER_2(vfp_sitod, f64, i32, ptr) - -DEF_HELPER_2(vfp_touih, i32, f16, ptr) -DEF_HELPER_2(vfp_touis, i32, f32, ptr) -DEF_HELPER_2(vfp_touid, i32, f64, ptr) -DEF_HELPER_2(vfp_touizh, i32, f16, ptr) -DEF_HELPER_2(vfp_touizs, i32, f32, ptr) -DEF_HELPER_2(vfp_touizd, i32, f64, ptr) -DEF_HELPER_2(vfp_tosih, s32, f16, ptr) -DEF_HELPER_2(vfp_tosis, s32, f32, ptr) -DEF_HELPER_2(vfp_tosid, s32, f64, ptr) -DEF_HELPER_2(vfp_tosizh, s32, f16, ptr) -DEF_HELPER_2(vfp_tosizs, s32, f32, ptr) -DEF_HELPER_2(vfp_tosizd, s32, f64, ptr) - -DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) -DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) -DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) -DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr) -DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr) -DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr) -DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) -DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) - -DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr) - DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) =20 -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i3= 2) -DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i3= 2) -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i3= 2) -DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i3= 2) - -DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) -DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) -DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr) - -DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) -DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) -DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) =20 DEF_HELPER_3(shl_cc, i32, env, i32, i32) @@ -259,13 +112,6 @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_3(ror_cc, i32, env, i32, i32) =20 -DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr) -DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) - DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) =20 @@ -949,4 +795,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif =20 +#include "tcg/helper-vfp.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-vfp.h.inc b/target/arm/tcg/helper-vfp.h.= inc new file mode 100644 index 0000000000..31b58568e8 --- /dev/null +++ b/target/arm/tcg/helper-vfp.h.inc @@ -0,0 +1,163 @@ +/* + * ARM VFP helper definitions + * + * Copyright (c) 2007 CodeSourcery. + * Written by Paul Brook + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +DEF_HELPER_1(vfp_get_fpscr, i32, env) +DEF_HELPER_2(vfp_set_fpscr, void, env, i32) + +DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr) +DEF_HELPER_1(vfp_negh, f16, f16) +DEF_HELPER_1(vfp_negs, f32, f32) +DEF_HELPER_1(vfp_negd, f64, f64) +DEF_HELPER_1(vfp_absh, f16, f16) +DEF_HELPER_1(vfp_abss, f32, f32) +DEF_HELPER_1(vfp_absd, f64, f64) +DEF_HELPER_2(vfp_sqrth, f16, f16, env) +DEF_HELPER_2(vfp_sqrts, f32, f32, env) +DEF_HELPER_2(vfp_sqrtd, f64, f64, env) +DEF_HELPER_3(vfp_cmph, void, f16, f16, env) +DEF_HELPER_3(vfp_cmps, void, f32, f32, env) +DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) +DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) +DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) +DEF_HELPER_3(vfp_cmped, void, f64, f64, env) + +DEF_HELPER_2(vfp_fcvtds, f64, f32, env) +DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) +DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr) +DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr) + +DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) +DEF_HELPER_2(vfp_uitos, f32, i32, ptr) +DEF_HELPER_2(vfp_uitod, f64, i32, ptr) +DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) +DEF_HELPER_2(vfp_sitos, f32, i32, ptr) +DEF_HELPER_2(vfp_sitod, f64, i32, ptr) + +DEF_HELPER_2(vfp_touih, i32, f16, ptr) +DEF_HELPER_2(vfp_touis, i32, f32, ptr) +DEF_HELPER_2(vfp_touid, i32, f64, ptr) +DEF_HELPER_2(vfp_touizh, i32, f16, ptr) +DEF_HELPER_2(vfp_touizs, i32, f32, ptr) +DEF_HELPER_2(vfp_touizd, i32, f64, ptr) +DEF_HELPER_2(vfp_tosih, s32, f16, ptr) +DEF_HELPER_2(vfp_tosis, s32, f32, ptr) +DEF_HELPER_2(vfp_tosid, s32, f64, ptr) +DEF_HELPER_2(vfp_tosizh, s32, f16, ptr) +DEF_HELPER_2(vfp_tosizs, s32, f32, ptr) +DEF_HELPER_2(vfp_tosizd, s32, f64, ptr) + +DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) +DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) +DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr) +DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr) +DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr) +DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) + +DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr) + +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i3= 2) + +DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) +DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) +DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr) + +DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) +DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) + +DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474283; cv=none; d=zohomail.com; s=zohoarc; b=FYoGT3DEDARpnGR80hTIAQNOMtBFeIIth4q2DWuMv+4U8Y4QlNQEFVRJKIvOYamjczHcnS6dOqwH7xnTAqLOLMnI1LVRgkOIX0s3NGGPI3EVFvnx/FJez0J9sQ1w9d/Llxs55Pa7vtu+StcaJ4LhqQSJAhHQL6N9fdEoTsNkXcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474283; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AR0wVsv/Xl7da2GZgdWozBlSUli51+XLnKlxpWKhmhI=; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id m11-20020a5d6a0b000000b0030b5d203e7esm9086865wru.97.2023.06.11.01.59.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473976; x=1689065976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AR0wVsv/Xl7da2GZgdWozBlSUli51+XLnKlxpWKhmhI=; b=Mheq9QXbdVE16Jmrn8rZRIntOr/umM7cAbXAZwVyL4YwtolzHrGO6dYkGnriz8YEFx M6/ydDTcHR0KedQ1q8i6PCiskh3v6ipophKF3RK8i1wa9EY2fm1lavXdzoiSEWy1wCTO b070fAp/xb4wTF/yhldw2UxeL2aZIu2upg2VTeKHFn4ioeQehBfsqR0iDC0dfPH7KQMF wYS2VtmXA/p9fkQU9km7XnWWbnHzBW5uAOi0ODFCdEH8QcOsfhx1uvT3L5uqlPMvJWLz J5roSnVOj5zGQOXOGve+dtTIfIgMkzBRpb6nxRzcoRpoARJEGypa+oV/YrELRcsBXCnp L28w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473976; x=1689065976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AR0wVsv/Xl7da2GZgdWozBlSUli51+XLnKlxpWKhmhI=; b=hUFBTrDHAblnzl3E5+qt8C/0vM5lzMloGoOzU9nwsZW8innr0CKOceUmaJW022wsS5 i4CeK39VxcsiRyeH/jpMGjBFwbo0zCwlQ9NFG1NjMTTav4q87RdOsTFQBq42XFN/xT9N W1/JSJ8Z2spMY9DHOlrUAg6mvuVYsJz30F7mDJ9UbImWcXi/f8CM8shdIKQrUm6K48J0 AbB71SR6FK5WCw/mlSPULW/mo2hmGgUfaYtQPhD5efISbYTkTVsyC8q4JR4mae7S3dMj MtBR0OLixLrIHGtKx+uaPMTvf2/78FyMGU3LxIuNY9eIIcZiagC2tpPF107Vh5tX1ZEb 7zTw== X-Gm-Message-State: AC+VfDxlE9CGThyZOAXVCdlYVDq6eB/Q4rT+Sx14Cu5ZzB6Fglc0CWhn aVs0Q4GE3uJWiX7VrByiThHw+tjbpa2ic04js4g= X-Google-Smtp-Source: ACHHUZ4/MUHbhwywlyZe1qDRNjKo3aTfVIVJtyMfwAA0Bj/xmWCh778CSYRqLV602ftukrP221SQsw== X-Received: by 2002:a05:600c:21c7:b0:3f7:3651:450c with SMTP id x7-20020a05600c21c700b003f73651450cmr4555331wmj.6.1686473976267; Sun, 11 Jun 2023 01:59:36 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 11/26] target/arm/tcg: Reduce 'helper-vfp.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:31 +0200 Message-Id: <20230611085846.21415-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474285305100002 Instead of including helper-vfp.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/mve_helper.c | 4 ++++ target/arm/tcg/sve_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 4 ++++ target/arm/tcg/translate-m-nocp.c | 5 +++++ target/arm/tcg/translate-neon.c | 4 ++++ target/arm/tcg/translate-vfp.c | 6 ++++++ target/arm/tcg/vec_helper.c | 4 ++++ target/arm/vfp_helper.c | 4 ++++ 9 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index cdc453f040..1041accf71 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -795,5 +795,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif =20 -#include "tcg/helper-vfp.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 403b345ea3..d8ba5a9e60 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -27,6 +27,10 @@ #include "tcg/tcg.h" #include "fpu/softfloat.h" =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static uint16_t mve_eci_mask(CPUARMState *env) { /* diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 0097522470..8a0d966aae 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -29,6 +29,9 @@ #include "sve_ldst_internal.h" #include "hw/core/tcg-cpu-ops.h" =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H =20 /* Return a value for NZCV as per the ARM PredTest pseudofunction. * diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index aa93f37e21..c0727c900f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -26,6 +26,10 @@ #include "semihosting/semihost.h" #include "cpregs.h" =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; =20 diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m= -nocp.c index 33f6478bb9..7343945b41 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -21,6 +21,11 @@ #include "translate.h" #include "translate-a32.h" =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +/* Include the generated decoder */ #include "decode-m-nocp.c.inc" =20 /* diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 03913de047..497aba2e39 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -24,6 +24,10 @@ #include "translate.h" #include "translate-a32.h" =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 359b1e3e96..10d4502239 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -24,6 +24,12 @@ #include "translate.h" #include "translate-a32.h" =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* Include the generated VFP decoder */ #include "decode-vfp.c.inc" #include "decode-vfp-uncond.c.inc" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index f59d3b26ea..013ca1b05f 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -25,6 +25,10 @@ #include "qemu/int128.h" #include "vec_internal.h" =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 36906db8e0..cbd78cc810 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -32,6 +32,10 @@ =20 #ifdef CONFIG_TCG =20 +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Convert host exception flags to vfp form. */ static inline int vfp_exceptbits_from_host(int host_bits) { --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id k10-20020adff5ca000000b003077a19cf75sm9081745wrp.60.2023.06.11.01.59.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473980; x=1689065980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cI5tDvyzjBGzw5l/XkLwcYgWT6+N8zbnEiW/1PeWfOw=; b=onYxBlIvsAEMelIaiMMsa1RUIC+5AVADZKAyOheNc5XcnTGqIgqsxXJcAJRMHrGwU4 AFLPwC9c4W/v/jHdjEWdQiCNL9ICbvm6ri4HNldBuCBZJh1YL2tj3OPSvVG4PrriUqBB HT9OAFkLgCzYsXbbBjpPTcmrqdTiTwe7MADiQVK6VWN3r1Wv4jZOokkGh/UqnEPTDomy Q2TFdDpFkz0Lun/ay3315U3zX7iS0j9nLwnH3JIQenRp/LRdPiiFGSgsy48UGWeciAc0 NJgBtdFLqCEKy1fIRM9He1sPmLYIRxlDKgOdydFJ6ZRhdvALefxPauCVYgaomHrY78VZ ozOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473980; x=1689065980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cI5tDvyzjBGzw5l/XkLwcYgWT6+N8zbnEiW/1PeWfOw=; b=SxGx88FUql8w6OAF2ZKQOaeofSiBKtpNVIICbylTkm4GH0IdIAbA9K166Lidsyc65j NoK/tA8qfdKZd03o8qpKWHOgmHEpYxgi+5yRejAw+2N9nUolz3YW0CJ58842OilWNxR7 qcIxktSFlWi0Tu04SdUimE7lOH1ns5gTWvhbz5K3MMV41rDgTYZYPIh4RRdPG3tk+rKT mbjby4I/h3iwTj3XIp0bRp9syZJca7Kt8MLYbfad7YR54rLkSpbb5lS8+e0NDjB+czIJ bWr7fa+9dL4uv4O6BAm1/erGFi1Fq57iCya4SCbEc92fGKwg4dmnKq4l1pLKD4tXWMcu fROw== X-Gm-Message-State: AC+VfDx3zhFx1dKym4M5+aHBFX6iuhIlxCCOXiSndDsarANqDtSvlPqv jnGpwycNNZmNLfSzHWeqTZE+JTiyPko4geX0QlM= X-Google-Smtp-Source: ACHHUZ6vxcIviv3fsTWgo/KcPrs/kJmf4LDcY2odLtChzDlAIBPZnQbSCosdZ4vGSR136+jADFgFug== X-Received: by 2002:a05:600c:21c7:b0:3f7:3651:450c with SMTP id x7-20020a05600c21c700b003f73651450cmr4555420wmj.6.1686473980472; Sun, 11 Jun 2023 01:59:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 12/26] target/arm/tcg: Move neon_tbl() from op_helper.c to neon_helper.c Date: Sun, 11 Jun 2023 10:58:32 +0200 Message-Id: <20230611085846.21415-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474058284100003 neon_tbl() helper is only called by NEON files. No need to have it in the generic op_helper.c, move it with the rest of the NEON helpers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/neon_helper.c | 22 ++++++++++++++++++++++ target/arm/tcg/op_helper.c | 22 ---------------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index bc6c4a54e9..0a4ab3e42c 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -1738,3 +1738,25 @@ void HELPER(neon_zip16)(void *vd, void *vm) rm[0] =3D m0; rd[0] =3D d0; } + +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, + uint64_t ireg, uint64_t def) +{ + uint64_t tmp, val =3D 0; + uint32_t maxindex =3D ((desc & 3) + 1) * 8; + uint32_t base_reg =3D desc >> 2; + uint32_t shift, index, reg; + + for (shift =3D 0; shift < 64; shift +=3D 8) { + index =3D (ireg >> shift) & 0xff; + if (index < maxindex) { + reg =3D base_reg + (index >> 3); + tmp =3D *aa32_vfp_dreg(env, reg); + tmp =3D ((tmp >> ((index & 7) << 3)) & 0xff) << shift; + } else { + tmp =3D def & (0xffull << shift); + } + val |=3D tmp; + } + return val; +} diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 3baf8004f6..70a9c37b74 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -82,28 +82,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, raise_exception(env, excp, syndrome, target_el); } =20 -uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, - uint64_t ireg, uint64_t def) -{ - uint64_t tmp, val =3D 0; - uint32_t maxindex =3D ((desc & 3) + 1) * 8; - uint32_t base_reg =3D desc >> 2; - uint32_t shift, index, reg; - - for (shift =3D 0; shift < 64; shift +=3D 8) { - index =3D (ireg >> shift) & 0xff; - if (index < maxindex) { - reg =3D base_reg + (index >> 3); - tmp =3D *aa32_vfp_dreg(env, reg); - tmp =3D ((tmp >> ((index & 7) << 3)) & 0xff) << shift; - } else { - tmp =3D def & (0xffull << shift); - } - val |=3D tmp; - } - return val; -} - void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) { /* --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474304; cv=none; d=zohomail.com; s=zohoarc; b=fROgIZJWDpsr5QLB2mpG4hwtgw2bFaeG4/OQIcb3B7v8B45DPE3xJzszu/bUGOrQPJoRlRePdVjGj61sGjctXvStLdofpvWo39z4jifEHYU6Kwhp2ChA+K6PqKDsIc4I0jM6PV7YsC36I+RlxzixbwerrjKqI+a/hJ6j51pLCX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474304; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QVdVsutRh46jRwa2PoJBROMIYsAkmEcJwwavIyUiJGE=; b=F1/kjU+ZMtGWh3Fm7NwI7PjkpypRLnr/ujIPjOTi2+gkeQAlBv0LGXPmjGV5cM3k44NbmFrkPRG7SACl86Q1RidK0yUVGaBz6X5JtER4jzVwSgAuK1JW5wd9zOjeVnAsKv/vq1B4eiY/Vmwo7ukPh8cPfAJzWqvWH9dxjXPBHe4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474304895961.4276316232971; Sun, 11 Jun 2023 02:05:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gww-0003t6-BH; Sun, 11 Jun 2023 05:01:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8GvQ-0002Sd-2T for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:52 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8GvK-0003jy-Sa for qemu-devel@nongnu.org; Sun, 11 Jun 2023 04:59:49 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f736e0c9b1so34201375e9.3 for ; Sun, 11 Jun 2023 01:59:46 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id 16-20020a05600c021000b003f7f6827ab9sm7825038wmi.31.2023.06.11.01.59.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473985; x=1689065985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QVdVsutRh46jRwa2PoJBROMIYsAkmEcJwwavIyUiJGE=; b=WViQk21z2QcHR80MDEUpGqwwxqEOC9/bM2qlRy8fQ96jbRD6xZLukAuZvB3hUry4VX xL8SPWSewEsppjHoewBoDrKTEFIN/5faT2FouAYQsLcKT8MdJObXFvMYnYBNjfhWOdW1 7ZOm5OYrafSygyXLOOQeYIhrEyM3nZ5TsnQJ6M8E6P5UJytVbgPPoDirHpRgUZmWFFlZ ljEV7yVQNT9X/2QCmaKq1iuFjVACx8h9DlWmvYtN1L3+9CuVYoMneuVlhsCiLvp1xTEi jmWAx/h6JvGKboM1X4W9oQQ+DcXOa+yrZ60zDEy6uqdBlYFDesFSdrWLR/RHqrfnpbhM Edog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473985; x=1689065985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QVdVsutRh46jRwa2PoJBROMIYsAkmEcJwwavIyUiJGE=; b=DLBlbM79KQEfdnK2TxYF4Gk0ww37WdsFVE6KQCGU+diKou5r94jYXIi8kkGUESZ6/5 IGSHvkHScmDlox5VRXCtJNgZda4sOHEJe4slywW5oos511dyn6rKfOyI0ovBqLPdV0yo Jb8DNJJxtAMcOyP2GfQJz/FOcIZq7StaCbfI0E+/HlMqDI5prz0WJwD3LkS+1zqj9Rnh anvVJcl4PSXH08F/17iHFMSMMyHFGCWURku+35mYy9VuhHzQULby1GCd+LIajDxRfx+Y h8Een4DcE3+Hf4GEi2YzcNwSvDyRN9CE7EaAfNIpRl6tlGqknABaQ9gXXHAVjd0KPYMK UbPA== X-Gm-Message-State: AC+VfDzEVNK9PW1N47q4ZndczCgdixAePvq+OgCadk9iYpXfRrxPYlqm dKkjwhvBWWYKJ/NfDU+3XQ2mLskbrvl8idTW9Oo= X-Google-Smtp-Source: ACHHUZ6gE3Fdu+H/cGJplIjr3MMWQrUNprlltsn+pxUgLChKmdltGgGOR2g7VzBrFpigHGi+jU2XyA== X-Received: by 2002:a1c:7203:0:b0:3f4:28bd:74f5 with SMTP id n3-20020a1c7203000000b003f428bd74f5mr5015404wmc.25.1686473984712; Sun, 11 Jun 2023 01:59:44 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 13/26] target/arm/tcg: Extract NEON definitions to 'helper-neon.h.inc' Date: Sun, 11 Jun 2023 10:58:33 +0200 Message-Id: <20230611085846.21415-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474305498100004 helper.h is used by all units, but not all require the NEON definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 207 +----------------------------- target/arm/tcg/helper-neon.h.inc | 213 +++++++++++++++++++++++++++++++ 2 files changed, 214 insertions(+), 206 deletions(-) create mode 100644 target/arm/tcg/helper-neon.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index 1041accf71..97d97dc9d8 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -105,8 +105,6 @@ DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, = env, tl, i32, i32, i32) =20 DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) =20 -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) - DEF_HELPER_3(shl_cc, i32, env, i32, i32) DEF_HELPER_3(shr_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32) @@ -117,191 +115,6 @@ DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64= , ptr) =20 DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) =20 -/* neon_helper.c */ -DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s64, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(neon_sqadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_sqadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_sqadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_sqadd_u64, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qadd_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qadd_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qsub_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qsub_s64, i64, env, i64, i64) - -DEF_HELPER_2(neon_hadd_s8, i32, i32, i32) -DEF_HELPER_2(neon_hadd_u8, i32, i32, i32) -DEF_HELPER_2(neon_hadd_s16, i32, i32, i32) -DEF_HELPER_2(neon_hadd_u16, i32, i32, i32) -DEF_HELPER_2(neon_hadd_s32, s32, s32, s32) -DEF_HELPER_2(neon_hadd_u32, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_s8, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_u8, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_s16, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_u16, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_s32, s32, s32, s32) -DEF_HELPER_2(neon_rhadd_u32, i32, i32, i32) -DEF_HELPER_2(neon_hsub_s8, i32, i32, i32) -DEF_HELPER_2(neon_hsub_u8, i32, i32, i32) -DEF_HELPER_2(neon_hsub_s16, i32, i32, i32) -DEF_HELPER_2(neon_hsub_u16, i32, i32, i32) -DEF_HELPER_2(neon_hsub_s32, s32, s32, s32) -DEF_HELPER_2(neon_hsub_u32, i32, i32, i32) - -DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) - -DEF_HELPER_2(neon_shl_u16, i32, i32, i32) -DEF_HELPER_2(neon_shl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) -DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) -DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) - -DEF_HELPER_2(neon_add_u8, i32, i32, i32) -DEF_HELPER_2(neon_add_u16, i32, i32, i32) -DEF_HELPER_2(neon_padd_u8, i32, i32, i32) -DEF_HELPER_2(neon_padd_u16, i32, i32, i32) -DEF_HELPER_2(neon_sub_u8, i32, i32, i32) -DEF_HELPER_2(neon_sub_u16, i32, i32, i32) -DEF_HELPER_2(neon_mul_u8, i32, i32, i32) -DEF_HELPER_2(neon_mul_u16, i32, i32, i32) - -DEF_HELPER_2(neon_tst_u8, i32, i32, i32) -DEF_HELPER_2(neon_tst_u16, i32, i32, i32) -DEF_HELPER_2(neon_tst_u32, i32, i32, i32) - -DEF_HELPER_1(neon_clz_u8, i32, i32) -DEF_HELPER_1(neon_clz_u16, i32, i32) -DEF_HELPER_1(neon_cls_s8, i32, i32) -DEF_HELPER_1(neon_cls_s16, i32, i32) -DEF_HELPER_1(neon_cls_s32, i32, i32) -DEF_HELPER_1(neon_cnt_u8, i32, i32) -DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) - -DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) -DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) -DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) -DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) - -DEF_HELPER_1(neon_narrow_u8, i32, i64) -DEF_HELPER_1(neon_narrow_u16, i32, i64) -DEF_HELPER_2(neon_unarrow_sat8, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u8, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s8, i32, env, i64) -DEF_HELPER_2(neon_unarrow_sat16, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u16, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s16, i32, env, i64) -DEF_HELPER_2(neon_unarrow_sat32, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u32, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s32, i32, env, i64) -DEF_HELPER_1(neon_narrow_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_high_u16, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) -DEF_HELPER_1(neon_widen_u8, i64, i32) -DEF_HELPER_1(neon_widen_s8, i64, i32) -DEF_HELPER_1(neon_widen_u16, i64, i32) -DEF_HELPER_1(neon_widen_s16, i64, i32) - -DEF_HELPER_2(neon_addl_u16, i64, i64, i64) -DEF_HELPER_2(neon_addl_u32, i64, i64, i64) -DEF_HELPER_2(neon_paddl_u16, i64, i64, i64) -DEF_HELPER_2(neon_paddl_u32, i64, i64, i64) -DEF_HELPER_2(neon_subl_u16, i64, i64, i64) -DEF_HELPER_2(neon_subl_u32, i64, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) -DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) -DEF_HELPER_2(neon_mull_u8, i64, i32, i32) -DEF_HELPER_2(neon_mull_s8, i64, i32, i32) -DEF_HELPER_2(neon_mull_u16, i64, i32, i32) -DEF_HELPER_2(neon_mull_s16, i64, i32, i32) - -DEF_HELPER_1(neon_negl_u16, i64, i64) -DEF_HELPER_1(neon_negl_u32, i64, i64) - -DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) - -DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr) -DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr) - -DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) - DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 @@ -403,13 +216,6 @@ DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 -DEF_HELPER_FLAGS_5(neon_paddh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_5(neon_pmaxh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_5(neon_pminh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_5(neon_padds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_5(neon_pmaxs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_5(neon_pmins, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) - DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) @@ -630,8 +436,6 @@ DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 -DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_3(gvec_ssra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_ssra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_ssra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) @@ -710,16 +514,6 @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 -DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) @@ -795,4 +589,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif =20 +#include "tcg/helper-neon.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-neon.h.inc b/target/arm/tcg/helper-neon.= h.inc new file mode 100644 index 0000000000..5ea58c058c --- /dev/null +++ b/target/arm/tcg/helper-neon.h.inc @@ -0,0 +1,213 @@ +/* + * ARM NEON helper definitions + * + * Copyright (c) 2007, 2008 CodeSourcery. + * Written by Paul Brook + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) + +DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s64, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(neon_sqadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u64, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qadd_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qadd_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qsub_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qsub_s64, i64, env, i64, i64) + +DEF_HELPER_2(neon_hadd_s8, i32, i32, i32) +DEF_HELPER_2(neon_hadd_u8, i32, i32, i32) +DEF_HELPER_2(neon_hadd_s16, i32, i32, i32) +DEF_HELPER_2(neon_hadd_u16, i32, i32, i32) +DEF_HELPER_2(neon_hadd_s32, s32, s32, s32) +DEF_HELPER_2(neon_hadd_u32, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_s8, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_u8, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_s16, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_u16, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_s32, s32, s32, s32) +DEF_HELPER_2(neon_rhadd_u32, i32, i32, i32) +DEF_HELPER_2(neon_hsub_s8, i32, i32, i32) +DEF_HELPER_2(neon_hsub_u8, i32, i32, i32) +DEF_HELPER_2(neon_hsub_s16, i32, i32, i32) +DEF_HELPER_2(neon_hsub_u16, i32, i32, i32) +DEF_HELPER_2(neon_hsub_s32, s32, s32, s32) +DEF_HELPER_2(neon_hsub_u32, i32, i32, i32) + +DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) + +DEF_HELPER_2(neon_shl_u16, i32, i32, i32) +DEF_HELPER_2(neon_shl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) +DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) +DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) + +DEF_HELPER_2(neon_add_u8, i32, i32, i32) +DEF_HELPER_2(neon_add_u16, i32, i32, i32) +DEF_HELPER_2(neon_padd_u8, i32, i32, i32) +DEF_HELPER_2(neon_padd_u16, i32, i32, i32) +DEF_HELPER_2(neon_sub_u8, i32, i32, i32) +DEF_HELPER_2(neon_sub_u16, i32, i32, i32) +DEF_HELPER_2(neon_mul_u8, i32, i32, i32) +DEF_HELPER_2(neon_mul_u16, i32, i32, i32) + +DEF_HELPER_2(neon_tst_u8, i32, i32, i32) +DEF_HELPER_2(neon_tst_u16, i32, i32, i32) +DEF_HELPER_2(neon_tst_u32, i32, i32, i32) + +DEF_HELPER_1(neon_clz_u8, i32, i32) +DEF_HELPER_1(neon_clz_u16, i32, i32) +DEF_HELPER_1(neon_cls_s8, i32, i32) +DEF_HELPER_1(neon_cls_s16, i32, i32) +DEF_HELPER_1(neon_cls_s32, i32, i32) +DEF_HELPER_1(neon_cnt_u8, i32, i32) +DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) + +DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) +DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) + +DEF_HELPER_1(neon_narrow_u8, i32, i64) +DEF_HELPER_1(neon_narrow_u16, i32, i64) +DEF_HELPER_2(neon_unarrow_sat8, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_u8, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_s8, i32, env, i64) +DEF_HELPER_2(neon_unarrow_sat16, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_u16, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_s16, i32, env, i64) +DEF_HELPER_2(neon_unarrow_sat32, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_u32, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_s32, i32, env, i64) +DEF_HELPER_1(neon_narrow_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_high_u16, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) +DEF_HELPER_1(neon_widen_u8, i64, i32) +DEF_HELPER_1(neon_widen_s8, i64, i32) +DEF_HELPER_1(neon_widen_u16, i64, i32) +DEF_HELPER_1(neon_widen_s16, i64, i32) + +DEF_HELPER_2(neon_addl_u16, i64, i64, i64) +DEF_HELPER_2(neon_addl_u32, i64, i64, i64) +DEF_HELPER_2(neon_paddl_u16, i64, i64, i64) +DEF_HELPER_2(neon_paddl_u32, i64, i64, i64) +DEF_HELPER_2(neon_subl_u16, i64, i64, i64) +DEF_HELPER_2(neon_subl_u32, i64, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) +DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) +DEF_HELPER_2(neon_mull_u8, i64, i32, i32) +DEF_HELPER_2(neon_mull_s8, i64, i32, i32) +DEF_HELPER_2(neon_mull_u16, i64, i32, i32) +DEF_HELPER_2(neon_mull_s16, i64, i32, i32) + +DEF_HELPER_1(neon_negl_u16, i64, i64) +DEF_HELPER_1(neon_negl_u32, i64, i64) + +DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) + +DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr) +DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr) + +DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) + +DEF_HELPER_FLAGS_5(neon_paddh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_5(neon_pmaxh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_5(neon_pminh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_5(neon_padds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_5(neon_pmaxs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_5(neon_pmins, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, = i32) + +DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474102; cv=none; d=zohomail.com; s=zohoarc; b=akz6kA6EZV1fUWxxuYABJhzAcwVgaIyfQBgw0VpL8qokq3qndvAUQz02Zo2HRx7mwgLFDV+YpU834JAUA4zODXfP1PgvywpIaJthOhQjfPRGbkWvQvgrZq6/BIu8llKGhpPlKtXtW7Gz1EyfyUp+o03wKJnHOLaCr+aqUC0uPJQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474102; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id o7-20020adfeac7000000b002fed865c55esm9139039wrn.56.2023.06.11.01.59.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473989; x=1689065989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5nz4UOUVBnov9YujuZ44MJvqxjEXrGs664hSVxA4MoM=; b=iZsCcQAIsiry4BtQd/wddHuRkOXcU0t2ZsyUrWSsGAytswR/cATk70HNp/12c3LfEc Tmt70EiFy7AWJ8KQJpP3RbyeNHAurOTb2dR612VCLjtYnQsCpZ1Gx4ryQWRrg+y2hfbi qrau9WJJdDw0ZMS4tWSZrZEqVLHmUsfsKzcbxNrzg441dSwJm7KhlnnfqMl52u7lTAGS p91fr0TZzT0Y249PA2EkPWbgUbTTyp5YH5DGfM8zzRO2XL/GEDooQIUIn05ZBWbL7hd/ 0JhBjNFir+uU7X8xvV7kc4NmOqreVr0wFTPNCmiJe2Z9aFGYic8A/rdGEE6YNRMPweKF MIHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473989; x=1689065989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5nz4UOUVBnov9YujuZ44MJvqxjEXrGs664hSVxA4MoM=; b=eklHBgBBzjpxjWCeRcqh7pQ4EErW0+ZsC7oJo6jiA0xQ1dW/5AWl30kSYCpN2tOh7P 2uIAefx0Qg0nCGsR2eFx+tf+0YtM4ObrUCeTeQwtG0GFpEricyZufdoGxwk0L6/88D0R DW3Be0KnyEJQY8pi4vsuCpDxlSJSUSXrESSewb38eDLjrrK7KQoPux2Fg7xNraHEsOE7 wAwGDtCgujUbqYriPx8muXputvNgnzI2y6ZUqLAOEHPKx0L5LAaNIW6uns6JHzpETEdu 5x4Gu35pjx5Dke9fU2wCqBoh9K8nksv0vPo9n1AcwJx8gYSLuZ3wUOSr/RpZb/hiCId3 FTNg== X-Gm-Message-State: AC+VfDyfratYXaPMx+UQKY3hKIB5XxzN2zhV4rwBv5Xi5C9hwa4bTYTA WaZvmCsVIhfWSQHJrRA97Kq0TPe1O9b4MXOqFvU= X-Google-Smtp-Source: ACHHUZ4niy0G1FGC0sF8damYThS0ASNWJYbE5zyIq+y6lkw8GBxqsVmKvjwYNiSZh0+rkxoNmzNLvw== X-Received: by 2002:adf:f983:0:b0:307:8c47:a266 with SMTP id f3-20020adff983000000b003078c47a266mr2401236wrr.61.1686473989020; Sun, 11 Jun 2023 01:59:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 14/26] target/arm/tcg: Reduce 'helper-neon.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:34 +0200 Message-Id: <20230611085846.21415-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474103471100001 Instead of including helper-neon.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/neon_helper.c | 5 ++++- target/arm/tcg/translate-a64.c | 4 ++++ target/arm/tcg/translate-neon.c | 6 ++++++ target/arm/tcg/translate-sme.c | 4 ++++ target/arm/tcg/translate.c | 4 ++++ target/arm/tcg/vec_helper.c | 4 ++++ 7 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 97d97dc9d8..eb8ac68dc8 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -589,5 +589,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif =20 -#include "tcg/helper-neon.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 0a4ab3e42c..0432a6e771 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -9,10 +9,13 @@ #include "qemu/osdep.h" =20 #include "cpu.h" -#include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "vec_internal.h" =20 +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c0727c900f..22caf89bb0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -30,6 +30,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; =20 diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 497aba2e39..9a1831f849 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -28,6 +28,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index d0054e3f77..24796e5d9e 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -21,6 +21,10 @@ #include "translate.h" #include "translate-a64.h" =20 +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + /* * Include the generated decoder. */ diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index a352fced6e..2b3951cece 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -29,6 +29,10 @@ #include "cpregs.h" #include "exec/helper-proto.h" =20 +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 013ca1b05f..af325577f0 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -29,6 +29,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c230800b003f7ed9dae70sm7858539wmo.0.2023.06.11.01.59.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473993; x=1689065993; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BG2JfoLxLWWNEdXGyigAHArQ37JVkaH142Sz4w845eA=; b=evN1UmyNNRf2UkhROJIa7rk8s+QSMahA+yd+3g9LDK1SNJVNuK2sJpiUx5+DPlT1i1 7odyRlS43kUo+hK24+K6MuG8MKxxzxTMzQ+gMXOQ5ZTwKRq0t6MlUIdW6rM+sZPp8qaq iOgmWAw71FJgH6s8fSbzmzBhmEflWS4i0h6kny5fBYjV3Mbi8sBhvdOFftQeglxe3fpY cwzlwNxaJ3moLurCHbhD76lk4r7WEYKsDbnQVTiHDwOvCvr4O22cvlGisT0NqoPZAjCJ TZbExCQ9n2e0dgDN6xqCQrPaW8bw5eKer1KMukES4wSsOLTUP9iJmndtY1bEJYpEYyzy WCeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473993; x=1689065993; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BG2JfoLxLWWNEdXGyigAHArQ37JVkaH142Sz4w845eA=; b=AoNibLHBgfY+LlfJV/hHv+lYmsqIJGu/ji7hLud0S5H8KxspHlleK+TqrmuHHsa+BF bnGLZqz4mnDK5Z1rflWLlv5AQqMNoljzQGQBoQgHd4DvuRSQ7NmcDkqK4QlhD4FGt1BU Okp6X0uQhsOkz54IoVkjYa8piojT5n83To8OjJyE/UkaJh/mngIn3JBCjezxBTVHL0It eqyICvLYyqkmCPP0vPKkuc8mB2pNVKS/c0CpEBKUE+IB+z+QMB8oHB3iEbpklzkxXzD1 wtPQJc3hd6V1NcFUQHUOe+Ty5EUSvvOykGBulARt4R57IxwaOc6VUP7HuRNlcR+xOD/N XJLw== X-Gm-Message-State: AC+VfDwmYl6sGYj2RpYIr76lIcjZvMP1hLW79H60OadHn+Pi+7l4YWRf xZb5+kF+cE9Rthl6RKJdUfGkMEQzmABWxaveu2Q= X-Google-Smtp-Source: ACHHUZ5Bkn++vce2ThRVXcLuF0W2GzrHjmjEG6xnSXLX+Rsou1bSXzphU83bw0HK0WouZt1FkGzc4g== X-Received: by 2002:adf:ce89:0:b0:303:2583:9635 with SMTP id r9-20020adfce89000000b0030325839635mr2156293wrn.20.1686473993384; Sun, 11 Jun 2023 01:59:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 15/26] target/arm/tcg: Extract SVE2 definitions to 'helper-sve.h.inc' Date: Sun, 11 Jun 2023 10:58:35 +0200 Message-Id: <20230611085846.21415-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474333673100002 helper.h is used by all units, but not all require the SVE2 definitions. We already have helper-sve.h.inc for SVE* definitions, move them there. The next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 46 --------------------------------- target/arm/tcg/helper-sve.h.inc | 46 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index eb8ac68dc8..444be99c96 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -162,23 +162,6 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_5(gvec_sdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(gvec_udot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(gvec_sdot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) @@ -514,35 +497,6 @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 -DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_5(gvec_smmla_b, TCG_CALL_NO_RWG, diff --git a/target/arm/tcg/helper-sve.h.inc b/target/arm/tcg/helper-sve.h.= inc index cc4e1d8948..042a29d76a 100644 --- a/target/arm/tcg/helper-sve.h.inc +++ b/target/arm/tcg/helper-sve.h.inc @@ -2802,3 +2802,49 @@ DEF_HELPER_FLAGS_4(sve2_sqshlu_b, TCG_CALL_NO_RWG, v= oid, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_sqshlu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sve2_sqshlu_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sve2_sqshlu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) + +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id w25-20020a1cf619000000b003f7f52c9988sm7877641wmc.21.2023.06.11.01.59.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686473997; x=1689065997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dviO6n8wA4yJsaVpJ1+rfxPOtVuyVvqQ3eDo42v2ZSU=; b=FzYjyNIZ89jTf4B24vWsducejgSoVidmsAWdRaMygMznHXqyaFDP0uj69dI2Axh7GO zRm/pWmzW2WEZrCkfiVRV8a43pYNLmpayWl7QmiRGyk+CyTMpkglYdEmyDggp6lZty4d b30dPyAGEHUSVkjDlY8/GemwEMffcASa9h45sfqC3fAe18Y5G3rVBJNYUGxoYw6kJPS6 HUsDXfEfdxRibps3oJMgFObmyWzmuA4G11dd8GdBlO8Q5RcIYG+uHVgn5FnY+28jRK/W /wfg6K+LO5Re32dHdQ2iiSMgqkTSCsPXtloslkh/iS6blG5106zXc0ur6spJbak+5rWD C+XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686473997; x=1689065997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dviO6n8wA4yJsaVpJ1+rfxPOtVuyVvqQ3eDo42v2ZSU=; b=ljiUtsSCHG5RQz41q4iwXEY9TfysgZMs3hkVOXFqxAG1AJZSgMUYbJAb9XJiqYRmRa ulo6WVw8QNrX9MRSGfVW2ufrfhc6OMVdR+RbLHC2+IWdfMROXnayidcZvykhtLjF16yd 2xfxuuUwKWF++HcgmWruRe6HH6Ouh75qMkrDbUvI8TyQyT1mgyvZcFPmZbccN5hwOHXY 1Pm+Fnld3ckqJ0mCI0/f4Apz06oWoT9WEYrqtULXqZGW4/setRgp2esRoE9socjr4daz PScWF/D3cSix5tChOyL6etLJj/tgIig0+PR6I40cf7ZDSvQEwN69zmL8D1rUBN6tnllB iL/g== X-Gm-Message-State: AC+VfDxEBCKaRdZ75EUMNQruRWlPTZ/cQV6xJZOmDyd1wXOS0RXyk6e1 lBNugS2ff052qLcbUB1g3AMrJbhgng/4CL7zoH8= X-Google-Smtp-Source: ACHHUZ7JPgSmc8/QgUoIMpDsXtwNeiJb/iEzIHkuSTA05jv2pGewvcA2L+OBJS21KxLylGy/yov5gw== X-Received: by 2002:a05:600c:2212:b0:3f4:23b9:eed2 with SMTP id z18-20020a05600c221200b003f423b9eed2mr4821369wml.38.1686473997621; Sun, 11 Jun 2023 01:59:57 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 16/26] target/arm/tcg: Reduce 'helper-sve.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:36 +0200 Message-Id: <20230611085846.21415-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474278133100003 Instead of including helper-sve.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/sve_helper.c | 4 ++++ target/arm/tcg/translate-sme.c | 4 ++++ target/arm/tcg/translate-sve.c | 5 +++++ target/arm/tcg/vec_helper.c | 4 ++++ 5 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 444be99c96..134d428175 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -539,7 +539,6 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, =20 #ifdef TARGET_AARCH64 #include "tcg/helper-a64.h.inc" -#include "tcg/helper-sve.h.inc" #include "tcg/helper-sme.h.inc" #endif =20 diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 8a0d966aae..79a42af591 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -33,6 +33,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Return a value for NZCV as per the ARM PredTest pseudofunction. * * The return value has bit 31 set if N is set, bit 1 set if Z is clear, diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 24796e5d9e..e63b9883a9 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -25,6 +25,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + /* * Include the generated decoder. */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index ff050626e6..45a36760fd 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -22,6 +22,11 @@ #include "translate-a64.h" #include "fpu/softfloat.h" =20 +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H =20 typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, uint32_t, uint32_t); diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index af325577f0..d93960198f 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -33,6 +33,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474417; cv=none; d=zohomail.com; s=zohoarc; b=Q3ECBS6OHscnbP7vjdTzuEtOG3SBnCAsJqvXHeDSCxao/TF97eKMl/XQ14r+pZUctuiXqzyQpdGhAtX61NBidT8iMOX/Q6GO0GnJtSYyadCCx5OuPI2oN/AUu0kO/eaby3UYX7pqp/zxFk6z5tkkSOWKXh8bKfDqn5qrhtyFqM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474417; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=btom/u1hZkX8UjQkUT1e66Oa9l3yd2W6yx3XFKKVFxk=; b=KaYAu9TSyfkCHS7wzk1ksX0Hfh4zDpF5r/3eBXaSf3JkyQmWRcGpaYhk/UWuX7eGCdCM+XmrJA/AwievKjsaanpX7svBMPgdmVDdF5guLSBbLlgD2RPWCkfHrVVg5ew4QKRdv81U2YuGiMq6hr/IbI31qqpf+e/iCR+eRaC5P3s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168647441769243.31682752345057; Sun, 11 Jun 2023 02:06:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8GxW-0004UR-Bl; Sun, 11 Jun 2023 05:02:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gvg-0002fl-QD for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:15 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gvc-0003oM-VC for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:06 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-30fbf6603d2so125911f8f.0 for ; Sun, 11 Jun 2023 02:00:03 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id cr5-20020a05600004e500b0030c6751a49dsm9070871wrb.115.2023.06.11.02.00.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686474002; x=1689066002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=btom/u1hZkX8UjQkUT1e66Oa9l3yd2W6yx3XFKKVFxk=; b=WBikaPQO1TstEK7K2PjFrb1eYs8oL0HBtvj5KQKxNj6x0QBlOzZU87/x8IC6iqMqKP R4hsQYLfLPHItor73LkzF3hSdAbCD0nvVt7kSlnAhXfGCvLpZveQWjeHPxOqxRSczeWS umVGj65oO96m+mXZ/K+M0M/PKAe7/ZpyNG0KJF6H9Y6IKSCB15LjTtZ5fmmfzgke6Sko AtTkDoezZ2J97S+d5UcD28WawD8BrFL+5goYaDx9EaY37tucBKee3A0fWzMyCtdEqnOM xVQPhJAHdgmLHtUxpxX/rGI0Qj+iq2NIQGeh8wWCn/w9kewqSFcAzvq63WTv6eiauwX4 RsvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686474002; x=1689066002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=btom/u1hZkX8UjQkUT1e66Oa9l3yd2W6yx3XFKKVFxk=; b=iZYioWqbwZDIKVS+61iBGj8/NThBgzOUOFTsBvUZyXal4NC+5cL9A4IOUGl6l6gicq IUqNMM6qpHJDXpzolJr2+SF+reRqPU8cGHVHicKLM9V4YmrAgEUqLdnEqTNAfrQ8jl97 vqbjhcahcca5jIfFbf5+j2lsFHFGykcIsW9CEij4AOaRFF7YoPBS4AA8OuTgHYY49YGg Wngq6vI/zec1O03y16duL77gX+3oVodV93VszKg36yDf+U/Khj2nWojFlDmSMXnYDmI7 wiJVCP7f/ocpwHogrIqrjWn9ac+NWCZRTQNZK+sBk1qcZkjeY9XahA5kVM8orw7KVJZ9 6mMg== X-Gm-Message-State: AC+VfDxqe6p+B89AXS3sL73vOdF0Jfd0uiD6AUX7cwbWyMwTNHkGnEvp S6aqonTwUbcoQMGh/Aae7k99Fgz6c1qBGVzkBjM= X-Google-Smtp-Source: ACHHUZ4aD+Nir/NhYWpz/IcJAc8FW3CPUJaSm4XXvhh8OnfUm9F0d2S9+M9LHYs4HFri/bj3nPHQnA== X-Received: by 2002:a5d:6682:0:b0:30f:bafb:2469 with SMTP id l2-20020a5d6682000000b0030fbafb2469mr1238430wru.53.1686474001951; Sun, 11 Jun 2023 02:00:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 17/26] target/arm/tcg: Reduce 'helper-mve.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:37 +0200 Message-Id: <20230611085846.21415-18-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474418210100001 Instead of including helper-mve.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/tcg/mve_helper.c | 5 ++++- target/arm/tcg/translate-mve.c | 6 ++++++ target/arm/tcg/translate.c | 4 ++++ 4 files changed, 14 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 134d428175..61cd8fd21e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -541,5 +541,3 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-a64.h.inc" #include "tcg/helper-sme.h.inc" #endif - -#include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index d8ba5a9e60..a3fca486e0 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internals.h" #include "vec_internal.h" -#include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "tcg/tcg.h" @@ -31,6 +30,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-mve.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static uint16_t mve_eci_mask(CPUARMState *env) { /* diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index bbc7b3f4ce..8577dc4377 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -21,6 +21,12 @@ #include "translate.h" #include "translate-a32.h" =20 +#define HELPER_H "tcg/helper-mve.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + static inline int vidup_imm(DisasContext *s, int x) { return 1 << x; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 2b3951cece..d88b355230 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -33,6 +33,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-mve.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474326; cv=none; d=zohomail.com; s=zohoarc; b=SzoRIfE+7Zl3Mc0KI6nkZA7wvPKhdNjl9IPpG+fD2POW6jFoaL+YNQO+utBAL47IbnYFB7uqcI6ujJsK9gNgr3HXUnhn3UqvKFXFcjlXLBhLbGYxfI3hxxFXREEVFneFMIzPs3nxw0OPj12vkyPmxRbJJfHapy7OQ150pr81HSc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474326; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6fgvCMeWGWtzi1ogVNS3n2ceF5EfOYaR43hCpswXEso=; b=WLEOl+GTojAMiubEvvBTllJsKElSi/sm+nfGD7PWFFeq+feQVgAN0QpkVLMSVOKwA0RgUQtJU44bWBrjYgcLEDG9meKf+DrrgMiOYHHNJgpclpO+3b89uMlH2MOkefhtNamubtUVKcbP5GobqBL0/rHLi4DXykMaIZ4x4fZwqUk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474326835344.4244217188892; Sun, 11 Jun 2023 02:05:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gxj-0005dE-Qq; Sun, 11 Jun 2023 05:02:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gvk-0002hr-7Y for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:19 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gvg-000401-Ef for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:11 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-30af56f5f52so2111512f8f.1 for ; Sun, 11 Jun 2023 02:00:07 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id d17-20020adffbd1000000b0030fb4b55c13sm3028336wrs.96.2023.06.11.02.00.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686474006; x=1689066006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6fgvCMeWGWtzi1ogVNS3n2ceF5EfOYaR43hCpswXEso=; b=j/qXLV/9sVhsCh+/pKikW540b9dVvIF3Gz9WWELqLKNQlKcGmEF5gPf7nAgeWOgq47 XoXJP28L1REftwOig/rwqZGN8S0/Wu172rPjgq4sllTA6cpMDWLhAjS5GItSRC3N/gTt SstZ5wQhZtF6QGFoEvIhbcsWfnqDAT0UzPDZL4jz+Bfqnx9URfWKFvayiIdZg+/EPAXN ZIFAhK2cBbJ9X8/UdCquuy4MkCyavks7G8IDoLu9EDB2BoEb0L27vGpMYv8NLTG2hLNu h1/+QAe9Zhk8KrGMCfVz7end6nU3woQqAh+QmD6Q38wyDJv2kJIohIzdNtFwSwa274lg ewug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686474006; x=1689066006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6fgvCMeWGWtzi1ogVNS3n2ceF5EfOYaR43hCpswXEso=; b=KDKNVGJxiaKNZ/e+BtCU8kvClaoer0DksXlzvz0b9Uyp54hOZhsuHRfGH9He0tISQJ 59QVzRUXsYGgygjuKI1oHuZdUDqO19q0lTW+JNP9PkW8CO7H9JnOZmk7kYC6zU0mW8iD J6+K3QkXRhBMZvvk2VcXj4JuToGc38Juh7VClcKzTSuzFkRbym86CFZvouHVV2vcryMR e+OAL0YJkJVDRXWJKV+VBJKQph97E8/lMhDU4FGI/E1IBUE2RisVjHWViOeo18E3+dhu 98U1iLnyFNtL60GkL6LfEBw1gvls4OqRA8e1+G09c9Bb1qY5IN4wD0sbZ3qqrH3FhK+J joEQ== X-Gm-Message-State: AC+VfDxb+riMjmaOdONg66WKZVhWSzt5LwGUc2qderLTRNeRi4B8z56A CyflSbgWFEuNV9wmr8gFlO0GN9DT6MnCX/MKPdw= X-Google-Smtp-Source: ACHHUZ5iO9zuLrN6TJoL+lJmI+a3Plt2MDM6WR8WDENIVtQxFvacvManeZ7zSAuZBjXGvoFMThvyGA== X-Received: by 2002:a5d:5491:0:b0:30f:bb97:37e8 with SMTP id h17-20020a5d5491000000b0030fbb9737e8mr916769wrv.47.1686474006262; Sun, 11 Jun 2023 02:00:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 18/26] target/arm/tcg: Reduce 'helper-sme.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:38 +0200 Message-Id: <20230611085846.21415-19-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474327433100002 Instead of including helper-sme.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/sme_helper.c | 5 ++++- target/arm/tcg/translate-a64.c | 4 ++++ target/arm/tcg/translate-sme.c | 6 ++++++ 4 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 61cd8fd21e..b7201eb89c 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -539,5 +539,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, =20 #ifdef TARGET_AARCH64 #include "tcg/helper-a64.h.inc" -#include "tcg/helper-sme.h.inc" #endif diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 1e67fcac30..04170ad18d 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internals.h" #include "tcg/tcg-gvec-desc.h" -#include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" @@ -29,6 +28,10 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" =20 +#define HELPER_H "tcg/helper-sme.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + void helper_set_svcr(CPUARMState *env, uint32_t val, uint32_t mask) { aarch64_set_svcr(env, val, mask); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 22caf89bb0..d1ab1edf6d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -34,6 +34,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-sme.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; =20 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e63b9883a9..fa0dc20bf2 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-sme.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* * Include the generated decoder. */ --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474305; cv=none; d=zohomail.com; s=zohoarc; b=bjXarlpXBA7k3aDGoKXaQggi1uk2OXUr17+k6sbJOJUmpzIpLP50Qgjn04cVWbNhlBFQVyyY7qTNblBNVJgK8aYPVzKovwdSe+Qklp30LLFoQAMtKn48bvyhDzgVwKHSzhvf3ZeEkuMPfotZyEjmXgvn9rMsBXhk0ir9hKS5apw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474305; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JMWaSEeC21286qg08dnBXfstMJP9JJH0vEjQ7Wn/jbk=; b=XXh9EZ3OmvaOtNY2mGfsDKQLRhl3TGyJE9qf5KpM1d81nkU2gHNxtbvSJ+BADVTNWtQ1jh1ggrHoWibeYG07QAtcdRxQAc2DNid6Hl+b2GJ1Zjz5xVnGK+ubgnDdJLZkmkmp0JKa7Wftt8f3JQgW4aR6mz04NpYS0ApKCL6dNw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474305396102.99546326054394; Sun, 11 Jun 2023 02:05:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gwh-0003iz-Ec; Sun, 11 Jun 2023 05:01:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gvn-0002iV-Uk for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:19 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gvl-00041C-FQ for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:15 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f6d3f83d0cso33983065e9.2 for ; Sun, 11 Jun 2023 02:00:11 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id h17-20020a05600c28d100b003f080b2f9f4sm7895759wmd.27.2023.06.11.02.00.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686474011; x=1689066011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JMWaSEeC21286qg08dnBXfstMJP9JJH0vEjQ7Wn/jbk=; b=EbpgekJsiQZYZ/R2odpsxmHdAEsV8Y3uyOTPwDsDRv74HougKNUPFsh8DzW9wcnwyp pI3+kYYbXh0JF5hNED4YatHWAzpDMkDwIKrLvT1lLPzM/urmUJvHbA619JPlP8w5prOR VCpvbOkjxYMX4IQC/CmLxfcT2WMS7NjbhOLt+17+elu5rC/p22SU2qhyNTP4TVtjexgv GSdpRs09FKU75Yz6PHuMpHdXAnN+Pc0FzIL+Z+ODRal/Xyda4nfQG9BSAJqF4dfxBh6A k3EtHaUZXOA3S/zkc4J4tsH/kfHEKKf7zv60VcXUh2h0DIyaKZmi/NbGI/4/DYexxGeD EI8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686474011; x=1689066011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JMWaSEeC21286qg08dnBXfstMJP9JJH0vEjQ7Wn/jbk=; b=C9L5kiByubfKKMdOzoXBFCCsO7hHXheMtxuVBMA5OPkoFF6L5m69UY3N1fGIF9HzuN Vy9eyJHe59j7/QLOwDWRTIWNtrULxSYHHldsoPkRhvIQKlD5e7bAsitu4OiUz+vuzxsF weDawEbFz3u2H7NluCr6XeZezubK+EB4rNMJ1pULkTyKzxlqPnSBbDz49Bl6ZxRtCTjB g7wOdSqpSMgOQLkZGNgTMXepYymzbhF5OGX3XF6+tHvSc0XfIQuOc1Rpw/Qn1jsaK4vC owFX1jVShMQl29BuIpli6C1FlJgGPc5ksfnKV4uXkjjdDG0Y48D9VE+2gfqyS67HNFyP rIzQ== X-Gm-Message-State: AC+VfDyc0/0xD5EcFBbHVAFjjlct4grTUBgzzfW5v7AhiZy2QowrEyIH tYxH+rzE6k5BBeEDeGZfgS8S6CykDWNDu0sDos8= X-Google-Smtp-Source: ACHHUZ5Do8M2CQyMM4GT6D96gXMWkBBo0axG3Pvhrm9KBbG5CgSQaAt4jHIoBIVdhPbf7G7jnsKeNg== X-Received: by 2002:a7b:c8d3:0:b0:3f7:f584:5792 with SMTP id f19-20020a7bc8d3000000b003f7f5845792mr5269513wml.0.1686474010623; Sun, 11 Jun 2023 02:00:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 19/26] target/arm/tcg: Reduce 'helper-a64.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:39 +0200 Message-Id: <20230611085846.21415-20-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474307364100007 Instead of including helper-a64.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 4 ---- target/arm/tcg/helper-a64.c | 4 ++++ target/arm/tcg/mte_helper.c | 4 +++- target/arm/tcg/pauth_helper.c | 4 +++- target/arm/tcg/sve_helper.c | 5 ++++- target/arm/tcg/translate-a64.c | 6 ++++++ target/arm/tcg/vec_helper.c | 4 ++++ 7 files changed, 24 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b7201eb89c..71e2cd5580 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -536,7 +536,3 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) - -#ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h.inc" -#endif diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 1c9370f07b..86133c6e0d 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -35,6 +35,10 @@ #include "fpu/softfloat.h" #include /* For crc32 */ =20 +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* C2.4.7 Multiply and divide */ /* special cases for 0 and LLONG_MIN are mandated by the standard */ uint64_t HELPER(udiv64)(uint64_t num, uint64_t den) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9c64def081..f29715869f 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -24,11 +24,13 @@ #include "exec/exec-all.h" #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" -#include "exec/helper-proto.h" #include "hw/core/tcg-cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" =20 +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H =20 static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) { diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 62af569341..3a8f0d820f 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -22,10 +22,12 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" =20 +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H =20 static uint64_t pac_cell_shuffle(uint64_t i) { diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 79a42af591..64f744bf6a 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" @@ -37,6 +36,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Return a value for NZCV as per the ARM PredTest pseudofunction. * * The return value has bit 31 set if N is set, bit 1 set if Z is clear, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d1ab1edf6d..6047f07f8c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -38,6 +38,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; =20 diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index d93960198f..9dd7e0f5e1 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -37,6 +37,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474306; cv=none; d=zohomail.com; s=zohoarc; b=e+UOdkW9dMU8Inhq4nl8phDU8YrvoCnmRtL2XJ9ODKretzU28nd5MssHga00XhrUN96Wcg1bn8bk4iyeLIyK9BJvmRVm+otGPAo1W/njrr7SZACWbp09DgY8rlb+NkO2ic/XPGWUEMOiONhuyF72ReCeYVVbX3hS4Z37lZsI578= ARC-Message-Signature: i=1; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id u5-20020a5d5145000000b0030fa57d8064sm5842041wrt.52.2023.06.11.02.00.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686474015; x=1689066015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TyRRQl63EjUwf6nuHb///9HEwrhn3HTdxj4GOGWSaio=; b=wFALolBSDATXLAJZVy/5VIIHEKz6MtJ4Oo6FQJUB+5nDrq+KEN5DiyDI6EJlSwLAaT fj8VUBclM/4BP3MoSOiwGOMrHMFvfVVnE+nidosA3fVEsCPggsO40vArzPMWXHmxaihF RbZbz27aKCCfK/vrDMIW/FO9QzXpFLK+bLBH4rC6P+2CUz9FQpwPwfT93abSrDWclrBV roFycHxq5Ji56xFVMC2OetkezCi0Wfr06M/Od5T4ZbaCJgb0OqSMvb+dmET6EOiuKEeZ f6NKLV3bm473qj4aiyp3Q4WKzA1rB7z6URXN811+jCUW6GpJ3tWboJqR00+IQX8M/kgI qAmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686474015; x=1689066015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TyRRQl63EjUwf6nuHb///9HEwrhn3HTdxj4GOGWSaio=; b=Kh1hFcc8oe4ckrQsOfhrpj0fPjOo3+bw5xeARypsc7p4d0cB3AzhwMDaEhZXmoDJEz s32JnzPp2109pzHXTWU0RcQ2Szo5LwbXOcWmcDcOrgYAkbCXtfLo0HlTrtIRN5Nn0jIY pXi5qKlkNCZh5thxthads0Ama30xvjDSqrG3e9Ui5Y7NBrvjnqcm9CJoevqM7nDLEiD2 zWf61/+1WefULpi5TtSdcziuUHwXHEwzABezVzB35PU9nE+iV+4/K+e2N5EI/FpEA80z QGPQzkJwD2cwAwxxkFLVQPbCZCA8onEObY5RAGLixLV/rtGZSyUgxvk/V6bzJ5KSE4Wo 2//g== X-Gm-Message-State: AC+VfDwQZRGzfIbFXp21Va6j5SaJV8WQ28nMKmAeKbsbbgcbY11DE8QA XBfXvFeepfTR5DFMuIuczD/jy6NyAq25JGroYys= X-Google-Smtp-Source: ACHHUZ75ZjLLQfBWYfV48x3geI/Q/YP6UC5aeKT2Hw/IrhB1aabzN9evzeSipV3IirlSI5YvMvikXA== X-Received: by 2002:a7b:c7d4:0:b0:3f6:389:73b1 with SMTP id z20-20020a7bc7d4000000b003f6038973b1mr3909544wmk.6.1686474014917; Sun, 11 Jun 2023 02:00:14 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 20/26] target/arm/tcg: Move v8m_stackcheck() from op_helper.c to m_helper.c Date: Sun, 11 Jun 2023 10:58:40 +0200 Message-Id: <20230611085846.21415-21-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474308344100011 No need to have the v8m_stackcheck() helper in the generic op_helper.c, move it with the rest of the M-profile helpers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/m_helper.c | 16 ++++++++++++++++ target/arm/tcg/op_helper.c | 16 ---------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 0891acc29c..0780bb3dea 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2893,3 +2893,19 @@ uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool = secure, bool threadmode, } } } + +void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) +{ + /* + * Perform the v8M stack limit check for SP updates from translated co= de, + * raising an exception if the limit is breached. + */ + if (newvalue < v7m_sp_limit(env)) { + /* + * Stack limit exceptions are a rare case, so rather than syncing + * PC/condbits before the call, we use raise_exception_ra() so + * that cpu_restore_state() will sort them out. + */ + raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); + } +} diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 70a9c37b74..04a90e3e3a 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -82,22 +82,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, raise_exception(env, excp, syndrome, target_el); } =20 -void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) -{ - /* - * Perform the v8M stack limit check for SP updates from translated co= de, - * raising an exception if the limit is breached. - */ - if (newvalue < v7m_sp_limit(env)) { - /* - * Stack limit exceptions are a rare case, so rather than syncing - * PC/condbits before the call, we use raise_exception_ra() so - * that cpu_restore_state() will sort them out. - */ - raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); - } -} - uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res =3D a + b; --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474178; cv=none; d=zohomail.com; s=zohoarc; b=VKHmyBcnKhk+17isebdA6vdQoFYZWcg9nxX7vtsmV4QYtFyLvKBKsQk9642Y2NZCvCPpIK2ugicnv6L4VXpp8PHLX8saNvZ/ooSQt6dstj/VKFlxv+Vt+b1qW0TOuY4IG3vXMP8ODnT0ijnILpKiXqDl8tWjhhwgTqCJkbv1bp0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474178; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sFrqSxuYHrI3cS6SOens6cMF97H9CMcbIb+bhGC3+VE=; b=K9acUctD0Zto6UGDe5BtNodZkMsZxEaw5aXrmpRD2OeKLbCffZZywcIH+rr5maR6AezP84A3hCT5rcTEYI0l3u1FdiVJBd67b6HleJnOU2+URjhljFfu/HxCsjFYxwYRO4nriABXfaNc1IDjLagb+y3EiTSimfMpgp5eSPCn8sU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16864741785011016.9761044868801; Sun, 11 Jun 2023 02:02:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gxa-00058F-DQ; Sun, 11 Jun 2023 05:02:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gvu-0002oz-Qc for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:24 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gvt-00043K-05 for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:22 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-307d20548adso2161258f8f.0 for ; Sun, 11 Jun 2023 02:00:20 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. [91.163.26.170]) by smtp.gmail.com with ESMTPSA id m11-20020a5d6a0b000000b0030b5d203e7esm9088473wru.97.2023.06.11.02.00.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686474019; x=1689066019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sFrqSxuYHrI3cS6SOens6cMF97H9CMcbIb+bhGC3+VE=; b=Amm+rujTZFaiFRW1MTIaW1l3ApJ8Nu10NtTmtnrVAs33pd0UPuDF+PfyhZ2XRW2oL4 VTHY5cHRIwviP1IdNOeK3rRvLzxTFsjePuSgw7wICl6bLOT3qKnyrJSoCJc8gNaQAdvp vmXzMcYnvrBJ5kv5AovsA/Hdoojjosp6SH7qaA8ydARzsR8ICT6IJskImN6CzW3HXEDC 4rzhNFx9JiNQfUwg8NO+01T/pL4uBTHC6tN+6Lco3SG4HlgWdBFDdpkFq14BRhyNZSTg mEkhTs5rXhbkAmMg8MoRiXzlhbh4q0WgGkMdlkCqHXbe12zalueR0mF/qEQqwt/gVisC 7vgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686474019; x=1689066019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sFrqSxuYHrI3cS6SOens6cMF97H9CMcbIb+bhGC3+VE=; b=WgsoCwNJn7neHPhmvgkZFqrNbNRvnQ7OZoHaPERMTq12jWCLEpKX2EpfQ31olRD5tT 6ilzbID0ttcA1MyT6mhNPIM85EWOGCSDKWuvjHcwCx713EWoVRBM10wYm3CLtboTVrbK h7QOgya8RV0LKTfe1URcRm7/EGvMdklqzzExNyctxlVuRgQeBy9sdn7mPirtzQuOq8tb mnxVQLuR3XE+r7PphvSJftXOsaVJZGJwuHbj85qI/cQJp0uUVfYA+1OsRoklveLsB7oI AK5NiJtDmcMxtkLvYzKcUumx+ANck8RnjFneHWP/+Mvdvgag0mAlroS68DJ8BuJjsFaJ PWjA== X-Gm-Message-State: AC+VfDyoja1g1e91RSVrcA72Cx0Am+vKvrKyZfPxfIVCEagkKr73Vu9B y//pTu+exgbC5NQbkPvjbCzE+tYxbwXTXCDsOnU= X-Google-Smtp-Source: ACHHUZ7mzGzQM8cr0kUO4vyT/veifMhsLbQpQ5CLWE3vLHIRKF2ZDkhbsieHp4lzmHxUQjrF6Vp3rQ== X-Received: by 2002:adf:f6c8:0:b0:309:50e7:7d0 with SMTP id y8-20020adff6c8000000b0030950e707d0mr2664023wrp.31.1686474019087; Sun, 11 Jun 2023 02:00:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 21/26] target/arm/tcg: Extract M-profile definitions to 'helper-m.h.inc' Date: Sun, 11 Jun 2023 10:58:41 +0200 Message-Id: <20230611085846.21415-22-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474179726100001 helper.h is used by all units, but not all require the M-profile definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 17 ++--------------- target/arm/tcg/helper-m.h.inc | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+), 15 deletions(-) create mode 100644 target/arm/tcg/helper-m.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index 71e2cd5580..05117934f3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -62,21 +62,6 @@ DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) DEF_HELPER_1(cpsr_read, i32, env) =20 -DEF_HELPER_3(v7m_msr, void, env, i32, i32) -DEF_HELPER_2(v7m_mrs, i32, env, i32) - -DEF_HELPER_2(v7m_bxns, void, env, i32) -DEF_HELPER_2(v7m_blxns, void, env, i32) - -DEF_HELPER_3(v7m_tt, i32, env, i32, i32) - -DEF_HELPER_1(v7m_preserve_fp_state, void, env) - -DEF_HELPER_2(v7m_vlstm, void, env, i32) -DEF_HELPER_2(v7m_vlldm, void, env, i32) - -DEF_HELPER_2(v8m_stackcheck, void, env, i32) - DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32) =20 DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) @@ -536,3 +521,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +#include "tcg/helper-m.h.inc" diff --git a/target/arm/tcg/helper-m.h.inc b/target/arm/tcg/helper-m.h.inc new file mode 100644 index 0000000000..122311b6d0 --- /dev/null +++ b/target/arm/tcg/helper-m.h.inc @@ -0,0 +1,23 @@ +/* + * ARM M-profile helper definitions + * + * Copyright (c) 2007 CodeSourcery. + * Written by Paul Brook + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +DEF_HELPER_3(v7m_msr, void, env, i32, i32) +DEF_HELPER_2(v7m_mrs, i32, env, i32) + +DEF_HELPER_2(v7m_bxns, void, env, i32) +DEF_HELPER_2(v7m_blxns, void, env, i32) + +DEF_HELPER_3(v7m_tt, i32, env, i32, i32) + +DEF_HELPER_1(v7m_preserve_fp_state, void, env) + +DEF_HELPER_2(v7m_vlstm, void, env, i32) +DEF_HELPER_2(v7m_vlldm, void, env, i32) + +DEF_HELPER_2(v8m_stackcheck, void, env, i32) --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474144; cv=none; d=zohomail.com; s=zohoarc; b=T/jr2Mxj9cO+6VEhISr2gE2KfwkFqmsTAPvJvcihNXpLDGhY5jCEMiVfBFru9H5T01a26crDevFPWdlIcJlVO2m5/H+iiep0I7NCKuhCUJXLL52va3Epb1h9A44yXNMbny0xFq4o08cGhf/eMHkV15/Kd0jH5pKNQXn46skCXsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474144; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q/kuWTPxcHL3QCO5m7VZbZfFT5tI+SpH0RGLuwEKATs=; b=f2ZVWa9mPyneUGarJKwfd5hjkD8NtqA0eoYI1DNWOMrxexCsCldD6YWIU2535vb0QSJb6JkFMG3REGuhbb2GMFsNHI5cR4JH2Cftwf68tM8snN/c2GhakjU28Jy6c4Q00LFhvtRmiI29eH7Zygn6jXhVvnECF3IoG4Nlj/l3pL4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474144593216.0078196954929; Sun, 11 Jun 2023 02:02:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gxk-0005f3-5J; Sun, 11 Jun 2023 05:02:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gvy-0002tM-NJ for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:30 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gvw-00044I-QA for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:26 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f6d7abe9a4so23238015e9.2 for ; Sun, 11 Jun 2023 02:00:24 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/tcg/m_helper.c | 4 ++++ target/arm/tcg/translate-m-nocp.c | 6 ++++++ target/arm/tcg/translate-vfp.c | 4 ++++ target/arm/tcg/translate.c | 5 +++++ 5 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 05117934f3..37f9879b95 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -521,5 +521,3 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) - -#include "tcg/helper-m.h.inc" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 0780bb3dea..45568d96bb 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -21,6 +21,10 @@ #include "hw/intc/armv7m_nvic.h" #endif =20 +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) { diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m= -nocp.c index 7343945b41..ee9c296a98 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -25,6 +25,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* Include the generated decoder */ #include "decode-m-nocp.c.inc" =20 diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 10d4502239..7d36a06726 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -24,6 +24,10 @@ #include "translate.h" #include "translate-a32.h" =20 +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-vfp.h.inc" #include "exec/helper-proto.h.inc" #include "exec/helper-gen.h.inc" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index d88b355230..0e692f45f8 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -37,6 +37,11 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474357; cv=none; d=zohomail.com; s=zohoarc; b=HEUFkx0DAjzu/iLAKQzY7yMInmW2qTQKNT+qgIEZ1QLI5FUokzXLlT+OUP4xfJ41QvKbaF8htf0ImyUUSoAqtYZKCpO47ZXsd179J3IhH6G6sqoWO+1vp8y4hDrmmVXqTujtb9C/bZUPCSljmJ7TsMF6sfkPmyQvRaMkUiJeSC8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686474357; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7bOi95+MAdYOQf36lFFFxG4Odq562AhoTTqq539rW9I=; b=Yeq7Dexs0luIfYyVq78ZPZCs1c8epV9ovkToDIAUr8pqefTPyeNUfJG+xJKFRRktFkikuAv1N7ERuFqFaBDyYD/Y6eSInnSssz3NVqJuuw1PWYN6vMaKFmdzpoXh9j77Y558y9KsTIuXMY32VNmyvLzt+r/JHGzOZeK68O21Y5c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686474357690196.28022506960372; Sun, 11 Jun 2023 02:05:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8Gxp-0006R6-SF; Sun, 11 Jun 2023 05:02:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8Gw4-000368-T4 for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:33 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8Gw2-00046U-97 for qemu-devel@nongnu.org; Sun, 11 Jun 2023 05:00:32 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-30fbcfdc7b6so131086f8f.3 for ; Sun, 11 Jun 2023 02:00:28 -0700 (PDT) Received: from localhost.localdomain (91-163-26-170.subs.proxad.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474358629100003 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- CHECK: By extracting some inlined (FP) helpers from translate.h, we could reduce 'helper-gen.h.inc' to helper.c. --- target/arm/tcg/translate.h | 4 +++- target/arm/helper.c | 5 +++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3d7c55d3b6..fc6357eae8 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -6,9 +6,11 @@ #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" #include "exec/translator.h" -#include "exec/helper-gen.h" #include "internals.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H =20 /* internal defines */ =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index d4bee43bd0..89ee68893f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -26,6 +26,11 @@ #include "qapi/error.h" #include "qemu/guest-random.h" #ifdef CONFIG_TCG + +#define HELPER_H "helper.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #include "semihosting/common-semi.h" #endif #include "cpregs.h" --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474427913100002 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- This mean we can extract more tcg/helper-foo.h.inc, maybe: - gvec / simd / crypto - exception / wfi --- target/arm/debug_helper.c | 6 +++++- target/arm/helper.c | 2 +- target/arm/tcg/crypto_helper.c | 5 ++++- target/arm/tcg/helper-a64.c | 5 ++++- target/arm/tcg/hflags.c | 5 ++++- target/arm/tcg/m_helper.c | 5 ++++- target/arm/tcg/op_helper.c | 5 ++++- target/arm/tcg/psci.c | 5 ++++- target/arm/tcg/tlb_helper.c | 4 +++- target/arm/tcg/translate.c | 2 +- target/arm/tcg/vec_helper.c | 5 ++++- target/arm/vfp_helper.c | 5 ++++- 12 files changed, 42 insertions(+), 12 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 8362462a07..31165b92a5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,10 +11,14 @@ #include "internals.h" #include "cpregs.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" #include "sysemu/tcg.h" =20 #ifdef CONFIG_TCG + +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 89ee68893f..523f7b7765 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11,7 +11,6 @@ #include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/timer.h" #include "qemu/bitops.h" @@ -28,6 +27,7 @@ #ifdef CONFIG_TCG =20 #define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" #include "exec/helper-gen.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index d28690321f..1b6b105527 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -12,12 +12,15 @@ #include "qemu/osdep.h" =20 #include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "crypto/aes.h" #include "crypto/sm4.h" #include "vec_internal.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + union CRYPTO_STATE { uint8_t bytes[16]; uint32_t words[4]; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 86133c6e0d..56c2f01532 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -21,7 +21,6 @@ #include "qemu/units.h" #include "cpu.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/main-loop.h" @@ -35,6 +34,10 @@ #include "fpu/softfloat.h" #include /* For crc32 */ =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-a64.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 616c5fa723..83a1aa08e4 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -8,9 +8,12 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "exec/helper-proto.h" #include "cpregs.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static inline bool fgt_svc(CPUARMState *env, int el) { /* diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 45568d96bb..1991eafe05 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -10,7 +10,6 @@ #include "cpu.h" #include "internals.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" #include "qemu/log.h" @@ -25,6 +24,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) { diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 04a90e3e3a..24205074cc 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -19,12 +19,15 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "cpregs.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 6c1239bb96..2822a6b96a 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -18,13 +18,16 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "kvm-consts.h" #include "qemu/main-loop.h" #include "sysemu/runstate.h" #include "internals.h" #include "arm-powerctl.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { /* diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 8df36c2cbf..e663aef2fd 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -9,8 +9,10 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H =20 /* * Returns true if the stage 1 translation regime is using LPAE format page diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 0e692f45f8..fc7a2804f7 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -27,7 +27,6 @@ #include "arm_ldst.h" #include "semihosting/semihost.h" #include "cpregs.h" -#include "exec/helper-proto.h" =20 #define HELPER_H "tcg/helper-neon.h.inc" #include "exec/helper-gen.h.inc" @@ -43,6 +42,7 @@ #undef HELPER_H =20 #define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" #include "exec/helper-info.c.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 9dd7e0f5e1..325a231de9 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -19,12 +19,15 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" #include "vec_internal.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-vfp.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index cbd78cc810..51f8e92ff7 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "internals.h" #ifdef CONFIG_TCG #include "qemu/log.h" @@ -32,6 +31,10 @@ =20 #ifdef CONFIG_TCG =20 +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-vfp.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id e7-20020a056000120700b0030af8da022dsm9093350wrx.44.2023.06.11.02.00.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686474036; x=1689066036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3c5LLgM8zqCm+VTMgGqUz6vtedxBGV45kgOdre73KRM=; b=Tv7At1gmt7VmV/BILMQQibm6etqqfIHfsQNL8jOqLkgVeMYpjdHmOqqESbyWFSxie8 pFV39qhZzQOvE4XdyBAokoIv35DlGiOxl5zraIgLguvKxHKOefeYjwDTNvbJxB29d8IE pj9Mhcs2a8ol/JlqzUyUYOg7onC+cRnFub0Io6FN7E27pKD9W+d5uuraWuOyGkj9an5f CJPND+lcOMjLsM6AQVDweOsy43w7+9LKyMp1C5g6qFvzQGoJBHL+5+zxkNvxBGCGo+2A dhm3+pnZNoGlfU4c0E7trdjHpa74u6rOc1fZRU2hIdFWHDBbTR8UCHKwvpflZRpmFR4Z DUiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686474036; x=1689066036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3c5LLgM8zqCm+VTMgGqUz6vtedxBGV45kgOdre73KRM=; b=aAb7rOhbUZYymFd6PZ5ORirZw6sQVwHBUIL2Q7Ru0FzvQ6vjz0mIoWaKdrEZ8iElT8 ezzmRmMhqkXWi7lXoMukcMm64xg4KTgpAgzYLV4N3/sBjas4LJPYHHaHgzvwIUa9qZNg Vd2SIvBiiHEnY/thZSzyJZuOy4VZiX39fOR3n5orJofZhVH7YfqD3Dx64FzbMxe6VOdG u3ZGxibJ7CV6hZZOZzbHT49KpOOwoYppRQnJzdBOKeRvlkWIbM2lAjNOKVPIL6V0HVPI U2SlNh9VfFrR4bW5LV2lzoRIOzgmelxejB8zBUmwMXtQkGgWKvtefSs/3nBNTOEbjROp OkAw== X-Gm-Message-State: AC+VfDw795LjjjVeNp5NogUB4mfX3FrCZVTu1U6LahUF0K7MBKf0JO6f 3qJzCIQmKpRAashYsj+5MxE9nNJudNWWekRKSc4= X-Google-Smtp-Source: ACHHUZ7pv3NKIvjh/8ZmWtUoMFgNX4PrRJNpueHmXJp3Jz06RCD5wCtmSFcPHWr/f5tJoq+WfVTc1Q== X-Received: by 2002:a5d:5543:0:b0:304:b967:956f with SMTP id g3-20020a5d5543000000b00304b967956fmr2723982wrw.8.1686474036139; Sun, 11 Jun 2023 02:00:36 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 25/26] target/arm/tcg: Rename 'helper.h' -> 'tcg/helper.h.inc' Date: Sun, 11 Jun 2023 10:58:45 +0200 Message-Id: <20230611085846.21415-26-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474377889100003 Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'helper.h' as 'helper.h.inc'. Since this file is TCG-specific, move it to the tcg/ directory. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/translate.h | 2 +- target/arm/{helper.h =3D> tcg/helper.h.inc} | 0 target/arm/debug_helper.c | 2 +- target/arm/helper.c | 2 +- target/arm/tcg/crypto_helper.c | 2 +- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/hflags.c | 2 +- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/psci.c | 2 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/translate.c | 2 +- target/arm/tcg/vec_helper.c | 2 +- target/arm/vfp_helper.c | 2 +- 14 files changed, 13 insertions(+), 13 deletions(-) rename target/arm/{helper.h =3D> tcg/helper.h.inc} (100%) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index fc6357eae8..940347b6bd 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -8,7 +8,7 @@ #include "exec/translator.h" #include "internals.h" =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-gen.h.inc" #undef HELPER_H =20 diff --git a/target/arm/helper.h b/target/arm/tcg/helper.h.inc similarity index 100% rename from target/arm/helper.h rename to target/arm/tcg/helper.h.inc diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 31165b92a5..b32852e947 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -15,7 +15,7 @@ =20 #ifdef CONFIG_TCG =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 523f7b7765..2bdf7b0d4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -26,7 +26,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #include "exec/helper-gen.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 1b6b105527..15faa7455e 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -17,7 +17,7 @@ #include "crypto/sm4.h" #include "vec_internal.h" =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 56c2f01532..b8ee45074f 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -34,7 +34,7 @@ #include "fpu/softfloat.h" #include /* For crc32 */ =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 83a1aa08e4..e75cb0100e 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,7 +10,7 @@ #include "internals.h" #include "cpregs.h" =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 1991eafe05..4100161775 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 24205074cc..e1aadd63f0 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -24,7 +24,7 @@ #include "exec/cpu_ldst.h" #include "cpregs.h" =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 2822a6b96a..e00b9b1493 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -24,7 +24,7 @@ #include "internals.h" #include "arm-powerctl.h" =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index e663aef2fd..3f8cb358a6 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -10,7 +10,7 @@ #include "internals.h" #include "exec/exec-all.h" =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index fc7a2804f7..f44b9415ec 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -41,7 +41,7 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #include "exec/helper-info.c.inc" #undef HELPER_H diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 325a231de9..46f347a8c3 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -24,7 +24,7 @@ #include "qemu/int128.h" #include "vec_internal.h" =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 51f8e92ff7..38faf99073 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -31,7 +31,7 @@ =20 #ifdef CONFIG_TCG =20 -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H =20 --=20 2.38.1 From nobody Wed Feb 11 04:36:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686474356; cv=none; d=zohomail.com; s=zohoarc; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id v18-20020a5d43d2000000b0030ae93bd196sm9052286wrr.21.2023.06.11.02.00.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686474040; x=1689066040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R/F/L6gm+zkVK5EOXjzGUKkb1zlWJACWpFKWw3y8T80=; b=KMH4A5NVVpQqs0+u339v2qEHWKHSsqO0eHhvqtEv6XuXXum/KWS0MOkaqywQKG70KE nYWnbHXeVsMgLCyvux3JAetmGkz20tCCx6zJRbS61NB+0w1yIjRh4MdVq5QbwcueV4HW sOyPbv5MN6l6DySYx33HQLXck7okuMHImvz0O9MUJDj40r14WU73r3ACTC/qYzeccrDU LcBRGUtxkldoGv7yFAZk86i8UqgW/Nb/y2AX2jf1Jqd2gCW/He5ZiFXjN/kvZ7TWeZ7Q npTdwyNs5DwCxXbLasgzubfejF37koB8xhmj7bHvujujtkqd511lgm74nskdWFCnYtnZ bTbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686474040; x=1689066040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R/F/L6gm+zkVK5EOXjzGUKkb1zlWJACWpFKWw3y8T80=; b=fjyhgElbQJ3p3KXhUZz5TZwqfenFP8ATz6R3kgBmzZiqDhtQTPrdvpKVfNzWPTwNFG HSofwp3tMEXy7zT/8FuZfuZLNZUTJZj0b2ye5zirGemvWcxWrrJEHRKcknPaOynpkxPK D6y7qq5wfKiZ1wYOejaK6pWsZ3sh8LKeDU9Nvx9BXlHFi9AAJyLzxcpdhbgWq5wB4jmt mI23UPIVPsnuNcVXqc+xQFg8nTx2Qe5yUi6a26IlpgBl/C1+jzw5HTM5QzXjZS7zGWqn UKdryp/pFoCw6FfEY/y6iOcCBIdxwsyPhkGIHjR9wPjJoJlsaHupiyTorE7tIEqy1pWA U5/A== X-Gm-Message-State: AC+VfDzkoqbPKN4AHuwFfdeQwSf7EZnKVichoBtxSK+Dk3j1bAZO9fej P95gu9ix0uxbs0azVwAtHSCNYuTH4BxfeXfLb0o= X-Google-Smtp-Source: ACHHUZ4HEuH0fpMSXFeq2lM2+eohGzSGtm0VpsMnqzyocUpSDvVFBiNApLwC3wdz+ZaQ1SIdyLE99g== X-Received: by 2002:adf:f649:0:b0:30a:9014:838d with SMTP id x9-20020adff649000000b0030a9014838dmr2645906wrp.11.1686474040470; Sun, 11 Jun 2023 02:00:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 26/26] tests/tcg/aarch64: Rename bti-crt.inc.c -> bti-crt.c.inc Date: Sun, 11 Jun 2023 10:58:46 +0200 Message-Id: <20230611085846.21415-27-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686474357557100001 Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'bti-crt.inc.c' as 'bti-crt.c.inc'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tests/tcg/aarch64/bti-1.c | 2 +- tests/tcg/aarch64/bti-3.c | 2 +- tests/tcg/aarch64/{bti-crt.inc.c =3D> bti-crt.c.inc} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename tests/tcg/aarch64/{bti-crt.inc.c =3D> bti-crt.c.inc} (100%) diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c index 61924f0d7a..99a879af23 100644 --- a/tests/tcg/aarch64/bti-1.c +++ b/tests/tcg/aarch64/bti-1.c @@ -2,7 +2,7 @@ * Branch target identification, basic notskip cases. */ =20 -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" =20 static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c index a852856d9a..8c534c09d7 100644 --- a/tests/tcg/aarch64/bti-3.c +++ b/tests/tcg/aarch64/bti-3.c @@ -2,7 +2,7 @@ * BTI vs PACIASP */ =20 -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" =20 static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.c.= inc similarity index 100% rename from tests/tcg/aarch64/bti-crt.inc.c rename to tests/tcg/aarch64/bti-crt.c.inc --=20 2.38.1