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Date: Thu, 8 Jun 2023 00:23:14 -0700 Message-Id: <20230608072314.3561109-5-tommy.wu@sifive.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230608072314.3561109-1-tommy.wu@sifive.com> References: <20230608072314.3561109-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=tommy.wu@sifive.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1686209050494100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 12 +++++ target/riscv/op_helper.c | 49 +++++++++++++++++++ 4 files changed, 65 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 98e97810fd..00f1032086 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -112,6 +112,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 73d5d1b045..e0698f9dfb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -111,6 +111,9 @@ wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm =20 +# *** NMI *** +mnret 0111000 00010 00000 000 00000 1110011 + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 528baa1652..ef7f102069 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -104,6 +104,18 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } =20 +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_mnret(cpu_pc, cpu_env); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f563dc3981..b27beec871 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -359,6 +359,55 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } =20 +target_ulong helper_mnret(CPURISCVState *env) +{ + if (!riscv_cpu_cfg(env)->ext_smrnmi) { + /* RNMI feature is not presented. */ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + if (!(env->priv >=3D PRV_M)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + /* Get return PC from mnepc CSR. */ + target_ulong retpc =3D env->mnepc; + if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + } + + /* Get previous privilege level from mnstatus CSR. */ + target_ulong prev_priv =3D get_field(env->mnstatus, MNSTATUS_MNPP); + + if (riscv_cpu_cfg(env)->pmp && + !pmp_get_num_rules(env) && (prev_priv !=3D PRV_M)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + riscv_cpu_set_mode(env, prev_priv); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, true); + + target_ulong prev_virt =3D get_field(env->mnstatus, MNSTATUS_MNPV); + + /* + * If MNRET changes the privilege mode to a mode + * less privileged than M, it also sets mstatus.MPRV to 0. + */ + if (prev_priv < PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, false); + } + + if (riscv_has_ext(env, RVH)) { + if (prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_virt_enabled(env, prev_virt); + } + + return retpc; +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); --=20 2.31.1