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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v10-20020a5d4b0a000000b0030789698eebsm12134017wrq.89.2023.06.06.02.48.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 02:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686044910; x=1688636910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=shirMCVat1ANUxDCq/6z2swO2ZjovBkHEb+yOZF6W9E=; b=epwX0wZUqnlxJYjIzdqObgdNIPFwITyVnmHtaVElulMZrsXhvXUbFF55p+vkECoAZ8 tEHl93jh8Fq88Dy5P0klncyk9ToAetXKBkOFTNx2gR4bmyOofreIhL4po0UR5A7JWSHw q87Qu0qokqE5nDasNn9krkqwLhNW+pr0Fpj6RpcIumrbNvFBnEj4PhfDrdxjxZexn9Yz QyukcNxEOIlFjx17iQ6kBreHuquintQ51HZYxmN3WXOlHmP7OXaag6pZVIjOPpmE+YTL JhXJ0oos9tFvahsOdb8dI6G/8UpCgow7zsjMt512j6I6IoVzxJqJIIabujZmQ/yKXqem 0m/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686044910; x=1688636910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=shirMCVat1ANUxDCq/6z2swO2ZjovBkHEb+yOZF6W9E=; b=BdVNZWSigrhWZyiymCjdtP6qd8hfoC6uMRXBs9ImaJp5fGYml1GbQzbCjMcOgARLsV Hdl6yfbods0QF4TdmCmMVfT2UxjfnZLcQP0P4KcNez/+C4zVMAFJLcVR4jZmSZ5amapV vaPELsEh6/347psWMNVvzLjkJzomEoNvh1Aa/idExbvIwgmtrSMAg44/26NlkN+4CRal CPskKlppTxpeTba4esANoj67IkaLX2ECA/mY3IqrTcpsrZxzfocAXAlFnHKsmXXwqlPV 1a1nZr0BmFqWpQgerT3ja47/DT9ZG89s6/me8n8aasUB7p/0uOW0c1WY9kXH5F356VG1 bLmA== X-Gm-Message-State: AC+VfDzsRjf2luC7RVC230j6K6vcDVnR8YkHj1xXmeVF9iUEH8rPOEwU zJ/aMRE0GEhzQ8WyceTaB98+sdEG/CViY7Jh4uA= X-Google-Smtp-Source: ACHHUZ4xCVZz2/EVCKksqv/2khWdHTUpfgG49OYbymw9J1bU1q7cRK2c/CeelBZJBzJQXi2zOV9iDA== X-Received: by 2002:a05:600c:1d28:b0:3f7:6238:8103 with SMTP id l40-20020a05600c1d2800b003f762388103mr4973911wms.11.1686044909993; Tue, 06 Jun 2023 02:48:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/42] target/arm: Hoist finalize_memop out of do_gpr_{ld, st} Date: Tue, 6 Jun 2023 10:48:01 +0100 Message-Id: <20230606094814.3581397-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230606094814.3581397-1-peter.maydell@linaro.org> References: <20230606094814.3581397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686045256103100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20230530191438.411344-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 61 +++++++++++++++++++--------------- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 88183f9dca1..d90e8661ca5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -838,7 +838,6 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 = source, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - memop =3D finalize_memop(s, memop); tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop); =20 if (iss_valid) { @@ -873,7 +872,6 @@ static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 = dest, TCGv_i64 tcg_addr, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - memop =3D finalize_memop(s, memop); tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); =20 if (extend && (memop & MO_SIGN)) { @@ -2625,6 +2623,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr; + MemOp memop; =20 switch (o2_L_o1_o0) { case 0x0: /* STXR */ @@ -2661,10 +2660,11 @@ static void disas_ldst_excl(DisasContext *s, uint32= _t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, + do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 @@ -2679,10 +2679,11 @@ static void disas_ldst_excl(DisasContext *s, uint32= _t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, t= rue, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2790,9 +2791,9 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; + MemOp memop =3D finalize_memop(s, size + is_signed * MO_SIGN); =20 - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, - false, true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); } } =20 @@ -3046,7 +3047,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool post_index; bool writeback; int memidx; - + MemOp memop; TCGv_i64 clean_addr, dirty_addr; =20 if (is_vector) { @@ -3073,7 +3074,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3107,6 +3108,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } =20 memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); + clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, size, is_unpriv, memidx); @@ -3122,10 +3125,10 @@ static void disas_ldst_reg_imm9(DisasContext *s, ui= nt32_t insn, bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); =20 if (is_store) { - do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, + do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_= SIGN, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop, is_extended, memidx, iss_valid, rt, iss_sf, false); } @@ -3174,8 +3177,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, bool is_signed =3D false; bool is_store =3D false; bool is_extended =3D false; - TCGv_i64 tcg_rm, clean_addr, dirty_addr; + MemOp memop; =20 if (extract32(opt, 1, 1) =3D=3D 0) { unallocated_encoding(s); @@ -3202,7 +3205,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3215,6 +3218,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); + + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); =20 if (is_vector) { @@ -3226,11 +3231,12 @@ static void disas_ldst_reg_roffset(DisasContext *s,= uint32_t insn, } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); + if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + do_gpr_ld(s, tcg_rt, clean_addr, memop, is_extended, true, rt, iss_sf, false); } } @@ -3262,12 +3268,11 @@ static void disas_ldst_reg_unsigned_imm(DisasContex= t *s, uint32_t insn, int rn =3D extract32(insn, 5, 5); unsigned int imm12 =3D extract32(insn, 10, 12); unsigned int offset; - TCGv_i64 clean_addr, dirty_addr; - bool is_store; bool is_signed =3D false; bool is_extended =3D false; + MemOp memop; =20 if (is_vector) { size |=3D (opc & 2) << 1; @@ -3289,7 +3294,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3299,6 +3304,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); =20 if (is_vector) { @@ -3311,10 +3318,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext= *s, uint32_t insn, TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, - true, rt, iss_sf, false); + do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, fals= e); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + do_gpr_ld(s, tcg_rt, clean_addr, memop, is_extended, true, rt, iss_sf, false); } } @@ -3344,7 +3350,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, bool a =3D extract32(insn, 23, 1); TCGv_i64 tcg_rs, tcg_rt, clean_addr; AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D s->be_data | size | MO_ALIGN; + MemOp mop =3D finalize_memop(s, size | MO_ALIGN); =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { unallocated_encoding(s); @@ -3405,7 +3411,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, * full load-acquire (we only need "load-acquire processor consist= ent"), * but we choose to implement them as full LDAQ. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3451,6 +3457,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, bool use_key_a =3D !extract32(insn, 23, 1); int offset; TCGv_i64 clean_addr, dirty_addr, tcg_rt; + MemOp memop; =20 if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { unallocated_encoding(s); @@ -3477,12 +3484,14 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, offset =3D sextract32(offset << size, 0, 10 + size); tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 + memop =3D finalize_memop(s, size); + /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, is_wback || rn !=3D 31, size); =20 tcg_rt =3D cpu_reg(s, rt); - do_gpr_ld(s, tcg_rt, clean_addr, size, + do_gpr_ld(s, tcg_rt, clean_addr, memop, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); =20 @@ -3524,7 +3533,7 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) } =20 /* TODO: ARMv8.4-LSE SCTLR.nAA */ - mop =3D size | MO_ALIGN; + mop =3D finalize_memop(s, size | MO_ALIGN); =20 switch (opc) { case 0: /* STLURB */ --=20 2.34.1