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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v10-20020a5d4b0a000000b0030789698eebsm12134017wrq.89.2023.06.06.02.48.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 02:48:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686044904; x=1688636904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=husryfr8aoyZTxHtkzHPAjPwAMvj0JcrBa+W6jOb1To=; b=dYebCER2slljbpt+ORDvIwhMJ4O99r6LHP5vIPox9+Wfhs4pQFF/tvj8iqDl1PGejN tzIRZ4bxGHY4vq1m17UtLQ4lBjD/ZY0b5e9qW78zrCSZ7b8w5XkUpmQbenRBOcHF6vev cUnDNRo6R2rQQmV3Sb0sO0FwPfLaGc4sTCKFCX8RREpyjV4+d7/f1VyqyzJwXRrWqmcM MEQGr7yWkUxdjm8eCDmViGqK/2tq4wHjTbClIm7di/v0TVSE3XxnG6xjku2Ol6WR65ez t1lxzEnx6bG5Lp5RZsSmZ9z7c2oSMaDmUlVXvqsL/PaBu66nz6xMiowgiix3sYx7zggx OAmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686044904; x=1688636904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=husryfr8aoyZTxHtkzHPAjPwAMvj0JcrBa+W6jOb1To=; b=gQWyncmlTXa365H+G/LKkvoZJ4uhcFXHqCJHjl/8js6QMEFnUIevve/EBHLetWRLdA wugGjoJTz+nR1y3CdoLtQ4lSWB+rgIURtZ6F84YkGlK6cRRWSaU8ReL22olkws1qEIDw jScd8wRtSYNb1Gf1ldz71erElnG4DF29z5cghSW+pyPwQkHHEDpgzHFDL/Te/ItJLMDP zVl37K1nOC1rPGVr+95ue5P22lz0pF2uTDWVFe1Sp7F9FqeegXUDm0rN4KsYdKuCzC8J IjrJ7fKiqhlvZvuFeZoVjfK5P744CxNwieHB0a0uKyBeqn2ZYQmsoZkzl1W8cFyj6iLl Z8MA== X-Gm-Message-State: AC+VfDwZtzBr6LygyqFa9UX5QS771mn80wkX8YpgDSxcXl6XUwzUfJF3 I8FGwQzP1fC1vGLFUv1sXkFFHY+SSS046GuQ+vM= X-Google-Smtp-Source: ACHHUZ5gAYhogi0x4MkikA0M0F2kcJ/k/nY4ZINa97xhhz/YFRK0lTazwqdIO+P7ccPtlvp/qpoz3w== X-Received: by 2002:adf:e652:0:b0:309:3a60:d791 with SMTP id b18-20020adfe652000000b003093a60d791mr1599736wrn.54.1686044904632; Tue, 06 Jun 2023 02:48:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/42] hw: arm: allwinner-sramc: Add SRAM Controller support for R40 Date: Tue, 6 Jun 2023 10:47:49 +0100 Message-Id: <20230606094814.3581397-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230606094814.3581397-1-peter.maydell@linaro.org> References: <20230606094814.3581397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686045010464100001 Content-Type: text/plain; charset="utf-8" From: qianfan Zhao Only a few important registers are added, especially the SRAM_VER register. Signed-off-by: qianfan Zhao Reviewed-by: Niek Linnenbank Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-r40.h | 3 + include/hw/misc/allwinner-sramc.h | 69 +++++++++++ hw/arm/allwinner-r40.c | 7 +- hw/misc/allwinner-sramc.c | 184 ++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/trace-events | 4 + 8 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/allwinner-sramc.h create mode 100644 hw/misc/allwinner-sramc.c diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index 5f2d08489eb..72710d3edce 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -27,6 +27,7 @@ #include "hw/sd/allwinner-sdhost.h" #include "hw/misc/allwinner-r40-ccu.h" #include "hw/misc/allwinner-r40-dramc.h" +#include "hw/misc/allwinner-sramc.h" #include "hw/i2c/allwinner-i2c.h" #include "hw/net/allwinner_emac.h" #include "hw/net/allwinner-sun8i-emac.h" @@ -38,6 +39,7 @@ enum { AW_R40_DEV_SRAM_A2, AW_R40_DEV_SRAM_A3, AW_R40_DEV_SRAM_A4, + AW_R40_DEV_SRAMC, AW_R40_DEV_EMAC, AW_R40_DEV_MMC0, AW_R40_DEV_MMC1, @@ -102,6 +104,7 @@ struct AwR40State { =20 ARMCPU cpus[AW_R40_NUM_CPUS]; const hwaddr *memmap; + AwSRAMCState sramc; AwA10PITState timer; AwSdHostState mmc[AW_R40_NUM_MMCS]; AwR40ClockCtlState ccu; diff --git a/include/hw/misc/allwinner-sramc.h b/include/hw/misc/allwinner-= sramc.h new file mode 100644 index 00000000000..66b01b8d044 --- /dev/null +++ b/include/hw/misc/allwinner-sramc.h @@ -0,0 +1,69 @@ +/* + * Allwinner SRAM controller emulation + * + * Copyright (C) 2023 qianfan Zhao + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_SRAMC_H +#define HW_MISC_ALLWINNER_SRAMC_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "qemu/uuid.h" + +/** + * Object model + * @{ + */ +#define TYPE_AW_SRAMC "allwinner-sramc" +#define TYPE_AW_SRAMC_SUN8I_R40 TYPE_AW_SRAMC "-sun8i-r40" +OBJECT_DECLARE_TYPE(AwSRAMCState, AwSRAMCClass, AW_SRAMC) + +/** @} */ + +/** + * Allwinner SRAMC object instance state + */ +struct AwSRAMCState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /* registers */ + uint32_t sram_ctl1; + uint32_t sram_ver; + uint32_t sram_soft_entry_reg0; +}; + +/** + * Allwinner SRAM Controller class-level struct. + * + * This struct is filled by each sunxi device specific code + * such that the generic code can use this struct to support + * all devices. + */ +struct AwSRAMCClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + uint32_t sram_version_code; +}; + +#endif /* HW_MISC_ALLWINNER_SRAMC_H */ diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index c018ad231ad..7d29eb224f6 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -39,6 +39,7 @@ const hwaddr allwinner_r40_memmap[] =3D { [AW_R40_DEV_SRAM_A2] =3D 0x00004000, [AW_R40_DEV_SRAM_A3] =3D 0x00008000, [AW_R40_DEV_SRAM_A4] =3D 0x0000b400, + [AW_R40_DEV_SRAMC] =3D 0x01c00000, [AW_R40_DEV_EMAC] =3D 0x01c0b000, [AW_R40_DEV_MMC0] =3D 0x01c0f000, [AW_R40_DEV_MMC1] =3D 0x01c10000, @@ -76,7 +77,6 @@ struct AwR40Unimplemented { static struct AwR40Unimplemented r40_unimplemented[] =3D { { "d-engine", 0x01000000, 4 * MiB }, { "d-inter", 0x01400000, 128 * KiB }, - { "sram-c", 0x01c00000, 4 * KiB }, { "dma", 0x01c02000, 4 * KiB }, { "nfdc", 0x01c03000, 4 * KiB }, { "ts", 0x01c04000, 4 * KiB }, @@ -288,6 +288,8 @@ static void allwinner_r40_init(Object *obj) "ram-addr"); object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc), "ram-size"); + + object_initialize_child(obj, "sramc", &s->sramc, TYPE_AW_SRAMC_SUN8I_R= 40); } =20 static void allwinner_r40_realize(DeviceState *dev, Error **errp) @@ -382,6 +384,9 @@ static void allwinner_r40_realize(DeviceState *dev, Err= or **errp) AW_R40_GIC_SPI_TIMER1)); =20 /* SRAM */ + sysbus_realize(SYS_BUS_DEVICE(&s->sramc), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sramc), 0, s->memmap[AW_R40_DEV_SRA= MC]); + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", 16 * KiB, &error_abort); memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c new file mode 100644 index 00000000000..a8b731f8f28 --- /dev/null +++ b/hw/misc/allwinner-sramc.c @@ -0,0 +1,184 @@ +/* + * Allwinner R40 SRAM controller emulation + * + * Copyright (C) 2023 qianfan Zhao + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "hw/misc/allwinner-sramc.h" +#include "trace.h" + +/* + * register offsets + * https://linux-sunxi.org/SRAM_Controller_Register_Guide + */ +enum { + REG_SRAM_CTL1_CFG =3D 0x04, /* SRAM Control register 1 */ + REG_SRAM_VER =3D 0x24, /* SRAM Version register */ + REG_SRAM_R40_SOFT_ENTRY_REG0 =3D 0xbc, +}; + +/* REG_SRAMC_VERSION bit defines */ +#define SRAM_VER_READ_ENABLE (1 << 15) +#define SRAM_VER_VERSION_SHIFT 16 +#define SRAM_VERSION_SUN8I_R40 0x1701 + +static uint64_t allwinner_sramc_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwSRAMCState *s =3D AW_SRAMC(opaque); + AwSRAMCClass *sc =3D AW_SRAMC_GET_CLASS(s); + uint64_t val =3D 0; + + switch (offset) { + case REG_SRAM_CTL1_CFG: + val =3D s->sram_ctl1; + break; + case REG_SRAM_VER: + /* bit15: lock bit, set this bit before reading this register */ + if (s->sram_ver & SRAM_VER_READ_ENABLE) { + val =3D SRAM_VER_READ_ENABLE | + (sc->sram_version_code << SRAM_VER_VERSION_SHIFT); + } + break; + case REG_SRAM_R40_SOFT_ENTRY_REG0: + val =3D s->sram_soft_entry_reg0; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_sramc_read(offset, val); + + return val; +} + +static void allwinner_sramc_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwSRAMCState *s =3D AW_SRAMC(opaque); + + trace_allwinner_sramc_write(offset, val); + + switch (offset) { + case REG_SRAM_CTL1_CFG: + s->sram_ctl1 =3D val; + break; + case REG_SRAM_VER: + /* Only the READ_ENABLE bit is writeable */ + s->sram_ver =3D val & SRAM_VER_READ_ENABLE; + break; + case REG_SRAM_R40_SOFT_ENTRY_REG0: + s->sram_soft_entry_reg0 =3D val; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } +} + +static const MemoryRegionOps allwinner_sramc_ops =3D { + .read =3D allwinner_sramc_read, + .write =3D allwinner_sramc_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl.min_access_size =3D 4, +}; + +static const VMStateDescription allwinner_sramc_vmstate =3D { + .name =3D "allwinner-sramc", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(sram_ver, AwSRAMCState), + VMSTATE_UINT32(sram_soft_entry_reg0, AwSRAMCState), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_sramc_reset(DeviceState *dev) +{ + AwSRAMCState *s =3D AW_SRAMC(dev); + AwSRAMCClass *sc =3D AW_SRAMC_GET_CLASS(s); + + switch (sc->sram_version_code) { + case SRAM_VERSION_SUN8I_R40: + s->sram_ctl1 =3D 0x1300; + break; + } +} + +static void allwinner_sramc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D allwinner_sramc_reset; + dc->vmsd =3D &allwinner_sramc_vmstate; +} + +static void allwinner_sramc_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + AwSRAMCState *s =3D AW_SRAMC(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sramc_ops, s, + TYPE_AW_SRAMC, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const TypeInfo allwinner_sramc_info =3D { + .name =3D TYPE_AW_SRAMC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D allwinner_sramc_init, + .instance_size =3D sizeof(AwSRAMCState), + .class_init =3D allwinner_sramc_class_init, +}; + +static void allwinner_r40_sramc_class_init(ObjectClass *klass, void *data) +{ + AwSRAMCClass *sc =3D AW_SRAMC_CLASS(klass); + + sc->sram_version_code =3D SRAM_VERSION_SUN8I_R40; +} + +static const TypeInfo allwinner_r40_sramc_info =3D { + .name =3D TYPE_AW_SRAMC_SUN8I_R40, + .parent =3D TYPE_AW_SRAMC, + .class_init =3D allwinner_r40_sramc_class_init, +}; + +static void allwinner_sramc_register(void) +{ + type_register_static(&allwinner_sramc_info); + type_register_static(&allwinner_r40_sramc_info); +} + +type_init(allwinner_sramc_register) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 007a81e6ede..2159de3ce65 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -406,6 +406,7 @@ config ALLWINNER_H3 config ALLWINNER_R40 bool default y if TCG && ARM + select ALLWINNER_SRAMC select ALLWINNER_A10_PIT select AXP2XX_PMU select SERIAL diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index efeb430a6ce..e4c21491759 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -170,6 +170,9 @@ config VIRT_CTRL config LASI bool =20 +config ALLWINNER_SRAMC + bool + config ALLWINNER_A10_CCM bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b04d43e05a3..78ca857c9d9 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -37,6 +37,7 @@ subdir('macio') =20 softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c')) =20 +softmmu_ss.add(when: 'CONFIG_ALLWINNER_SRAMC', if_true: files('allwinner-s= ramc.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner= -a10-ccm.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinn= er-a10-dramc.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-c= cu.c')) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 8b68f077657..4d1a0e17af5 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -33,6 +33,10 @@ allwinner_r40_dramphy_write(uint64_t offset, uint64_t da= ta, unsigned size) "writ allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset = 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset= 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 =20 +# allwinner-sramc.c +allwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 "= data 0x%" PRIx64 +allwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 = " data 0x%" PRIx64 + # avr_power.c avr_power_read(uint8_t value) "power_reduc read value:%u" avr_power_write(uint8_t value) "power_reduc write value:%u" --=20 2.34.1