From nobody Tue Feb 10 17:45:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685884646247330.922092354907; Sun, 4 Jun 2023 06:17:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5na7-00051P-Ek; Sun, 04 Jun 2023 09:15:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5na3-0004zu-9c for qemu-devel@nongnu.org; Sun, 04 Jun 2023 09:15:35 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5na0-0003FS-CX for qemu-devel@nongnu.org; Sun, 04 Jun 2023 09:15:34 -0400 Received: from [2a00:23c4:8bac:6900:b726:cf58:4c12:f013] (helo=kentang.home) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1q5nZp-0005pb-ML; Sun, 04 Jun 2023 14:15:25 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=eEFw788dh569iCUFSIkapMHiytAnsouf6PVjvltvkNs=; b=XeBY1kx/J8N365nvNqVu55X15t RSLf6Gk9gvKQh/I5KuXDXovRZQLbI8vlU6l6SJ+fGyJWmbQcV/+sijBops2oEvizbElbSfQheeKKz 7btV7CJi3o04jkMpBBrfP98VzaPRsRSk4sEhTqsJYCu5LaebI5zyIBz+a/YI0r20wpQlfF7eCAcsY 0kZTq3gBQzQTMVcBVKdaEFMVWhSQjumgyb+Vn0uyR4v10tri2A2i25T6eK3gLsrvZUHD2ijo9ongn 94QDT6j95gG9AirhZBdeurrvvo5HCNceJZac/REORSYWGpenbQCxdGRAFsxM+pd2AC6D7WmJM9qkM D+VSyR1KpJURYEhadrCqc/9nj+Hl1umy1oHQgNs069w1RQb7ociOvwoE9GeMhtLaYP5F4vwjKqzWV nySSDVpx8IE3Wzo93q3vpWO3CL65qOLmlXb3IB40jO3DS+OSftFuZT88qTYm1KkFDMgqtG860dOYz gj4W7z8dUJ/MOfUe82YO/JwP2Lg8dg7XmbJ6ZdCHrcVO16Yja587wKTwSmZQ0PC10E+Sf3ov6EQLQ DrSqQ+rK5/86LSYz9zE0EDg6Xuipv9eYM5aJgEo22LJavvyYSqRgw4mV+1m2u6/q6/HajVRxr91ea WY2PtR9sXcp2sBJ3fItrOtXH26FbvLqucjoocbcqs=; From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Sun, 4 Jun 2023 14:14:37 +0100 Message-Id: <20230604131450.428797-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230604131450.428797-1-mark.cave-ayland@ilande.co.uk> References: <20230604131450.428797-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8bac:6900:b726:cf58:4c12:f013 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 10/23] q800: reimplement mac-io region aliasing using IO memory region X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685884647724100005 Content-Type: text/plain; charset="utf-8" The current use of aliased memory regions causes us 2 problems: firstly the output of "info qom-tree" is absolutely huge and difficult to read, and secondly we have already reached the internal limit for memory regions as adding any new memory region into the mac-io region causes QEMU to assert with "phys_section_add: Assertion `map->sections_nb < TARGET_PAGE_SIZE' failed". Implement the mac-io region aliasing using a single IO memory region that applies IO_SLICE_MASK representing the maximum size of the aliased region a= nd then forwarding the access to the existing mac-io memory region using the address space API. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/m68k/q800.c | 100 +++++++++++++++++++++++++++++++++-------- include/hw/m68k/q800.h | 1 + 2 files changed, 82 insertions(+), 19 deletions(-) diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 6682c81ac8..cb4fcdcfb8 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -59,6 +59,7 @@ =20 #define IO_BASE 0x50000000 #define IO_SLICE 0x00040000 +#define IO_SLICE_MASK (IO_SLICE - 1) #define IO_SIZE 0x04000000 =20 #define VIA_BASE (IO_BASE + 0x00000) @@ -127,6 +128,68 @@ static uint8_t fake_mac_rom[] =3D { 0x60, 0xFE /* bras [self] */ }; =20 +static MemTxResult macio_alias_read(void *opaque, hwaddr addr, uint64_t *d= ata, + unsigned size, MemTxAttrs attrs) +{ + MemTxResult r; + uint32_t val; + + addr &=3D IO_SLICE_MASK; + addr |=3D IO_BASE; + + switch (size) { + case 4: + val =3D address_space_ldl_be(&address_space_memory, addr, attrs, &= r); + break; + case 2: + val =3D address_space_lduw_be(&address_space_memory, addr, attrs, = &r); + break; + case 1: + val =3D address_space_ldub(&address_space_memory, addr, attrs, &r); + break; + default: + g_assert_not_reached(); + } + + *data =3D val; + return r; +} + +static MemTxResult macio_alias_write(void *opaque, hwaddr addr, uint64_t v= alue, + unsigned size, MemTxAttrs attrs) +{ + MemTxResult r; + + addr &=3D IO_SLICE_MASK; + addr |=3D IO_BASE; + + switch (size) { + case 4: + address_space_stl_be(&address_space_memory, addr, value, attrs, &r= ); + break; + case 2: + address_space_stw_be(&address_space_memory, addr, value, attrs, &r= ); + break; + case 1: + address_space_stb(&address_space_memory, addr, value, attrs, &r); + break; + default: + g_assert_not_reached(); + } + + return r; +} + +static const MemoryRegionOps macio_alias_ops =3D { + .read_with_attrs =3D macio_alias_read, + .write_with_attrs =3D macio_alias_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + static void q800_machine_init(MachineState *machine) { Q800MachineState *m =3D Q800_MACHINE(machine); @@ -137,10 +200,8 @@ static void q800_machine_init(MachineState *machine) int bios_size; ram_addr_t initrd_base; int32_t initrd_size; - MemoryRegion *io; MemoryRegion *dp8393x_prom =3D g_new(MemoryRegion, 1); uint8_t *prom; - const int io_slice_nb =3D (IO_SIZE / IO_SLICE) - 1; int i, checksum; MacFbMode *macfb_mode; ram_addr_t ram_size =3D machine->ram_size; @@ -187,16 +248,10 @@ static void q800_machine_init(MachineState *machine) * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE */ - io =3D g_new(MemoryRegion, io_slice_nb); - for (i =3D 0; i < io_slice_nb; i++) { - char *name =3D g_strdup_printf("mac_m68k.io[%d]", i + 1); - - memory_region_init_alias(&io[i], NULL, name, get_system_memory(), - IO_BASE, IO_SLICE); - memory_region_add_subregion(get_system_memory(), - IO_BASE + (i + 1) * IO_SLICE, &io[i]); - g_free(name); - } + memory_region_init_io(&m->macio_alias, OBJECT(machine), &macio_alias_o= ps, + &m->macio, "mac-io.alias", IO_SIZE - IO_SLICE); + memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE, + &m->macio_alias); =20 /* IRQ Glue */ object_initialize_child(OBJECT(machine), "glue", &m->glue, TYPE_GLUE); @@ -212,7 +267,8 @@ static void q800_machine_init(MachineState *machine) } sysbus =3D SYS_BUS_DEVICE(via1_dev); sysbus_realize_and_unref(sysbus, &error_fatal); - sysbus_mmio_map(sysbus, 1, VIA_BASE); + memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE, + sysbus_mmio_get_region(sysbus, 1)); sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA1= )); /* A/UX mode */ @@ -230,7 +286,8 @@ static void q800_machine_init(MachineState *machine) via2_dev =3D qdev_new(TYPE_MOS6522_Q800_VIA2); sysbus =3D SYS_BUS_DEVICE(via2_dev); sysbus_realize_and_unref(sysbus, &error_fatal); - sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE); + memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE + VIA_SIZE, + sysbus_mmio_get_region(sysbus, 1)); sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA2= )); =20 @@ -264,7 +321,8 @@ static void q800_machine_init(MachineState *machine) OBJECT(get_system_memory()), &error_abort); sysbus =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sysbus, &error_fatal); - sysbus_mmio_map(sysbus, 0, SONIC_BASE); + memory_region_add_subregion(&m->macio, SONIC_BASE - IO_BASE, + sysbus_mmio_get_region(sysbus, 0)); sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_SONI= C)); =20 @@ -305,7 +363,8 @@ static void q800_machine_init(MachineState *machine) qdev_connect_gpio_out(DEVICE(escc_orgate), 0, qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_ESCC)); - sysbus_mmio_map(sysbus, 0, SCC_BASE); + memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE, + sysbus_mmio_get_region(sysbus, 0)); =20 /* SCSI */ =20 @@ -325,8 +384,10 @@ static void q800_machine_init(MachineState *machine) VIA2_IRQ_SCSI_BIT))); sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_de= v, VIA2_IRQ_SCSI_DATA_BIT))= ); - sysbus_mmio_map(sysbus, 0, ESP_BASE); - sysbus_mmio_map(sysbus, 1, ESP_PDMA); + memory_region_add_subregion(&m->macio, ESP_BASE - IO_BASE, + sysbus_mmio_get_region(sysbus, 0)); + memory_region_add_subregion(&m->macio, ESP_PDMA - IO_BASE, + sysbus_mmio_get_region(sysbus, 1)); =20 scsi_bus_legacy_handle_cmdline(&esp->bus); =20 @@ -334,7 +395,8 @@ static void q800_machine_init(MachineState *machine) =20 dev =3D qdev_new(TYPE_SWIM); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); + memory_region_add_subregion(&m->macio, SWIM_BASE - IO_BASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev)= , 0)); =20 /* NuBus */ =20 diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index 17067dfad7..1ed38bf0b1 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -40,6 +40,7 @@ struct Q800MachineState { MemoryRegion rom; GLUEState glue; MemoryRegion macio; + MemoryRegion macio_alias; }; =20 #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800") --=20 2.30.2