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([2602:ae:1598:4c01:66a6:82c2:d794:68f6]) by smtp.gmail.com with ESMTPSA id e91-20020a17090a6fe400b002508d73f4e8sm3914289pjk.57.2023.06.02.19.34.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 19:34:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685759696; x=1688351696; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m3OHDG5WK7pMNPAxl55tD/qKqCZQ1l17wihsUptzQ58=; b=ibkNH62KmMxPoUq17zOh3oLg47my8C4QKa7P7f2qQs2nGPYb8lZWIbGUhGBgOiK4NI kAwgvUc5ZTHy61UEzmZ3wRKFZ/w/UMDhLS3DUz8wXtNn8jRruCIHDtQB/i6KuLDEBioZ ederaqCUOGp2eFkSNPw503RXhASm67MxlmZwHDFTaMrpaWEl0pmlJLQjxTfGSWSIHDak LmkbIXxd6+WgXNEJsazwpXvyMtJdX/BBaQ4fI2MXV6/qYqE/GI4Dg5Ru+onW2tuwX/Qu 6oDgcMyroooykMxHYKcAfFioaMRJL8O5mLNm7Y6kWGqIg2BDF54uZOrvIXzazrGM8RwJ 9wwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685759696; x=1688351696; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m3OHDG5WK7pMNPAxl55tD/qKqCZQ1l17wihsUptzQ58=; b=L3Qligm5XJo2/E8CGn3FI//Baddb6kVSY6nBbZhf1Hbk2YCdG0ceWmUe8kuJ65Gamv 1m2DOknWv5lMaAxRxlhn+8IYWu+78ADu9Sw0pxjvojicAE8iIxgYLLT4L15HTa2ojWIp AsGxAuUH/ifdL3TvzEDD3n6DLMJszhnZenLS4ovSuS7TM3850Y573AiJNPGMGskEl34F PicmM2MSZpdYlH5m18eEK5AjPNonLZd3pcf0U+j43ypO5FwrtjxWF3HBg4ibQkrGWzzX kbl6EWhzfqI5cgAymitUdS6s4QFud9NDB8jswjHJ2zRTFFIAp/OHVuLbRM1HOB+x9Z8i T2lg== X-Gm-Message-State: AC+VfDxuEjqphtM36TJujX+aIfAy2uoP7TZFIR3EnJhqP7DGV0F0cLHS eeZcxgs6TuVpMnMX8fPuyCB+WRYNxAHLXXoXyPk= X-Google-Smtp-Source: ACHHUZ76AjUwHThURAVw7smpE0g25zx8SUI14WtIuByygliUY4WVQEn+wg0CKYKoTOm+Y33IU30HBw== X-Received: by 2002:a25:d846:0:b0:ba8:3b3d:3dc0 with SMTP id p67-20020a25d846000000b00ba83b3d3dc0mr5224104ybg.65.1685759696030; Fri, 02 Jun 2023 19:34:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ardb@kernel.org, berrange@redhat.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com Subject: [PATCH 31/35] host/include/aarch64: Implement aes-round.h Date: Fri, 2 Jun 2023 19:34:22 -0700 Message-Id: <20230603023426.1064431-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230603023426.1064431-1-richard.henderson@linaro.org> References: <20230603023426.1064431-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=richard.henderson@linaro.org; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685760040305100001 Content-Type: text/plain; charset="utf-8" Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson --- host/include/aarch64/host/aes-round.h | 204 ++++++++++++++++++++++++++ host/include/aarch64/host/cpuinfo.h | 1 + util/cpuinfo-aarch64.c | 2 + 3 files changed, 207 insertions(+) create mode 100644 host/include/aarch64/host/aes-round.h diff --git a/host/include/aarch64/host/aes-round.h b/host/include/aarch64/h= ost/aes-round.h new file mode 100644 index 0000000000..27ca823db6 --- /dev/null +++ b/host/include/aarch64/host/aes-round.h @@ -0,0 +1,204 @@ +/* + * AArch64 specific aes acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HOST_AES_ROUND_H +#define HOST_AES_ROUND_H + +#include "host/cpuinfo.h" +#include + +#ifdef __ARM_FEATURE_AES +# define HAVE_AES_ACCEL true +# define ATTR_AES_ACCEL +#else +# define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_AES) +# define ATTR_AES_ACCEL __attribute__((target("+crypto"))) +#endif + +static inline uint8x16_t aes_accel_bswap(uint8x16_t x) +{ + /* No arm_neon.h primitive, and the compilers don't share builtins. */ +#ifdef __clang__ + return __builtin_shufflevector(x, x, 15, 14, 13, 12, 11, 10, 9, 8, + 7, 6, 5, 4, 3, 2, 1, 0); +#else + return __builtin_shuffle(x, (uint8x16_t) + { 15, 14, 13, 12, 11, 10, 9, 8, + 7, 6, 5, 4, 3, 2, 1, 0, }); +#endif +} + +/* + * Through clang 15, the aes inlines are only defined if __ARM_FEATURE_AES; + * one cannot use __attribute__((target)) to make them appear after the fa= ct. + * Therefore we must fallback to inline asm. + */ +#ifdef __ARM_FEATURE_AES +# define aes_accel_aesd vaesdq_u8 +# define aes_accel_aese vaeseq_u8 +# define aes_accel_aesmc vaesmcq_u8 +# define aes_accel_aesimc vaesimcq_u8 +#else +static inline uint8x16_t aes_accel_aesd(uint8x16_t d, uint8x16_t k) +{ + asm(".arch_extension aes\n\t" + "aesd %0.16b, %1.16b" : "+w"(d) : "w"(k)); + return d; +} + +static inline uint8x16_t aes_accel_aese(uint8x16_t d, uint8x16_t k) +{ + asm(".arch_extension aes\n\t" + "aese %0.16b, %1.16b" : "+w"(d) : "w"(k)); + return d; +} + +static inline uint8x16_t aes_accel_aesmc(uint8x16_t d) +{ + asm(".arch_extension aes\n\t" + "aesmc %0.16b, %1.16b" : "=3Dw"(d) : "w"(d)); + return d; +} + +static inline uint8x16_t aes_accel_aesimc(uint8x16_t d) +{ + asm(".arch_extension aes\n\t" + "aesimc %0.16b, %1.16b" : "=3Dw"(d) : "w"(d)); + return d; +} +#endif /* __ARM_FEATURE_AES */ + +static inline void ATTR_AES_ACCEL +aesenc_MC_accel(AESState *ret, const AESState *st, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aesmc(t); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesmc(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_accel(AESState *ret, const AESState *st, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aese(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aese(t, z); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t k =3D (uint8x16_t)rk->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D aes_accel_aese(t, z); + t =3D aes_accel_aesmc(t); + t =3D veorq_u8(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aese(t, z); + t =3D aes_accel_aesmc(t); + t =3D veorq_u8(t, k); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aesimc(t); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesimc(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_accel(AESState *ret, const AESState *st, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D aes_accel_aesd(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesd(t, z); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_AK_IMC_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t k =3D (uint8x16_t)rk->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D aes_accel_aesd(t, z); + t =3D veorq_u8(t, k); + t =3D aes_accel_aesimc(t); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesd(t, z); + t =3D veorq_u8(t, k); + t =3D aes_accel_aesimc(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_IMC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + uint8x16_t t =3D (uint8x16_t)st->v; + uint8x16_t k =3D (uint8x16_t)rk->v; + uint8x16_t z =3D { }; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D aes_accel_aesd(t, z); + t =3D aes_accel_aesimc(t); + t =3D veorq_u8(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D aes_accel_aesd(t, z); + t =3D aes_accel_aesimc(t); + t =3D veorq_u8(t, k); + } + ret->v =3D (AESStateVec)t; +} + +#endif diff --git a/host/include/aarch64/host/cpuinfo.h b/host/include/aarch64/hos= t/cpuinfo.h index 82227890b4..05feeb4f43 100644 --- a/host/include/aarch64/host/cpuinfo.h +++ b/host/include/aarch64/host/cpuinfo.h @@ -9,6 +9,7 @@ #define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ #define CPUINFO_LSE (1u << 1) #define CPUINFO_LSE2 (1u << 2) +#define CPUINFO_AES (1u << 3) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c index f99acb7884..ababc39550 100644 --- a/util/cpuinfo-aarch64.c +++ b/util/cpuinfo-aarch64.c @@ -56,10 +56,12 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); info |=3D (hwcap & HWCAP_ATOMICS ? CPUINFO_LSE : 0); info |=3D (hwcap & HWCAP_USCAT ? CPUINFO_LSE2 : 0); + info |=3D (hwcap & HWCAP_AES ? CPUINFO_AES: 0); #endif #ifdef CONFIG_DARWIN info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE") * CPUINFO_LSE; info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE2") * CPUINFO_LSE2; + info |=3D sysctl_for_bool("hw.optional.arm.FEAT_AES") * CPUINFO_AES; #endif =20 cpuinfo =3D info; --=20 2.34.1