From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721193; cv=none; d=zohomail.com; s=zohoarc; b=R4GsG4MLOqJCcE+rr3fSEpYlKYxBpI/ZzJOIzbtpSXiAP2oFjh3FUKyJLn8n18qodRSiPpNpC762qY11OsFjzmaI3gbZvTg3difqGzM3m+3MnjJyJXDxM6xKOlmiSKrX4Zm7wzXqpz/HZptafQjRBUplXublCgkDVk0fyryt2+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721193; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T5r/LpHJMg7TbmN47HlK1bNQm+yT4WVmfzXQIP2d3t4=; b=BeexZo0Lp56N1t+f0CDwq+/XiF7rttKQbPoDIkx2ARCh/mJg0YAHVBOml8ZllRw7IcEf8qBlKh/RAjyNxgTFkK3VeCDXMIGl44szOUwI13Z3i5nPYaemFHrTRQUuSqwivNx1+QL6SOxjNh2tzcpz4pfoGtVHMB4FcQBH7cpuD4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721193887462.13980124955106; Fri, 2 Jun 2023 08:53:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574o-000367-Rk; Fri, 02 Jun 2023 11:52:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574n-00035o-FE for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:29 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574l-0003QR-OM for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:29 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3063433fa66so2217895f8f.3 for ; Fri, 02 Jun 2023 08:52:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721146; x=1688313146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=T5r/LpHJMg7TbmN47HlK1bNQm+yT4WVmfzXQIP2d3t4=; b=K2dKhw800F0rxq5ZXvDlEKEmum+eXRXGIm4a6d8x40IwSBKIMvd5rvgl8TNYs89Rsl Bjh0FX+Dl4R0xTFjuAc3w26xunrWpWYOHbQE7b5lKz2nJ/s+Ji2MH7PXILwV7VY0IgFc kgayOFLg6XRFCMs8ezWLJf/njl4JOEh9VWQFpU9uqH+ZVyg/Rn1G0UrVYrPPb3DzWUvZ 5cgdczK21w2VydIieuSPGPW7mAcFeQD/aCTPRsY1suXWDsHZ7nFmjZSzvxWK6D3m+1s8 kEx4WlV/+S3lPWnD8WOpO3aEnzZmTk37G0kR6ovOg2AYap0/eRZw8sEHP6ZudmMVpCqi dp/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721146; x=1688313146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T5r/LpHJMg7TbmN47HlK1bNQm+yT4WVmfzXQIP2d3t4=; b=lrJC8kiUZRvvAtfnTvsadIGAm/5oT2GG3/QSlTXg+IvVwaLl1YpCr2UQRQgtrHAagF LqMbUPloF06B1xKBzViWTGJt6jrQJKv0GByq6HC7LUFl+/ZPQd4CQOsmHHPW2x5BmsDM NJIhVJoE6CT8nWaHi72ckLIFcehgOhn+8KhjXcuWesmdkZwNIKhR24/s1zahQnpcGP3S EysI2YngVToXt750PAW2bsUwJ8vvZL2ShaOsachkaqtBYpmgxz5C3kA+am9q808UVXNO 229j2RXfYMyZ0PsPNMsJmlJZZR35cpf1ibQNjUVokdhTQNTriIwB6RZ5EClyu20mxmAH 0LYA== X-Gm-Message-State: AC+VfDzH/8Ip02AhTG8HA6mBYo2N7KoXX5k1pfNoVMNxklo3bhE5RIto 7JGZcRP4yElHkrPBoKyw1qx7uDnaMNMSEoVFmdk= X-Google-Smtp-Source: ACHHUZ4+hOXAPpW83FkzmhDy6HKDypvfJ73L00gJUGXIIaVZDBwKz5ti4h4DHRLg/laaExi8m0tsag== X-Received: by 2002:adf:dd0e:0:b0:30a:f06f:3ee0 with SMTP id a14-20020adfdd0e000000b0030af06f3ee0mr268590wrm.28.1685721146369; Fri, 02 Jun 2023 08:52:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/20] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics Date: Fri, 2 Jun 2023 16:52:04 +0100 Message-Id: <20230602155223.2040685-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721196128100003 Content-Type: text/plain; charset="utf-8" The atomic memory operations are supposed to return the old memory data value in the destination register. This value is not sign-extended, even if the operation is the signed minimum or maximum. (In the pseudocode for the instructions the returned data value is passed to ZeroExtend() to create the value in the register.) We got this wrong because we were doing a 32-to-64 zero extend on the result for 8 and 16 bit data values, rather than the correct amount of zero extension. Fix the bug by using ext8u and ext16u for the MO_8 and MO_16 data sizes rather than ext32u. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 741a6087399..075553e15f5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3401,8 +3401,22 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, */ fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); =20 - if ((mop & MO_SIGN) && size !=3D MO_64) { - tcg_gen_ext32u_i64(tcg_rt, tcg_rt); + if (mop & MO_SIGN) { + switch (size) { + case MO_8: + tcg_gen_ext8u_i64(tcg_rt, tcg_rt); + break; + case MO_16: + tcg_gen_ext16u_i64(tcg_rt, tcg_rt); + break; + case MO_32: + tcg_gen_ext32u_i64(tcg_rt, tcg_rt); + break; + case MO_64: + break; + default: + g_assert_not_reached(); + } } } =20 --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721270; cv=none; d=zohomail.com; s=zohoarc; b=bWGsziQAu2qJ/xBOOJYBp8kYRhsnGL6KKzCXL+wkAjwdEM2L4S2bv+nkNqHrlv7qKXYmABBqTVNBcRFK6jjz00jUnVNpYIxWuHHm6td2H5tdq/ZTuSJ0I3CnB1qeUcOo/0SggHtnO5VnA30bLjjSwZ7zgVhPMNdJqfWdrTdunvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721270; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8bAEGzOfvPGfWDyJXndBi9fppWOebMwnl9nEal6GFOc=; b=oBAQIrGfg7EsvxII1RP3iKs0cz71Pirp/CI3CNbqFM53l++yewc8o9wSD0LFQ5BZtvT6kLV5L79qfr6PaJYBWfMl5IpV4O5UCyT9wnlTiOTeMlOjqHZG2WBdG+hlbpXGQDQ+0kYP3yDxJbwdowFdn+V+DY4qn1uE4G7ppVcRXVQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721270006273.2441018834618; Fri, 2 Jun 2023 08:54:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574s-00039E-7V; Fri, 02 Jun 2023 11:52:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574p-00036m-LJ for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:31 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574m-0003Qq-FM for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:31 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f606912ebaso22542835e9.3 for ; Fri, 02 Jun 2023 08:52:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721147; x=1688313147; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8bAEGzOfvPGfWDyJXndBi9fppWOebMwnl9nEal6GFOc=; b=TpR+HfWXkgqWhgSsT49f6tSIT4thDd82wglrzPiEtqmWhZvM8TpBRtEdpd3hZJeXAl DO83oLAknQ5q/34oEop/qY1Mg3hbqw1RYTVeElpjGvTLNYs3c8SnMYyxMZ4KyYi1cdkn qhoGrP5ADe6NPNxmyqLCfLg0xC1jBypPQ5hJDI1/qtn6jw0zpEI+NGMuvk/eXgN5uaQq 0mOJ+vAEBFPz9V4x1wHN6JUQOQV0aTG2GKrUAf8k7RFAlYmdzQ6f/7LbVBUmJGUoA+GO Y68S/rjEow1aJ4RYvWkm07Vu9QiWsIu4as2WNFPdjtq9bBDpGKn9VDlRzutNjGS4dog/ 2Fog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721147; x=1688313147; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8bAEGzOfvPGfWDyJXndBi9fppWOebMwnl9nEal6GFOc=; b=JeQLnSxBKWpxbh6pmxF6N80RPIkSIpSNXlmNsNxEH/c8/pXCAQkskjwiQ2PaS2ysdE iAQ4HaORoks5UOxCoeT94jREcld6kuyPRkHgwzknk8icG+gdcB5y6RHo0HQ/uLEhu/a3 z8/rRcgsTNAY9DXbG5M45sTe20mg8zv9qKPp82vC6juw510D1hNFCKQyy9ftpXfVfT+e tb8BvLqUCJbN7Jz6eoA2q75HXeQ0pCFasjfQJAP6DtQVJ/0JoqG8o5671kIm4PH+J1Du bFzK+syfoZ5WLeluTEriRfiqqgow0aABflWNcwH6tPeA/7PR3MM01tjxDUCTNJGASBrk 4brQ== X-Gm-Message-State: AC+VfDwwKw2P4pDuYXOlmEq51jyhpUQNLxG5+gXxHYwz7rPALStG+tuX oYj10GYYbef9aQ6bwJtcb9zRHviH4bngCU8FR3g= X-Google-Smtp-Source: ACHHUZ5tKkC/I9DOn7HWaceSx6x9eL5tQ1w2Olsmg6guaDbmEfW3d8ccORU9DyijQBtkK57aDV3nqg== X-Received: by 2002:a05:600c:3798:b0:3f6:244:55df with SMTP id o24-20020a05600c379800b003f6024455dfmr2448989wmr.29.1685721147077; Fri, 02 Jun 2023 08:52:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/20] target/arm: Convert hint instruction space to decodetree Date: Fri, 2 Jun 2023 16:52:05 +0100 Message-Id: <20230602155223.2040685-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721270359100005 Content-Type: text/plain; charset="utf-8" Convert the various instructions in the hint instruction space to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 31 ++++ target/arm/tcg/translate-a64.c | 277 ++++++++++++++++++--------------- 2 files changed, 185 insertions(+), 123 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 12a310d0a31..1efd436e175 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -150,3 +150,34 @@ ERETA 1101011 0100 11111 00001 m:1 11111 111= 11 &reta # ERETAA, ERETAB # the processor is in halting debug state (which we don't implement). # The pattern is listed here as documentation. # DRPS 1101011 0101 11111 000000 11111 00000 + +# Hint instruction group +{ + [ + YIELD 1101 0101 0000 0011 0010 0000 001 11111 + WFE 1101 0101 0000 0011 0010 0000 010 11111 + WFI 1101 0101 0000 0011 0010 0000 011 11111 + # We implement WFE to never block, so our SEV/SEVL are NOPs + # SEV 1101 0101 0000 0011 0010 0000 100 11111 + # SEVL 1101 0101 0000 0011 0010 0000 101 11111 + # Our DGL is a NOP because we don't merge memory accesses anyway. + # DGL 1101 0101 0000 0011 0010 0000 110 11111 + XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 + PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 + PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 + AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 + AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 + ESB 1101 0101 0000 0011 0010 0010 000 11111 + PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 + PACIASP 1101 0101 0000 0011 0010 0011 001 11111 + PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 + PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 + AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 + AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 + AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 + AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 + ] + # The canonical NOP has CRm =3D=3D op2 =3D=3D 0, but all of the space + # that isn't specifically allocated to an instruction must NOP + NOP 1101 0101 0000 0011 0010 ---- --- 11111 +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 075553e15f5..ecc4b9c1bd3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1594,133 +1594,167 @@ static bool trans_ERETA(DisasContext *s, arg_reta= *a) return true; } =20 -/* HINT instruction group, including various allocated HINTs */ -static void handle_hint(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int c= rm) +static bool trans_NOP(DisasContext *s, arg_NOP *a) { - unsigned int selector =3D crm << 3 | op2; + return true; +} =20 - if (op1 !=3D 3) { - unallocated_encoding(s); - return; +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + /* + * When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + s->base.is_jmp =3D DISAS_YIELD; } + return true; +} =20 - switch (selector) { - case 0b00000: /* NOP */ - break; - case 0b00011: /* WFI */ - s->base.is_jmp =3D DISAS_WFI; - break; - case 0b00001: /* YIELD */ - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + s->base.is_jmp =3D DISAS_WFI; + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFI *a) +{ + /* + * When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + s->base.is_jmp =3D DISAS_WFE; + } + return true; +} + +static bool trans_XPACLRI(DisasContext *s, arg_XPACLRI *a) +{ + if (s->pauth_active) { + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + } + return true; +} + +static bool trans_PACIA1716(DisasContext *s, arg_PACIA1716 *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_PACIB1716(DisasContext *s, arg_PACIB1716 *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_AUTIA1716(DisasContext *s, arg_AUTIA1716 *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_AUTIB1716(DisasContext *s, arg_AUTIB1716 *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_YIELD; + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); } - break; - case 0b00010: /* WFE */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; - } - break; - case 0b00100: /* SEV */ - case 0b00101: /* SEVL */ - case 0b00110: /* DGH */ - /* we treat all as NOP at least for now */ - break; - case 0b00111: /* XPACLRI */ - if (s->pauth_active) { - gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); - } - break; - case 0b01000: /* PACIA1716 */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01010: /* PACIB1716 */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01100: /* AUTIA1716 */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01110: /* AUTIB1716 */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b10000: /* ESB */ - /* Without RAS, we must implement this as NOP. */ - if (dc_isar_feature(aa64_ras, s)) { - /* - * QEMU does not have a source of physical SErrors, - * so we are only concerned with virtual SErrors. - * The pseudocode in the ARM for this case is - * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then - * AArch64.vESBOperation(); - * Most of the condition can be evaluated at translation time. - * Test for EL2 present, and defer test for SEL2 to runtime. - */ - if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { - gen_helper_vesb(cpu_env); - } - } - break; - case 0b11000: /* PACIAZ */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11001: /* PACIASP */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11010: /* PACIBZ */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11011: /* PACIBSP */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11100: /* AUTIAZ */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11101: /* AUTIASP */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11110: /* AUTIBZ */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11111: /* AUTIBSP */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - default: - /* default specified as NOP equivalent */ - break; } + return true; +} + +static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_PACIASP(DisasContext *s, arg_PACIASP *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_PACIBSP(DisasContext *s, arg_PACIBSP *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_AUTIASP(DisasContext *s, arg_AUTIASP *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; } =20 static void gen_clrex(DisasContext *s, uint32_t insn) @@ -2246,9 +2280,6 @@ static void disas_system(DisasContext *s, uint32_t in= sn) return; } switch (crn) { - case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ - handle_hint(s, insn, op1, op2, crm); - break; case 3: /* CLREX, DSB, DMB, ISB */ handle_sync(s, insn, op1, op2, crm); break; --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721229; cv=none; d=zohomail.com; s=zohoarc; b=Fk8NVSM8BABGhbvp43mhV/WmKhLR/MHPZgg/xJ1/U0CURg6xIOKFDylvNC9vO+8DVskvP2bicFburahUisOPPzxElum970bOpkfGGbkSkHMNwPgWa7OC/SNTkuZFRjxSeJGrmYGfX5iEgx7VS69H6IV9x4G0VER/fpYm4df5xuo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721229; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hJsYRyAUxIkV2ASeZSYE7316GaNRhskisUjyxHNbJ/0=; b=gz+covtBDK5lgaguEmoYR2au68gjMeATZ3lBWIdtIJRCuNcLIPdaAIqe9RETL/4wwFstofFcqn1m0lYNwCNMlDxqv4no5xrc7+8rkpM2H96cJOJTBRvobjVKqNuMK42S5gQOPwF9qxzQRLOOo6kZU4N2EogfmwRZfC4wWnZ1pKc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721229353319.46254688740817; Fri, 2 Jun 2023 08:53:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574q-000385-Tw; Fri, 02 Jun 2023 11:52:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574p-00036H-5P for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:31 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574n-0003R5-57 for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:30 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-30af20f5f67so2189862f8f.1 for ; Fri, 02 Jun 2023 08:52:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721148; x=1688313148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hJsYRyAUxIkV2ASeZSYE7316GaNRhskisUjyxHNbJ/0=; b=X48/ayCXX2rgr8zxCAUTn2mQGQv2Ks46zXRxQNvKT0jNuALaXUrrr4Exd18SPe+Xt/ wftL/o8Og9X+nHEEPxhLrH9EMpwjsZ8yhZAITV/kj6CcxaFKrbpTge69n2W6gkhXw6El jZcsl/ItEA/lLaO9lsg52ho2Fvmk9kGvrCUa8N/ii3WQEAArvEvlFgCqL8L0IOfEOdv+ zcsKQCaemBKpfQVtHoPt3lvRAejH5OWxsJp4m4pl6Y65swzTabbRF15yI8L4SWdgNxp7 96+3FA8Si/nHwQ9xhEthMihY1ELoc1e1RF7G6KJVI95Oybx9C3vZGXWcR6WjUdbSYfHi LD7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721148; x=1688313148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hJsYRyAUxIkV2ASeZSYE7316GaNRhskisUjyxHNbJ/0=; b=MYJJ+oquqMWEpwusvkIL/xG7JiymMEsGffjUQa29l2FRclWoaPSKKhqw7ICK8dhiuH RklSD/v4l12pm/3WVdN0vR0skrhjGpvKcXywh0oro4IsUAjJYR1lKzmYPBgMDXiiiVOk +pp9RQlsmF3mktkmV8fyFbOwRke1J6g3PTBLzW6z7hLV3euUKOguJEwcDGXetiGVc6Bp OO0+IYucnsMQj0o6V8vsqnGiC/ZSkyrq/LPIHQ7w9qS3QUoPQwJJw6ybKl+YVTJ9Yj0J qRV3/dTTeHb2tVtnpzUo2Rnog//IB0f5jcyw/jqE+1wZDNQTAwyABme7JgrsNJXXhQHF ciLw== X-Gm-Message-State: AC+VfDyJ57nG7GIoahVjRkF8dyqDp7OCDOXspX5jb6z1IHr8E7sMUfQW UkYDhRZi+KuyOd8YJD60WlKaIg== X-Google-Smtp-Source: ACHHUZ4xX58YPeRvW3lIytRYDAm7IaiMKeCUi6hZGrcHqeyn6M1tA8UMCGnN1WpcXm5IMJhQJfo8Qg== X-Received: by 2002:adf:dc01:0:b0:2f6:ca0d:ec1c with SMTP id t1-20020adfdc01000000b002f6ca0dec1cmr347284wri.10.1685721147779; Fri, 02 Jun 2023 08:52:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/20] target/arm: Convert barrier insns to decodetree Date: Fri, 2 Jun 2023 16:52:06 +0100 Message-Id: <20230602155223.2040685-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721230487100001 Content-Type: text/plain; charset="utf-8" Convert the insns in the "Barriers" instruction class to decodetree: CLREX, DSB, DMB, ISB and SB. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 92 ++++++++++++++-------------------- 2 files changed, 46 insertions(+), 53 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 1efd436e175..553f6904d9c 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -181,3 +181,10 @@ ERETA 1101011 0100 11111 00001 m:1 11111 111= 11 &reta # ERETAA, ERETAB # that isn't specifically allocated to an instruction must NOP NOP 1101 0101 0000 0011 0010 ---- --- 11111 } + +# Barriers + +CLREX 1101 0101 0000 0011 0011 imm:4 010 11111 +DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 +ISB 1101 0101 0000 0011 0011 imm:4 110 11111 +SB 1101 0101 0000 0011 0011 0000 111 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ecc4b9c1bd3..09258a9854f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1757,67 +1757,56 @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTI= BSP *a) return true; } =20 -static void gen_clrex(DisasContext *s, uint32_t insn) +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) { tcg_gen_movi_i64(cpu_exclusive_addr, -1); + return true; } =20 -/* CLREX, DSB, DMB, ISB */ -static void handle_sync(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int c= rm) +static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a) { + /* We handle DSB and DMB the same way */ TCGBar bar; =20 - if (op1 !=3D 3) { - unallocated_encoding(s); - return; + switch (a->types) { + case 1: /* MBReqTypes_Reads */ + bar =3D TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; + break; + case 2: /* MBReqTypes_Writes */ + bar =3D TCG_BAR_SC | TCG_MO_ST_ST; + break; + default: /* MBReqTypes_All */ + bar =3D TCG_BAR_SC | TCG_MO_ALL; + break; } + tcg_gen_mb(bar); + return true; +} =20 - switch (op2) { - case 2: /* CLREX */ - gen_clrex(s, insn); - return; - case 4: /* DSB */ - case 5: /* DMB */ - switch (crm & 3) { - case 1: /* MBReqTypes_Reads */ - bar =3D TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; - break; - case 2: /* MBReqTypes_Writes */ - bar =3D TCG_BAR_SC | TCG_MO_ST_ST; - break; - default: /* MBReqTypes_All */ - bar =3D TCG_BAR_SC | TCG_MO_ALL; - break; - } - tcg_gen_mb(bar); - return; - case 6: /* ISB */ - /* We need to break the TB after this insn to execute - * a self-modified code correctly and also to take - * any pending interrupts immediately. - */ - reset_btype(s); - gen_goto_tb(s, 0, 4); - return; +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + reset_btype(s); + gen_goto_tb(s, 0, 4); + return true; +} =20 - case 7: /* SB */ - if (crm !=3D 0 || !dc_isar_feature(aa64_sb, s)) { - goto do_unallocated; - } - /* - * TODO: There is no speculation barrier opcode for TCG; - * MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, 4); - return; - - default: - do_unallocated: - unallocated_encoding(s); - return; +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa64_sb, s)) { + return false; } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, 4); + return true; } =20 static void gen_xaflag(void) @@ -2280,9 +2269,6 @@ static void disas_system(DisasContext *s, uint32_t in= sn) return; } switch (crn) { - case 3: /* CLREX, DSB, DMB, ISB */ - handle_sync(s, insn, op1, op2, crm); - break; case 4: /* MSR (immediate) */ handle_msr_i(s, insn, op1, op2, crm); break; --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721255; cv=none; d=zohomail.com; s=zohoarc; b=jmFqrAAzkQmAUCuGseP32f2mNyH4zlb6W5H6e6GqsO7W9pW/YPOGnyi3l/lq8Ywd0w5PhxQUD3bhPwbVgs76cNaUWS+43aVBIHnptHcdeVL1nSHeCwufIBXOSRewXPsyf5hFOiuBICyrMoqLBHIXSj9t5Ijrr/p+f87j3CM0FAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721255; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CVG899GadG9n5+PuNksPKw1TX7s6N642Zf3CKGOWr8s=; b=VCJ+nHAQSoEqxzAz3Kg14NjSwlaRvUA5nM+jyc1G7uyf0yAIUNj56CHKpRA4Gjuie9320BXreNbuhyMNd3zqwrvLh+TQOX/BGOfQGh0ZimBcLDdyu+yytb2WNLP9HMl+hrizfnNcfKpxhmJWz5ZfjUK2YQSJpKceui06efsdZ1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721255575855.9717718832476; Fri, 2 Jun 2023 08:54:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574s-000392-3b; Fri, 02 Jun 2023 11:52:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574q-00037R-Jj for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:32 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574n-0003RC-G4 for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:32 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3f6042d610fso21677075e9.1 for ; Fri, 02 Jun 2023 08:52:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721148; x=1688313148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CVG899GadG9n5+PuNksPKw1TX7s6N642Zf3CKGOWr8s=; b=mcgSSd4Z9UpL9s+ZOn/1rhmcYL43ryPIzlj2a9nbIpUoUQAGq/092q1uPluYkm2OKx JefmrImXZiMYH9tl2+7vHuKrq65y8w2gyYZZ2plxTFUY0NAh7zn14KTMmZkRTLKeOEt3 yjItJk3JdFWb/kso9mL0+sMSEz0MbISXmCFTLhqqKyhGEOZXN/OcZC6npr732tVAAj3G ijmfx+1RU0tGL4Waf1YZLiyTP/gNA397kGcWJ/qBzLRhdF6U7zdczfYV5GZYGI7x7yvH 7rB2Q4qSSFPC6FQAP5/qUC65kJhESF3gzQPgK51cxETzFIfEb0e/HqfnO9p/UvgNgjEe Wivg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721148; x=1688313148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CVG899GadG9n5+PuNksPKw1TX7s6N642Zf3CKGOWr8s=; b=AQRA9fYtTFj4uLBMXh+2ElrNt6r+H+u+jl7o4VHyCnFBc1srgxpfVK/GUccmHuex6S T5mm7hBwJMRCvoknlBRNovzF02BwsPbkpkDk7EpWyMbAvN8Bj/suDon9FroDLJ4/RBiM yb5A/7WKB79dBUZ+hhEGwLwW9HD7oX37dkOQ7MxGX0oHgpSDsQyUhgAz0doqw+QGCcoM Kz+VyQ4+9RM/PWAzwYR3b5AjrS5zFvCT52WfW/8C2841FCDj3oA+TGVN5Ej8lwz/tX30 h3jGzK0OJP4LmQZYTCjI4/57WQLseeixsIgHben0a50L10kuv1OEppEdcDNB+oqZKmB1 XEjQ== X-Gm-Message-State: AC+VfDzHewpPCfkpcpaYdmVVnqE5Sg0y/bNnCZowJvnMkp13EpR/KZm3 Mslj6iu9u6oF9AAlW52WU7XanfBjedWFECh6EUQ= X-Google-Smtp-Source: ACHHUZ6qaCxFDc04BZpy+nOtIFF2XVg8z8bbgL7WmmoAGE/CV3+zfROkN+19RsMctqxRYLOfBhMwzQ== X-Received: by 2002:a1c:7c1a:0:b0:3f6:117:6ed7 with SMTP id x26-20020a1c7c1a000000b003f601176ed7mr2157119wmc.35.1685721148184; Fri, 02 Jun 2023 08:52:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/20] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree Date: Fri, 2 Jun 2023 16:52:07 +0100 Message-Id: <20230602155223.2040685-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721256323100003 Content-Type: text/plain; charset="utf-8" Convert the CFINV, XAFLAG and AXFLAG insns to decodetree. The old decoder handles these in handle_msr_i(), but the architecture defines them as separate instructions from MSR (immediate). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 6 ++++ target/arm/tcg/translate-a64.c | 56 ++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 553f6904d9c..26a0b44cea9 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -188,3 +188,9 @@ CLREX 1101 0101 0000 0011 0011 imm:4 010 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 ISB 1101 0101 0000 0011 0011 imm:4 110 11111 SB 1101 0101 0000 0011 0011 0000 111 11111 + +# PSTATE + +CFINV 1101 0101 0000 0 000 0100 0000 000 11111 +XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 +AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 09258a9854f..33bebe594d1 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1809,9 +1809,25 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } =20 -static void gen_xaflag(void) +static bool trans_CFINV(DisasContext *s, arg_CFINV *a) { - TCGv_i32 z =3D tcg_temp_new_i32(); + if (!dc_isar_feature(aa64_condm_4, s)) { + return false; + } + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); + s->base.is_jmp =3D DISAS_NEXT; + return true; +} + +static bool trans_XAFLAG(DisasContext *s, arg_XAFLAG *a) +{ + TCGv_i32 z; + + if (!dc_isar_feature(aa64_condm_5, s)) { + return false; + } + + z =3D tcg_temp_new_i32(); =20 tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); =20 @@ -1835,10 +1851,17 @@ static void gen_xaflag(void) =20 /* C | Z */ tcg_gen_or_i32(cpu_CF, cpu_CF, z); + + s->base.is_jmp =3D DISAS_NEXT; + return true; } =20 -static void gen_axflag(void) +static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a) { + if (!dc_isar_feature(aa64_condm_5, s)) { + return false; + } + tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ =20 @@ -1847,6 +1870,9 @@ static void gen_axflag(void) =20 tcg_gen_movi_i32(cpu_NF, 0); tcg_gen_movi_i32(cpu_VF, 0); + + s->base.is_jmp =3D DISAS_NEXT; + return true; } =20 /* MSR (immediate) - move immediate to processor state field */ @@ -1859,30 +1885,6 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_TOO_MANY; =20 switch (op) { - case 0x00: /* CFINV */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_4, s)) { - goto do_unallocated; - } - tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); - s->base.is_jmp =3D DISAS_NEXT; - break; - - case 0x01: /* XAFlag */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { - goto do_unallocated; - } - gen_xaflag(); - s->base.is_jmp =3D DISAS_NEXT; - break; - - case 0x02: /* AXFlag */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { - goto do_unallocated; - } - gen_axflag(); - s->base.is_jmp =3D DISAS_NEXT; - break; - case 0x03: /* UAO */ if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721326; cv=none; d=zohomail.com; s=zohoarc; b=i5HB0LJojtR7iWQyA7l6ML5w5pkUEyob0K9fTxDsfR//wY5GVWqzcJxoY0qKca3DUO+alBuu0Iji+Uop88Vo/gmCZF4ohFX2rWj9X2ElAvCz82d/Z767zTHhYB3UM2R7mNG8BzRNL91oT0Uul5jSZq3cMOUAt0e4gU3bV/McZf8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721326; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1lZFx3mv+TDguBUy5+nAam7QazsVWb+5FMKek+p8BwM=; b=YzBeJ5Lb4l+vfgDpaxeIiOM8f3/VfdiVlIPY+BuCTjZV7r61x26vj3na6RObkeUbNipXA80Vgh7spA/dzcjDRJsjZ0TIapqGBQoZlbt/SfCEvLAB5Mk5xa3WhUgyw7yKaurKfrvqnPR8nX6sCZwz7DAGg/ISoLN4Y8tsSEXx5po= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721326353774.8502751860626; Fri, 2 Jun 2023 08:55:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574t-0003A9-6g; Fri, 02 Jun 2023 11:52:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574r-00038Y-Du for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:33 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574o-0003Ri-2A for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:33 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f60b3f32b4so20669235e9.1 for ; Fri, 02 Jun 2023 08:52:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721148; x=1688313148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1lZFx3mv+TDguBUy5+nAam7QazsVWb+5FMKek+p8BwM=; b=HKksRs2+K5XhTjkizZ7CxpVHC9T5D/ma3U3Z9u+3VN7GTlSrU+3oO2iGHqboaQB3Q9 RM/18tgSDen88Y914VA4ZPxS/GQV/5AJcZHbBV6PWe6AUy7UFeRjBPkL4/CTeaxN2WoO 4X79yAWj2g/cVaatrGxvIc+Oo1b9Eg1mU8xmoZWjC1ooV041mLDl4Fdtj2NfHGsNid1G eCZov2jhfRuasjFvQQlefmO4ubFM79NQXvzKe0K9FeC65dG1P6HOQG9p2GHXpxwvP9Ho yS6gyXN8tE4o3Iqelft1B7zlAWI/xBDPnjc0pd1no0dMHpdc9SdbIFUo5jm9A4GzoetV RN9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721148; x=1688313148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1lZFx3mv+TDguBUy5+nAam7QazsVWb+5FMKek+p8BwM=; b=ZBihFnRiEZBj64NoJ5ygvQ0jXN+MIxdVhAdcpfsAS/MSmVqA67QVSDqzpDxVNwSYCq fF86gpk8ZV2JfK7CviruTXimYQzEjfcothY7NFdNeuzzbcmHcI/2AKL5nGfjRsV32JPL dK+lL7cndrNHXbn/jTjXe9tlAfgQT0fINawLcDGT1oGDA8MgxrpH/HKYLdEzd7UkxzHj eimcD1k/WTItlwZR+r03PI0dTW+QY53mfaqOkpskRhDLrz2LZo8Hf8BeCFMkYeRwex8c dYfIF1aFssOVIGObvnzbYjbbuGUThDyVFz4gvGuMObctAiXNTYSZXyhPCEUGY6y1qLAK AHwA== X-Gm-Message-State: AC+VfDzC3feDN673O2YXsRA77m8Xrimp5mGfuV2Z8cd1nCt8Z4cbrnuw GqNSWU9Gja6OGSlyhbMnNkSfmmmCUHm/e/P/ruk= X-Google-Smtp-Source: ACHHUZ54zzWjTFTqIk4BhyAqi9/VHaR1y0lHDU2rFXdhOkA4/ut5axa3OSMS4HEGoAbQPirB9Bl79A== X-Received: by 2002:a05:600c:2303:b0:3f6:f152:1183 with SMTP id 3-20020a05600c230300b003f6f1521183mr2336763wmo.37.1685721148597; Fri, 02 Jun 2023 08:52:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/20] target/arm: Convert MSR (immediate) to decodetree Date: Fri, 2 Jun 2023 16:52:08 +0100 Message-Id: <20230602155223.2040685-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721328513100003 Content-Type: text/plain; charset="utf-8" Convert the MSR (immediate) insn to decodetree. Our implementation has basically no commonality between the different destinations, so we decode the destination register in a64.decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 13 ++ target/arm/tcg/translate-a64.c | 251 ++++++++++++++++----------------- 2 files changed, 136 insertions(+), 128 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 26a0b44cea9..a645dac8d26 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -194,3 +194,16 @@ SB 1101 0101 0000 0011 0011 0000 111 11111 CFINV 1101 0101 0000 0 000 0100 0000 000 11111 XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 + +# These are architecturally all "MSR (immediate)"; we decode the destinati= on +# register too because there is no commonality in our implementation. +@msr_i .... .... .... . ... .... imm:4 ... ..... +MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i +MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i +MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i +MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i +MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i +MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i +MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i +MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i +MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 33bebe594d1..bdc1ee18cdc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1875,124 +1875,130 @@ static bool trans_AXFLAG(DisasContext *s, arg_AXF= LAG *a) return true; } =20 -/* MSR (immediate) - move immediate to processor state field */ -static void handle_msr_i(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int = crm) +static bool trans_MSR_i_UAO(DisasContext *s, arg_i *a) { - int op =3D op1 << 3 | op2; - - /* End the TB by default, chaining is ok. */ - s->base.is_jmp =3D DISAS_TOO_MANY; - - switch (op) { - case 0x03: /* UAO */ - if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_UAO); - } else { - clear_pstate_bits(PSTATE_UAO); - } - gen_rebuild_hflags(s); - break; - - case 0x04: /* PAN */ - if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_PAN); - } else { - clear_pstate_bits(PSTATE_PAN); - } - gen_rebuild_hflags(s); - break; - - case 0x05: /* SPSel */ - if (s->current_el =3D=3D 0) { - goto do_unallocated; - } - gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP)); - break; - - case 0x19: /* SSBS */ - if (!dc_isar_feature(aa64_ssbs, s)) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_SSBS); - } else { - clear_pstate_bits(PSTATE_SSBS); - } - /* Don't need to rebuild hflags since SSBS is a nop */ - break; - - case 0x1a: /* DIT */ - if (!dc_isar_feature(aa64_dit, s)) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_DIT); - } else { - clear_pstate_bits(PSTATE_DIT); - } - /* There's no need to rebuild hflags because DIT is a nop */ - break; - - case 0x1e: /* DAIFSet */ - gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm)); - break; - - case 0x1f: /* DAIFClear */ - gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm)); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ - s->base.is_jmp =3D DISAS_UPDATE_EXIT; - break; - - case 0x1c: /* TCO */ - if (dc_isar_feature(aa64_mte, s)) { - /* Full MTE is enabled -- set the TCO bit as directed. */ - if (crm & 1) { - set_pstate_bits(PSTATE_TCO); - } else { - clear_pstate_bits(PSTATE_TCO); - } - gen_rebuild_hflags(s); - /* Many factors, including TCO, go into MTE_ACTIVE. */ - s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; - } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { - /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. = */ - s->base.is_jmp =3D DISAS_NEXT; - } else { - goto do_unallocated; - } - break; - - case 0x1b: /* SVCR* */ - if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) { - goto do_unallocated; - } - if (sme_access_check(s)) { - int old =3D s->pstate_sm | (s->pstate_za << 1); - int new =3D (crm & 1) * 3; - int msk =3D (crm >> 1) & 3; - - if ((old ^ new) & msk) { - /* At least one bit changes. */ - gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), - tcg_constant_i32(msk)); - } else { - s->base.is_jmp =3D DISAS_NEXT; - } - } - break; - - default: - do_unallocated: - unallocated_encoding(s); - return; + if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { + return false; } + if (a->imm & 1) { + set_pstate_bits(PSTATE_UAO); + } else { + clear_pstate_bits(PSTATE_UAO); + } + gen_rebuild_hflags(s); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_PAN(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + gen_rebuild_hflags(s); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_SPSEL(DisasContext *s, arg_i *a) +{ + if (s->current_el =3D=3D 0) { + return false; + } + gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(a->imm & PSTATE_SP)); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_SBSS(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_ssbs, s)) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_SSBS); + } else { + clear_pstate_bits(PSTATE_SSBS); + } + /* Don't need to rebuild hflags since SSBS is a nop */ + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_DIT(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_dit, s)) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_DIT); + } else { + clear_pstate_bits(PSTATE_DIT); + } + /* There's no need to rebuild hflags because DIT is a nop */ + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_TCO(DisasContext *s, arg_i *a) +{ + if (dc_isar_feature(aa64_mte, s)) { + /* Full MTE is enabled -- set the TCO bit as directed. */ + if (a->imm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + gen_rebuild_hflags(s); + /* Many factors, including TCO, go into MTE_ACTIVE. */ + s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; + return true; + } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { + /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ + return true; + } else { + /* Insn not present */ + return false; + } +} + +static bool trans_MSR_i_DAIFSET(DisasContext *s, arg_i *a) +{ + gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(a->imm)); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a) +{ + gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(a->imm)); + /* Exit the cpu loop to re-evaluate pending IRQs. */ + s->base.is_jmp =3D DISAS_UPDATE_EXIT; + return true; +} + +static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a) +{ + if (!dc_isar_feature(aa64_sme, s) || a->mask =3D=3D 0) { + return false; + } + if (sme_access_check(s)) { + int old =3D s->pstate_sm | (s->pstate_za << 1); + int new =3D a->imm * 3; + + if ((old ^ new) & a->mask) { + /* At least one bit changes. */ + gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), + tcg_constant_i32(a->mask)); + s->base.is_jmp =3D DISAS_TOO_MANY; + } + } + return true; } =20 static void gen_get_nzcv(TCGv_i64 tcg_rt) @@ -2266,18 +2272,7 @@ static void disas_system(DisasContext *s, uint32_t i= nsn) rt =3D extract32(insn, 0, 5); =20 if (op0 =3D=3D 0) { - if (l || rt !=3D 31) { - unallocated_encoding(s); - return; - } - switch (crn) { - case 4: /* MSR (immediate) */ - handle_msr_i(s, insn, op1, op2, crm); - break; - default: - unallocated_encoding(s); - break; - } + unallocated_encoding(s); return; } handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721272; cv=none; d=zohomail.com; s=zohoarc; b=CcEydWA78wGEIkQzI1gXbCvcOuxVkGNGPt5LauJyF3gktfdpCEC0+wZnTQWdnbOpvlvd1oslzTr+0zEf1SkP9J7MFGzXbjiH7u1xjJdjZ0gjay3ddzSxVOvOHawDEyBRY3GqpXl40djXEkv3THjz8sHhejXDIte4o7eEG/Lchis= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721272; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2eo472r8J3U7OZYtDc9uvjFKt5zEODMaDr+F6ZoZiNU=; b=AhEEoO0c0e6EhQiWDq2l1XH/qI5W7DqA5Mktr9hvCRqPWd8WqixE5vD2zuayqKyFXvUr5rJjiiVyoGNqY3/tjiDJ3oUYpG4dMHq/i/WqgOqDLrlKxR1ylRJNV/k34vlw23zFfLLHU/g8cJSI1vKgJPTnAz3Nd346oaD5IX6b31A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721272277947.6877358328129; Fri, 2 Jun 2023 08:54:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574t-0003AP-CH; Fri, 02 Jun 2023 11:52:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574s-00038y-1L for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:34 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574o-0003S2-Mx for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:33 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f68fc6b479so21648565e9.2 for ; Fri, 02 Jun 2023 08:52:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721149; x=1688313149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2eo472r8J3U7OZYtDc9uvjFKt5zEODMaDr+F6ZoZiNU=; b=RrXxNu9X7PUp+GDmBbhv2yDMm08UbEZtD9LktHFoMRFIUF+N9f2Q44dq2pIT+Mji3k aFCXfaeB6sOM01Tc961y7DJsvLHWWAtV3tpDAnm5Wj5wqiBYF0J0pEz4+B96v0tZCPBE UdyvlHIqPmI6FJsM3fQ2y/Y5zwl4m1E74N65lRKUizfxhcC4JAn+KstgJ4OLA/0bQa/F z8n3zL8ZbyGowvyuPHKEPHnkN0EnDUCWlaHlsX7SneGSUwgZNDNrfYTNUwT3p1EKbt8v CeTYtdr17YqY2JRErjl88wyLxOuVIBSI55gDQgDWMbcMbEf63QREz4+CX6+L4ABu7dDM At0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721149; x=1688313149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2eo472r8J3U7OZYtDc9uvjFKt5zEODMaDr+F6ZoZiNU=; b=iBT6Kdt+SLXcbGFoUPFq24pXg1D+PILhxES3YYQ1cJvq1R2Lc1tGF+wKjqKhVRb+Lf AeHBUwVnzFAZ3z9ZBw+sJ26LaTd4ag3cRuvp6Vt2f+NCaQsLZW9nlLiXa8o+hQE1FTTP R18DIQlnjZ6/06SLKyX4pSSCueVZQZmUS1SKQxZ9NkvkxZswQfOQjUIxsMBR574mxyfx IO1rargzrtzbwJosVQmmS6pkaqaVfcUgKRQV9A7VIUj+mtYbsAFLjfV7pm88V5idg/9L R2BhBM1KsTRBL1XtHxCjG6ZHJdqnsu1/bPlRKzP1JfEhdSoKxOEh+VsbJSJNqD9OcJ28 ZgtQ== X-Gm-Message-State: AC+VfDz289zf1SzXSvf3nJRK+Hv/cGnFbv8djWGNnhpn0Kd3kHxJ1wgP az4OLdaFn93MA/9EWoAQsyLgag== X-Google-Smtp-Source: ACHHUZ6iz4GzI2FviRJM78uHqHxd4Vr+k/3/DCiXA4yHM3bT5HYmjr0j30dSy6Am8nByqO5uzfR1bA== X-Received: by 2002:a7b:cb88:0:b0:3f6:f56:5e82 with SMTP id m8-20020a7bcb88000000b003f60f565e82mr2469414wmi.3.1685721149101; Fri, 02 Jun 2023 08:52:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/20] target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree Date: Fri, 2 Jun 2023 16:52:09 +0100 Message-Id: <20230602155223.2040685-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721272808100009 Content-Type: text/plain; charset="utf-8" Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are all essentially the same instruction (system register access). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 ++++++++ target/arm/tcg/translate-a64.c | 32 +++++--------------------------- 2 files changed, 13 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index a645dac8d26..e1a120ea4c0 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -207,3 +207,11 @@ MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 111= 11 @msr_i MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 + +# MRS, MSR (register), SYS, SYSL. These are all essentially the +# same instruction as far as QEMU is concerned. +# NB: op0 is bits [20:19], but op0=3D0b00 is other insns, so we have +# to hand-decode it. +SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D1 +SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D2 +SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D3 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bdc1ee18cdc..8e4d3676992 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2070,7 +2070,7 @@ static void gen_sysreg_undef(DisasContext *s, bool is= read, * These are all essentially the same insn in 'read' and 'write' * versions, with varying op0 fields. */ -static void handle_sys(DisasContext *s, uint32_t insn, bool isread, +static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { @@ -2254,28 +2254,10 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } } =20 -/* System - * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 - * +---------------------+---+-----+-----+-------+-------+-----+------+ - * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | - * +---------------------+---+-----+-----+-------+-------+-----+------+ - */ -static void disas_system(DisasContext *s, uint32_t insn) +static bool trans_SYS(DisasContext *s, arg_SYS *a) { - unsigned int l, op0, op1, crn, crm, op2, rt; - l =3D extract32(insn, 21, 1); - op0 =3D extract32(insn, 19, 2); - op1 =3D extract32(insn, 16, 3); - crn =3D extract32(insn, 12, 4); - crm =3D extract32(insn, 8, 4); - op2 =3D extract32(insn, 5, 3); - rt =3D extract32(insn, 0, 5); - - if (op0 =3D=3D 0) { - unallocated_encoding(s); - return; - } - handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); + handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt); + return true; } =20 /* Exception generation @@ -2382,11 +2364,7 @@ static void disas_b_exc_sys(DisasContext *s, uint32_= t insn) switch (extract32(insn, 25, 7)) { case 0x6a: /* Exception generation / System */ if (insn & (1 << 24)) { - if (extract32(insn, 22, 2) =3D=3D 0) { - disas_system(s, insn); - } else { - unallocated_encoding(s); - } + unallocated_encoding(s); } else { disas_exc(s, insn); } --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721287; cv=none; d=zohomail.com; s=zohoarc; b=cNrebFKYNZ4xLqW4h+XbX6Elugy/5nbjK0L53kiFCO0ZRNQKAotINvpVj2b96GyEQpbQi0nFteSrR7rTh1THxN1KShN+WfUiTNK96xcHKRqm1okrjzouXCokl0OJJKusHUF+bTI1Svaq84vcmr4njPxeKha7GoV89jg+6tkZ3+E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721287; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YSnpw6zs5zZnKAA2d+Gsz/pFbi8gBmglbDw3R5ffAAE=; b=NMuy/WKDULmc6zzTw6f3COylXu8Yzvc5uw9QIg14yh/VQ6JgcsjSKKnzhOAhrhwqkHMxciHoqjzjNs/menfi8tIXctGET3R7ywHQPZMJG6VvHef4B3ol2YIIMFhGtjoVEs0HXJ5diZQm8T4mLuCuEhOQwKOjjIl1z/Z2IZWwAQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721287400695.9899789871426; Fri, 2 Jun 2023 08:54:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574v-0003CJ-9x; Fri, 02 Jun 2023 11:52:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574t-0003AD-3q for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:35 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574p-0003SG-0d for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:34 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f606912ebaso22543415e9.3 for ; Fri, 02 Jun 2023 08:52:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721149; x=1688313149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YSnpw6zs5zZnKAA2d+Gsz/pFbi8gBmglbDw3R5ffAAE=; b=VoBoIokizXRyK0S6OZ57irpBKij3cFKfDgX9tImrj3L+Tsy7XpepiPjjhRRlgh8Vw9 GseTz7GXa9eRbXTZ+gmyi9Nu3dJE9apZLYuqp1ZXAFBro2e4GxgMbWyomJQre/neAaJf inVauwbk5fMqb6lj5ndZxRWmV5fODtCrL1+dXxjdg3uomBe02j8auVFwaVG2PfFhOnl0 JFsuugX5uRS2MfJJmcqf1TK6t2/+QXXAOstBibX7HPIfr8AlDl+urt6ljL01kKbhTM6o +MdgsPcqHsI6XjcbF+8i1MYGFTIo1CWu0u2WrYqC8CFwSM0xWpegvvVgNKSt8b+ISQLb fsoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721149; x=1688313149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YSnpw6zs5zZnKAA2d+Gsz/pFbi8gBmglbDw3R5ffAAE=; b=Ed7fcS0iB6r+T3NJyfKRzk5E2qHQYgB/zsWFJpCscGvjjcu+cxs1wcnqnoMpWTWzoW wYYocZZWJv9MrJlSmq099GYhbYehc9HgnB4uIA3q9RO10AZF/jsb/aGsDxPYiciDOzx6 oD8y+UlD8SLqjYh3tHov6Mm/DGGRQ5wjve2Kf/7zUUaA6U2xMipAny57vaKZpzLu/+6e 6gu+8mQRKeHQFE2JYC9LMKmYNfA1vNeelB9I072qq/x/NkSPS6uMVsc1pqFMrKlo3Gcf 1+lXJz54cfIkT4rORAgzswdsEaIP6bH6cpogZvIm263W3A5WzbHOK4WLgiM621RI3QhT LIWA== X-Gm-Message-State: AC+VfDyMpUUqWeiafXW4zckmcCLiWFDFCyEg16ksRezTNGh8fy8mUxHf ZWde0e2VqcdSxZGeZC+JLGStf6kp6liEvzIwLdg= X-Google-Smtp-Source: ACHHUZ6buzGpIv2fws9GhVrltxc5pEE+OattbTJ/Wj+IMWCw0uB5ClT7te4rO3aXI/bPm8DFodf+jA== X-Received: by 2002:a05:600c:b42:b0:3f1:7581:eaaf with SMTP id k2-20020a05600c0b4200b003f17581eaafmr2258724wmr.4.1685721149504; Fri, 02 Jun 2023 08:52:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/20] target/arm: Convert exception generation instructions to decodetree Date: Fri, 2 Jun 2023 16:52:10 +0100 Message-Id: <20230602155223.2040685-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721288852100007 Content-Type: text/plain; charset="utf-8" Convert the exception generation instructions SVC, HVC, SMC, BRK and HLT to decodetree. The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and DCPS3 just in order to then make them UNDEF; as with DRPS, we don't bother to decode them, but document the patterns in a64.decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 15 +++ target/arm/tcg/translate-a64.c | 173 ++++++++++++--------------------- 2 files changed, 79 insertions(+), 109 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index e1a120ea4c0..aba27047b56 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -215,3 +215,18 @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm= :1 011 11111 SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D1 SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D2 SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D3 + +# Exception generation + +@i16 .... .... ... imm:16 ... .. &i +SVC 1101 0100 000 ................ 000 01 @i16 +HVC 1101 0100 000 ................ 000 10 @i16 +SMC 1101 0100 000 ................ 000 11 @i16 +BRK 1101 0100 001 ................ 000 00 @i16 +HLT 1101 0100 010 ................ 000 00 @i16 +# These insns always UNDEF unless in halting debug state, which +# we don't implement. So we don't need to decode them. The patterns +# are listed here as documentation. +# DCPS1 1101 0100 101 ................ 000 01 @i16 +# DCPS2 1101 0100 101 ................ 000 10 @i16 +# DCPS3 1101 0100 101 ................ 000 11 @i16 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8e4d3676992..94410f6ece5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2260,119 +2260,77 @@ static bool trans_SYS(DisasContext *s, arg_SYS *a) return true; } =20 -/* Exception generation - * - * 31 24 23 21 20 5 4 2 1 0 - * +-----------------+-----+------------------------+-----+----+ - * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | - * +-----------------------+------------------------+----------+ - */ -static void disas_exc(DisasContext *s, uint32_t insn) +static bool trans_SVC(DisasContext *s, arg_i *a) { - int opc =3D extract32(insn, 21, 3); - int op2_ll =3D extract32(insn, 0, 5); - int imm16 =3D extract32(insn, 5, 16); - uint32_t syndrome; - - switch (opc) { - case 0: - /* For SVC, HVC and SMC we advance the single-step state - * machine before taking the exception. This is architecturally - * mandated, to ensure that single-stepping a system call - * instruction works properly. - */ - switch (op2_ll) { - case 1: /* SVC= */ - syndrome =3D syn_aa64_svc(imm16); - if (s->fgt_svc) { - gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); - break; - } - gen_ss_advance(s); - gen_exception_insn(s, 4, EXCP_SWI, syndrome); - break; - case 2: /* HVC= */ - if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - break; - } - /* The pre HVC helper handles cases when HVC gets trapped - * as an undefined insn by runtime configuration. - */ - gen_a64_update_pc(s, 0); - gen_helper_pre_hvc(cpu_env); - gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); - break; - case 3: /* SMC= */ - if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - break; - } - gen_a64_update_pc(s, 0); - gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); - gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); - break; - default: - unallocated_encoding(s); - break; - } - break; - case 1: - if (op2_ll !=3D 0) { - unallocated_encoding(s); - break; - } - /* BRK */ - gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); - break; - case 2: - if (op2_ll !=3D 0) { - unallocated_encoding(s); - break; - } - /* HLT. This has two purposes. - * Architecturally, it is an external halting debug instruction. - * Since QEMU doesn't implement external debug, we treat this as - * it is required for halting debug disabled: it will UNDEF. - * Secondly, "HLT 0xf000" is the A64 semihosting syscall instructi= on. - */ - if (semihosting_enabled(s->current_el =3D=3D 0) && imm16 =3D=3D 0x= f000) { - gen_exception_internal_insn(s, EXCP_SEMIHOST); - } else { - unallocated_encoding(s); - } - break; - case 5: - if (op2_ll < 1 || op2_ll > 3) { - unallocated_encoding(s); - break; - } - /* DCPS1, DCPS2, DCPS3 */ - unallocated_encoding(s); - break; - default: - unallocated_encoding(s); - break; + /* + * For SVC, HVC and SMC we advance the single-step state + * machine before taking the exception. This is architecturally + * mandated, to ensure that single-stepping a system call + * instruction works properly. + */ + uint32_t syndrome =3D syn_aa64_svc(a->imm); + if (s->fgt_svc) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + return true; } + gen_ss_advance(s); + gen_exception_insn(s, 4, EXCP_SWI, syndrome); + return true; } =20 -/* Branches, exception generating and system instructions */ -static void disas_b_exc_sys(DisasContext *s, uint32_t insn) +static bool trans_HVC(DisasContext *s, arg_i *a) { - switch (extract32(insn, 25, 7)) { - case 0x6a: /* Exception generation / System */ - if (insn & (1 << 24)) { - unallocated_encoding(s); - } else { - disas_exc(s, insn); - } - break; - default: + if (s->current_el =3D=3D 0) { unallocated_encoding(s); - break; + return true; } + /* + * The pre HVC helper handles cases when HVC gets trapped + * as an undefined insn by runtime configuration. + */ + gen_a64_update_pc(s, 0); + gen_helper_pre_hvc(cpu_env); + /* Architecture requires ss advance before we do the actual work */ + gen_ss_advance(s); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); + return true; +} + +static bool trans_SMC(DisasContext *s, arg_i *a) +{ + if (s->current_el =3D=3D 0) { + unallocated_encoding(s); + return true; + } + gen_a64_update_pc(s, 0); + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm))); + /* Architecture requires ss advance before we do the actual work */ + gen_ss_advance(s); + gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3); + return true; +} + +static bool trans_BRK(DisasContext *s, arg_i *a) +{ + gen_exception_bkpt_insn(s, syn_aa64_bkpt(a->imm)); + return true; +} + +static bool trans_HLT(DisasContext *s, arg_i *a) +{ + /* + * HLT. This has two purposes. + * Architecturally, it is an external halting debug instruction. + * Since QEMU doesn't implement external debug, we treat this as + * it is required for halting debug disabled: it will UNDEF. + * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. + */ + if (semihosting_enabled(s->current_el =3D=3D 0) && a->imm =3D=3D 0xf00= 0) { + gen_exception_internal_insn(s, EXCP_SEMIHOST); + } else { + unallocated_encoding(s); + } + return true; } =20 /* @@ -14035,9 +13993,6 @@ static bool btype_destination_ok(uint32_t insn, boo= l bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0xa: case 0xb: /* Branch, exception generation and system insns */ - disas_b_exc_sys(s, insn); - break; case 0x4: case 0x6: case 0xc: --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721388; cv=none; d=zohomail.com; s=zohoarc; b=DcsRUtyw+wiRDUVCWYRzCGCbgWkFQDPwjwBCN7kaVmeZfLSZhOFJqZzRqLQIuMbMLR+G3guKCQF8Up3dB/y/7Jfzr/OgRIIPLRKqi+mUVtxntZXFPVdT6NrkYa+ThFAWhkW9ug9BUhAhfWUvBm8eaILJs1eJ27h1VlaRmg2Qof8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721388; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WkGtrZrBF/XjQ2tvFCNg0zZgeoFtvEXOEGm+spnCLHk=; b=C5dbsbUrlqpiEw0o+d8HI1YeEIY4w9LX5cf57cf0tMfFVY0lmEKchNRFaBKzzesN4y5teYw8HN5dSAmoYYIKUeegpjRGDH4SVDi8YZ2Xy149r+nrjM2ShvQ4hZW2sghz277iyLI8EQ7gDF4WUTzxWdmsLp7ZdsYFq4ykJqU1DBo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168572138866031.763190538466574; Fri, 2 Jun 2023 08:56:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574v-0003Cu-RE; Fri, 02 Jun 2023 11:52:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574t-0003BC-SJ for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:35 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574p-0003SQ-EY for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:35 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f68fc6b479so21648775e9.2 for ; Fri, 02 Jun 2023 08:52:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721150; x=1688313150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WkGtrZrBF/XjQ2tvFCNg0zZgeoFtvEXOEGm+spnCLHk=; b=lvf+mFUr6f05s9zZSt4V4A9fnyvGr2ddqurMH2od39kljSjg7tZnlR+zG8R4wICQhD J5W6LFd49wlkaWGtmubMemgV0jFO2PZjBD8GDYJ5HviA4Z74CY6NC4izIMbH4Bbb4Whh 9Ef5IewoD6VWMkYOH1eVI0IpSVJoUOl5fSq+RIIDgxGeD0J7Jag+VIizAgzsPpLboG+j PgcVoWGKEYwGc5S2u68FtA8GaPaEYHRfZt85Oa0k8Jiuq6X7RD6edRSnG546dUWbDM1P aZtlb+Aq64IFBp2a2VGTHbbDFjp8PNYC/Z4RXv31HMr+IvLWjo04px1M2NkEVawRtp4W OijA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721150; x=1688313150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WkGtrZrBF/XjQ2tvFCNg0zZgeoFtvEXOEGm+spnCLHk=; b=O9pPzATSc5RcjA/LNsgQ5sgH0m3o73maNczvMHljV5cVyPiqpkjZerRHVm/nQt0uCr 7CUuMGXBZm7ByBkFUYYax8v1R63K9GbDAidQcj+dqu8/0sQRpMOOz1ggfXuoscgw7zuG ue09kUMgAI/UTBhrOvavs2QOkcXQGqW1Hsnw6Nv5e3fm9017dU8nqQrm1V6w94oJHEci uvCP7f3kbBAHeKPpm3rNfDK0fEdtuiYrmlOpFSvbHf+1Ri1ZdOvXYWmoPZZsrZQwBwTk QlvHYEAq3nuql7zLxOCm4m3g6kfNQOOOAsdaVo0Xl9oqfrxtRZe0Y9QRH+WJChWfSKYY bw8g== X-Gm-Message-State: AC+VfDxW208UupLoTIXUUgpsBMCF6Nj2AUz6URoBx+W4j5m1dduU2rxt 7D599pAqN2tf3PbGc3wtFnooIw== X-Google-Smtp-Source: ACHHUZ7zHDuZp2Qp9GyNiO/LJwYq6jwVn1LdtUyKLbjvmLG5zkDRZAINwGow4QUvJXgy3Gl365xfnQ== X-Received: by 2002:a05:600c:22c7:b0:3f6:e13:b266 with SMTP id 7-20020a05600c22c700b003f60e13b266mr2390564wmg.13.1685721149998; Fri, 02 Jun 2023 08:52:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/20] target/arm: Convert load/store exclusive and ordered to decodetree Date: Fri, 2 Jun 2023 16:52:11 +0100 Message-Id: <20230602155223.2040685-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721390052100001 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store exclusive (STXR, STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR, LDAR, LDLAR) to decodetree. Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding in the legacy decoder where we were not checking that the RES1 bits in the Rs and Rt2 fields were set. The new function ldst_iss_sf() is equivalent to the existing disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field rather than taking an undecoded two-bit opc field and extracting 'ext' from it. Once all the loads and stores have been converted to decodetree disas_ldst_compute_iss_sf() will be unused and can be deleted. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 11 +++ target/arm/tcg/translate-a64.c | 164 ++++++++++++++++++++------------- 2 files changed, 110 insertions(+), 65 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index aba27047b56..b9b32490cef 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -230,3 +230,14 @@ HLT 1101 0100 010 ................ 000 00 = @i16 # DCPS1 1101 0100 101 ................ 000 01 @i16 # DCPS2 1101 0100 101 ................ 000 10 @i16 # DCPS3 1101 0100 101 ................ 000 11 @i16 + +# Loads and stores + +&stxr rn rt rt2 rs sz lasr +&stlr rn rt sz lasr +@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr +@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr +STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR +LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR +STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR +LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 94410f6ece5..2a5c4eea02f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2560,6 +2560,102 @@ static bool disas_ldst_compute_iss_sf(int size, boo= l is_signed, int opc) return regsize =3D=3D 64; } =20 +static bool ldst_iss_sf(int size, bool sign, bool ext) +{ + + if (sign) { + /* + * Signed loads are 64 bit results if we are not going to + * do a zero-extend from 32 to 64 after the load. + * (For a store, sign and ext are always false.) + */ + return !ext; + } else { + /* Unsigned loads/stores work at the specified size */ + return size =3D=3D MO_64; + } +} + +static bool trans_STXR(DisasContext *s, arg_stxr *a) +{ + TCGv_i64 clean_addr; + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + true, a->rn !=3D 31, a->sz); + gen_store_exclusive(s, a->rs, a->rt, a->rt2, clean_addr, a->sz, false); + return true; +} + +static bool trans_LDXR(DisasContext *s, arg_stxr *a) +{ + TCGv_i64 clean_addr; + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + false, a->rn !=3D 31, a->sz); + s->is_ldex =3D true; + gen_load_exclusive(s, a->rt, a->rt2, clean_addr, a->sz, false); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_STLR(DisasContext *s, arg_stlr *a) +{ + TCGv_i64 clean_addr; + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + + /* + * StoreLORelease is the same as Store-Release for QEMU, but + * needs the feature-test. + */ + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { + return false; + } + /* Generate ISS for non-exclusive accesses including LASR. */ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + true, a->rn !=3D 31, a->sz); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, a->sz | MO_ALIGN, true, a-= >rt, + iss_sf, a->lasr); + return true; +} + +static bool trans_LDAR(DisasContext *s, arg_stlr *a) +{ + TCGv_i64 clean_addr; + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { + return false; + } + /* Generate ISS for non-exclusive accesses including LASR. */ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + false, a->rn !=3D 31, a->sz); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, a->sz | MO_ALIGN, false, t= rue, + a->rt, iss_sf, a->lasr); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; +} + /* Load/store exclusive * * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 @@ -2585,71 +2681,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) TCGv_i64 clean_addr; =20 switch (o2_L_o1_o0) { - case 0x0: /* STXR */ - case 0x1: /* STLXR */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); - return; - - case 0x4: /* LDXR */ - case 0x5: /* LDAXR */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, false); - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - return; - - case 0x8: /* STLLR */ - if (!dc_isar_feature(aa64_lor, s)) { - break; - } - /* StoreLORelease is the same as Store-Release for QEMU. */ - /* fall through */ - case 0x9: /* STLR */ - /* Generate ISS for non-exclusive accesses including LASR. */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); - return; - - case 0xc: /* LDLAR */ - if (!dc_isar_feature(aa64_lor, s)) { - break; - } - /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ - /* fall through */ - case 0xd: /* LDAR */ - /* Generate ISS for non-exclusive accesses including LASR. */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, t= rue, - rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - return; - case 0x2: case 0x3: /* CASP / STXP */ if (size & 2) { /* STXP / STLXP */ if (rn =3D=3D 31) { @@ -2704,6 +2735,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) return; } break; + default: + /* Handled in decodetree */ + break; } unallocated_encoding(s); } --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721389; cv=none; d=zohomail.com; s=zohoarc; b=bihRVysXhSFHki25XxlA8Bl8kUIP0yZRHmPv4pWwc0LTGMpIovE5btdj7g2VpXNmF/f0jQYxuKjhvu8eOH59OwIG7f9MORyqbu+mAWS4mqCF6iJBe3SiI2EFvlw25eI7SndvoVhEqaiPj114iHYIYALIkvesNvc+PErjy9mgzgk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721389; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EEoCGtTV/Xe6vXxMlBDKyD8Heo9qu37gFRA53k9Pqe4=; b=GUZamJ79lunZFasMmiDv2fmhq3TXmDYEMh/FNfi2jT4dJ13yafTSLnjH0Vo6mzRFKWPE7uoaYWsGmsHog2gdDMwY8zp0k94Qn+9Gi0UkXsIA0oUbHpGNyPvlW/FtgmyBZ765BTDdHaHV5RJygjifqRHGzRqJPz7DRDJ+Y2qjR9Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721389456397.0733661436883; Fri, 2 Jun 2023 08:56:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574v-0003CL-C0; Fri, 02 Jun 2023 11:52:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574t-0003B8-NP for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:35 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574q-0003Su-2D for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:35 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-30c4c1fd511so1498281f8f.1 for ; Fri, 02 Jun 2023 08:52:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721150; x=1688313150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EEoCGtTV/Xe6vXxMlBDKyD8Heo9qu37gFRA53k9Pqe4=; b=qKIwXDebAZpKEYxq23C063dR1P3XPlQCYs/Ac3qY/YsmnIQUgIrI6QkzkYvqEA8Ttn HmxL+QXSN1HDzzugaWsBQtSHwNOEtdEqpba+4CMdyr/dAauqhhd5K1v68jzfkOnPr44K wE0obCqfXJyZqifLh99yDVnSQ5yybAClVDoo49QFLj8KX6uEwqAQrsKca3Z3pPuliTnJ 0FxROkKMcGj0WtA5JsgnYwH3oPxKpElYf7uwsjdaXwoi/0cYD2XBTfzxlL/98T2hudin pcW5hMad3AiUQQgXm0WoHeEP9c0sUwiJMNcLa7b5cVRpHnUPntsMZJjFMPlNkZ5nKbTg AJ1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721150; x=1688313150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EEoCGtTV/Xe6vXxMlBDKyD8Heo9qu37gFRA53k9Pqe4=; b=FbAxp0+SB1lXs7pbvnUUTVSWzusPWBUbwczKcxjsQv/P5dgOoDlmz1z3ySanP/r7iq t64fd6ajKI7NBlI1lGshzefQyfCyV/KQOgkycBOCz2zOdTvOF2XcMIi/W6ctBeia3Kvs CQXh0ct0IAZnPAYO8wpPW1tymqZyLcNRbRXIqp3ZqyB2YhJWfB8pqw0904JSNLzjnIuo Qshs4xeSQ2nRPzdPrdfL9dnUGP+EgwiXSMYpf+IHfhwLrQVx7JJ6NKaEBXnL7a687Eg8 nSomRwfJeKXp/zVKLTPvLVyMJhCQgBM//J8xt968cQYD+ZmQu0Wxa+Zoej7M3DMNcs68 tldw== X-Gm-Message-State: AC+VfDyF/Xew7pSbx4zAg/xCHtNc5Sp6W7cH7OHGQfgAmTCW53zuijQi Q8LmzkkOwLln+8ttSrrYATgB7c5K+NErWIR8djQ= X-Google-Smtp-Source: ACHHUZ748G3rDpiJReGeSDF1WVMVMMfUgdF3kakoKcfwc8IeEK5Ah0F962Oeb2n+nyBoA/+MmR3AQg== X-Received: by 2002:adf:e606:0:b0:309:5029:b075 with SMTP id p6-20020adfe606000000b003095029b075mr323721wrm.13.1685721150711; Fri, 02 Jun 2023 08:52:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/20] target/arm: Convert LDXP, STXP, CASP, CAS to decodetree Date: Fri, 2 Jun 2023 16:52:12 +0100 Message-Id: <20230602155223.2040685-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721390463100003 Content-Type: text/plain; charset="utf-8" Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP), compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and swap (CAS, CASA, CASAL, CASL) instructions to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 +++ target/arm/tcg/translate-a64.c | 132 ++++++++++++--------------------- 2 files changed, 59 insertions(+), 83 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index b9b32490cef..2b4827384b5 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -237,7 +237,17 @@ HLT 1101 0100 010 ................ 000 00 = @i16 &stlr rn rt sz lasr @stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr @stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr +%imm1_30_p2 30:1 !function=3Dplus_2 +@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=3D%imm1= _30_p2 STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR + +STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP +LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP + +# CASP, CASPA, CASPAL, CASPL +CASP 0 . 001000 0 a:1 1 rs:5 lasr:1 11111 rn:5 rt:5 sz=3D%imm1_= 30_p2 +# CAS, CASA, CASAL, CASL +CAS sz:2 001000 1 a:1 1 rs:5 lasr:1 11111 rn:5 rt:5 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2a5c4eea02f..ce4cf1a3878 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2656,90 +2656,59 @@ static bool trans_LDAR(DisasContext *s, arg_stlr *a) return true; } =20 -/* Load/store exclusive - * - * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 - * +-----+-------------+----+---+----+------+----+-------+------+------+ - * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | - * +-----+-------------+----+---+----+------+----+-------+------+------+ - * - * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit - * L: 0 -> store, 1 -> load - * o2: 0 -> exclusive, 1 -> not - * o1: 0 -> single register, 1 -> register pair - * o0: 1 -> load-acquire/store-release, 0 -> not - */ -static void disas_ldst_excl(DisasContext *s, uint32_t insn) +static bool trans_STXP(DisasContext *s, arg_stxr *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rt2 =3D extract32(insn, 10, 5); - int rs =3D extract32(insn, 16, 5); - int is_lasr =3D extract32(insn, 15, 1); - int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; - int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr; =20 - switch (o2_L_o1_o0) { - case 0x2: case 0x3: /* CASP / STXP */ - if (size & 2) { /* STXP / STLXP */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); - return; - } - if (rt2 =3D=3D 31 - && ((rt | rs) & 1) =3D=3D 0 - && dc_isar_feature(aa64_atomics, s)) { - /* CASP / CASPL */ - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); - return; - } - break; - - case 0x6: case 0x7: /* CASPA / LDXP */ - if (size & 2) { /* LDXP / LDAXP */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, true); - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - return; - } - if (rt2 =3D=3D 31 - && ((rt | rs) & 1) =3D=3D 0 - && dc_isar_feature(aa64_atomics, s)) { - /* CASPA / CASPAL */ - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); - return; - } - break; - - case 0xa: /* CAS */ - case 0xb: /* CASL */ - case 0xe: /* CASA */ - case 0xf: /* CASAL */ - if (rt2 =3D=3D 31 && dc_isar_feature(aa64_atomics, s)) { - gen_compare_and_swap(s, rs, rt, rn, size); - return; - } - break; - default: - /* Handled in decodetree */ - break; + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); } - unallocated_encoding(s); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + true, a->rn !=3D 31, a->sz); + gen_store_exclusive(s, a->rs, a->rt, a->rt2, clean_addr, a->sz, true); + return true; +} + +static bool trans_LDXP(DisasContext *s, arg_stxr *a) +{ + TCGv_i64 clean_addr; + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + false, a->rn !=3D 31, a->sz); + s->is_ldex =3D true; + gen_load_exclusive(s, a->rt, a->rt2, clean_addr, a->sz, true); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_CASP(DisasContext *s, arg_CASP *a) +{ + if (!dc_isar_feature(aa64_atomics, s)) { + return false; + } + if (((a->rt | a->rs) & 1) !=3D 0) { + return false; + } + + gen_compare_and_swap_pair(s, a->rs, a->rt, a->rn, a->sz); + return true; +} + +static bool trans_CAS(DisasContext *s, arg_CAS *a) +{ + if (!dc_isar_feature(aa64_atomics, s)) { + return false; + } + gen_compare_and_swap(s, a->rs, a->rt, a->rn, a->sz); + return true; } =20 /* @@ -4098,9 +4067,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x08: /* Load/store exclusive */ - disas_ldst_excl(s, insn); - break; case 0x18: case 0x1c: /* Load register (literal) */ disas_ld_lit(s, insn); break; --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721321; cv=none; d=zohomail.com; s=zohoarc; b=doJpOnK7pCfvWslsHUaR+zERxfXk2rOlCD6W6j7H+VYm9bQdQdE/ckeS/lfRzAjn8yFNMlQgR60fEeUJRg79TKcimxpzA0ZMstOkh/03FGvyynSu9Dep0v3iYtPnxG5q/p2qBHhj/jQ0hfPPCpUVKmJt5EG3zk9LJlImmDKEFvQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721321; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e6odzKrf0EsTUJUThJ0AIB19OGhJGnKfmzZWI8IgT24=; b=BLkGW2IlPwqGDewROy5o7ck8obMopui/W/Cn4APekjFbVRnkKC7eqVeoLoXeHX3yz/ZAPCh2nSzeEwcib8j8yP4qnQHbs7WmXUrujoHU7Y1ki8v/3p6kjOLz8wr5FCtDqIke+/Yu4LM/d551oUPbaoeqytWFGGeXweaeJm0LcNc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721321194874.2478188620302; Fri, 2 Jun 2023 08:55:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574x-0003F3-EN; Fri, 02 Jun 2023 11:52:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574u-0003C4-Rt for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:36 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574q-0003TJ-MT for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:36 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-30ad752f433so2000685f8f.3 for ; Fri, 02 Jun 2023 08:52:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721151; x=1688313151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=e6odzKrf0EsTUJUThJ0AIB19OGhJGnKfmzZWI8IgT24=; b=r8Wr9+RbJhw20nf7ATclpIL0Gv4Wtgp49boYgMyLiytE6Dhk8vuDV+QOdEhTG+rpCu QgeoNRybCczJJMzZMHhXXCk3WQw0q9HEhyDChs6mMJ3OfQwMUxXohRqTWy/sBHzx10SE diF5iFUxTnzLL64WsqeEbCaeYXLzN/yH8tY3Frjs74iguXvhYc+CDxdtDg4rasYFRrjY P3QU2a3w9Oi3qoNrZmkPUEMG6Bl9t+AUHqxbeUgIm4QtNJDqc0mRPwoh6V5uVQFuaVOz 2o4FCIaj+rnHWKbdhM7EFWB6uGzQvS8YYuhkdGHRDJFWUyV2pFDC/suc20Nel5f2V71a SRow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721151; x=1688313151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e6odzKrf0EsTUJUThJ0AIB19OGhJGnKfmzZWI8IgT24=; b=hFXMyEvGd/nEDFYMl640g41Ec9XpqXQjcdWo0Ff1riLg1u98BSTnuxV6v0ExWzaDmT woV0ToskPlzq0IYu3fXa0+sH+7jMuthPHpt/9vI0v6zxpToLz2gENS30wFyxdsbO3Std E+LY6HouEuukewfIcqZuhuEgY7TV9PZlyxanmpTRHeeiQdthOe92GfEfN5E/s/qWjG6X qX9OpMxDz7jGff+kcvVAHOeXI240kllNipJMlSDk+mHWGxGNrMVQeaXWwYez77Ixc6RX p2D6xHmlJltsVwOoFCgC50boBpFbv7/7z6dYVMj1N/hZAJbsqprQm2gjMyu+X5tQJwme 43Yw== X-Gm-Message-State: AC+VfDxkgtQziuY8UPdLl5R5YcGPDc92V8Y59GSIQBB+bJ432yUf1+dq sXMyO9T/FW7SqFthLENXUA+IUSeLCRh9ZdB74Wo= X-Google-Smtp-Source: ACHHUZ6p18PJm9xaRXLK2ocAM2xTFEdimhlDfK+kKQYYhZQ2U49ksWjpcr8CdKtMBV1a+Vm/mnfyIQ== X-Received: by 2002:adf:e788:0:b0:30a:aeb0:910d with SMTP id n8-20020adfe788000000b0030aaeb0910dmr271530wrm.44.1685721151116; Fri, 02 Jun 2023 08:52:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/20] target/arm: Convert load reg (literal) group to decodetree Date: Fri, 2 Jun 2023 16:52:13 +0100 Message-Id: <20230602155223.2040685-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721322590100003 Content-Type: text/plain; charset="utf-8" Convert the "Load register (literal)" instruction class to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 13 ++++++ target/arm/tcg/translate-a64.c | 73 ++++++++++------------------------ 2 files changed, 33 insertions(+), 53 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 2b4827384b5..e24db340714 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -251,3 +251,16 @@ LDXP 1 . 001000 011 ..... . ..... ..... ...= .. @stxp # inc LDAXP CASP 0 . 001000 0 a:1 1 rs:5 lasr:1 11111 rn:5 rt:5 sz=3D%imm1_= 30_p2 # CAS, CASA, CASAL, CASL CAS sz:2 001000 1 a:1 1 rs:5 lasr:1 11111 rn:5 rt:5 + +&ldlit rt imm sz sign +@ldlit .. ... . .. ................... rt:5 &ldlit imm=3D%imm19 + +LD_lit 00 011 0 00 ................... ..... @ldlit sz=3D2 sign= =3D0 +LD_lit 01 011 0 00 ................... ..... @ldlit sz=3D3 sign= =3D0 +LD_lit 10 011 0 00 ................... ..... @ldlit sz=3D2 sign= =3D1 +LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=3D2 sign= =3D0 +LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3D3 sign= =3D0 +LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=3D4 sign= =3D0 + +# PRFM +NOP 11 011 0 00 ------------------- ----- diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ce4cf1a3878..07bcc700e0b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2711,60 +2711,30 @@ static bool trans_CAS(DisasContext *s, arg_CAS *a) return true; } =20 -/* - * Load register (literal) - * - * 31 30 29 27 26 25 24 23 5 4 0 - * +-----+-------+---+-----+-------------------+-------+ - * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | - * +-----+-------+---+-----+-------------------+-------+ - * - * V: 1 -> vector (simd/fp) - * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, - * 10-> 32 bit signed, 11 -> prefetch - * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) - */ -static void disas_ld_lit(DisasContext *s, uint32_t insn) +static bool trans_LD_lit(DisasContext *s, arg_ldlit *a) { - int rt =3D extract32(insn, 0, 5); - int64_t imm =3D sextract32(insn, 5, 19) << 2; - bool is_vector =3D extract32(insn, 26, 1); - int opc =3D extract32(insn, 30, 2); - bool is_signed =3D false; - int size =3D 2; - TCGv_i64 tcg_rt, clean_addr; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, false); + TCGv_i64 tcg_rt =3D cpu_reg(s, a->rt); + TCGv_i64 clean_addr =3D tcg_temp_new_i64(); =20 - if (is_vector) { - if (opc =3D=3D 3) { - unallocated_encoding(s); - return; - } - size =3D 2 + opc; - if (!fp_access_check(s)) { - return; - } - } else { - if (opc =3D=3D 3) { - /* PRFM (literal) : prefetch */ - return; - } - size =3D 2 + extract32(opc, 0, 1); - is_signed =3D extract32(opc, 1, 1); + gen_pc_plus_diff(s, clean_addr, a->imm); + do_gpr_ld(s, tcg_rt, clean_addr, a->sz + a->sign * MO_SIGN, + false, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a) +{ + /* Load register (literal), vector version */ + TCGv_i64 clean_addr; + + if (!fp_access_check(s)) { + return true; } - - tcg_rt =3D cpu_reg(s, rt); - clean_addr =3D tcg_temp_new_i64(); - gen_pc_plus_diff(s, clean_addr, imm); - if (is_vector) { - do_fp_ld(s, rt, clean_addr, size); - } else { - /* Only unsigned 32bit loads target 32bit registers. */ - bool iss_sf =3D opc !=3D 0; - - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, - false, true, rt, iss_sf, false); - } + gen_pc_plus_diff(s, clean_addr, a->imm); + do_fp_ld(s, a->rt, clean_addr, a->sz); + return true; } =20 /* @@ -4067,9 +4037,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x18: case 0x1c: /* Load register (literal) */ - disas_ld_lit(s, insn); - break; case 0x28: case 0x29: case 0x2c: case 0x2d: /* Load/store pair (all forms) */ disas_ldst_pair(s, insn); --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721336; cv=none; d=zohomail.com; s=zohoarc; b=YBtK5FBcUw0wt4t2UZJOLXDKpm8DTOsNkzYpT009uev79EY+4tqLuBv2Sv2tzoEUbFTtNk7RyIzg8+dsJftSPlqT7OTSThcWg88RW5OR5m1jtoNQbf+jTSsqUObtGrHRGxry0e1HRuIvkMBBeUjc645HNil2SfEXYBNH5T6tbY4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721336; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=77RbFzojTtJ/okh5WW9K0do57l5DLpmb5dkhivoChhA=; b=ZXUuqZpxuq9w/1KxwfKskvz83gRFjq5D5WoQGevUNmFZDU9nUWchSP1+BOJ9er9Tvqr6zzG25dLIN8GysPq9E0FxGaFKXc6Dfzt9RTXHq2yPB3uMJ1ObRRLX/3GAGOneoXvRv11yPeUPQL5VP5VpiNDaKtiCiH1p6/hoz0GxtJw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721336459138.67718168645763; Fri, 2 Jun 2023 08:55:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5750-0003HD-3S; Fri, 02 Jun 2023 11:52:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574v-0003D3-V9 for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:37 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574r-0003Td-1g for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:37 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f606a80d34so21277865e9.0 for ; Fri, 02 Jun 2023 08:52:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721151; x=1688313151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=77RbFzojTtJ/okh5WW9K0do57l5DLpmb5dkhivoChhA=; b=PTJlbABv8hVCQIPt35zz4X+X94uRUZdn/27QNkLhGFb2bTHiNK+vMdibVoZlb4HMGo lVRo/bQxTR+KjgOE4sW+no31jyZFroRJCvcE4xKCPXaU5XcpOdF+yDj94zWQA2EJ0EFn 2gAEbLxaoguQbTgYO1Ejb3biBO8Hj6Y1yXcx4OpLe8XdFVMveS+bqrRtUtfgKZIx5S3U fCYIRkxapNpyP8zPyTxSJuk7dsfndv9QnGXD0sLg1lEIinE9vBBiLMAHF9KN/9n1kkSZ qTol++640szk1rZk8pOyBU30l+4Nw2kWVlJZc9oCFWOKbWMfqiNKLSxQMKaNLaUMrPvg RHxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721151; x=1688313151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=77RbFzojTtJ/okh5WW9K0do57l5DLpmb5dkhivoChhA=; b=f0+58yk8Qd4phcoCDypDqwxYd10LJQYphEaXqTuusqRw9PauCt/6R/embE8X35F5GU UpUpFRhYolW/HOipI6nDbLmyWx2BrYEsZJloeWJtLec/rSG5HbYQAZzYgeXhrQJXA2eq f1mO9sIMvmxKc4g/ZIgt2xW3njwr1rAu3s0hAVY2aRuntgCfy0bNvh9NOdyPPCJJfamc JXWX7p9uY47h71efDO23U4csN5I0FDlfQPHw74SyC/mT+ryhHacqE+AjUq+4hBn+/4ig ZGftH7UgG/n98izptK+beWrFDo4iOtrupLkIXElxhFTmoxWZgNE/NByqUwJlQacZ898+ HY9A== X-Gm-Message-State: AC+VfDxR2SBApYQJEPocg7Ay29YIsdfG/6lRkcrc2sJBBipscm2+Yneo qFxNvktDnYCgauJq3y3b0IU4GIBfKHIFJELbpqw= X-Google-Smtp-Source: ACHHUZ55C3yf9u+o4R8SjepsN6YBUqek5LgjETnCpEebxxM/FT3b1X6F48zOG88LUhvXnligyDrK9A== X-Received: by 2002:a5d:5945:0:b0:309:4176:702 with SMTP id e5-20020a5d5945000000b0030941760702mr292103wri.37.1685721151566; Fri, 02 Jun 2023 08:52:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/20] target/arm: Convert load/store-pair to decodetree Date: Fri, 2 Jun 2023 16:52:14 +0100 Message-Id: <20230602155223.2040685-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721338554100003 Content-Type: text/plain; charset="utf-8" Convert the load/store register pair insns (LDP, STP, LDNP, STNP, LDPSW, STGP) to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 62 +++++++ target/arm/tcg/translate-a64.c | 299 ++++++++++++++------------------- 2 files changed, 192 insertions(+), 169 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index e24db340714..0a3850fe8d5 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -264,3 +264,65 @@ LD_lit_v 10 011 1 00 ................... ..... = @ldlit sz=3D4 sign=3D0 =20 # PRFM NOP 11 011 0 00 ------------------- ----- + +%imms7 15:s7 +&ldstpair rt2 rt rn imm sz sign w p +@ldstpair .. ... . ... . ....... rt2:5 rn:5 rt:5 &ldstpair imm=3D%im= ms7 + +# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches +# so we ignore hints about data access patterns, and handle these like +# plain signed offset. +STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 +LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 + +# STP and LDP: post-indexed +STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D1 w=3D1 +STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D1 w=3D1 +LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D1 w=3D1 + +# STP and LDP: offset +STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D0 w=3D0 +STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 +LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 + +# STP and LDP: pre-indexed +STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D0 w=3D1 +STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D1 +LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D1 + +# STGP: store tag and pair +STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 07bcc700e0b..bd591122628 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2737,181 +2737,146 @@ static bool trans_LD_lit_v(DisasContext *s, arg_l= dlit *a) return true; } =20 -/* - * LDNP (Load Pair - non-temporal hint) - * LDP (Load Pair - non vector) - * LDPSW (Load Pair Signed Word - non vector) - * STNP (Store Pair - non-temporal hint) - * STP (Store Pair - non vector) - * LDNP (Load Pair of SIMD&FP - non-temporal hint) - * LDP (Load Pair of SIMD&FP) - * STNP (Store Pair of SIMD&FP - non-temporal hint) - * STP (Store Pair of SIMD&FP) - * - * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 - * +-----+-------+---+---+-------+---+-----------------------------+ - * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | - * +-----+-------+---+---+-------+---+-------+-------+------+------+ - * - * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW/STGP 01 - * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit - * V: 0 -> GPR, 1 -> Vector - * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, - * 10 -> signed offset, 11 -> pre-index - * L: 0 -> Store 1 -> Load - * - * Rt, Rt2 =3D GPR or SIMD registers to be stored - * Rn =3D general purpose register containing address - * imm7 =3D signed offset (multiple of 4 or 8 depending on size) - */ -static void disas_ldst_pair(DisasContext *s, uint32_t insn) +static void op_addr_ldstpair_pre(DisasContext *s, arg_ldstpair *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_add= r, + uint64_t offset, bool is_store) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rt2 =3D extract32(insn, 10, 5); - uint64_t offset =3D sextract64(insn, 15, 7); - int index =3D extract32(insn, 23, 2); - bool is_vector =3D extract32(insn, 26, 1); - bool is_load =3D extract32(insn, 22, 1); - int opc =3D extract32(insn, 30, 2); - - bool is_signed =3D false; - bool postindex =3D false; - bool wback =3D false; - bool set_tag =3D false; - - TCGv_i64 clean_addr, dirty_addr; - - int size; - - if (opc =3D=3D 3) { - unallocated_encoding(s); - return; - } - - if (is_vector) { - size =3D 2 + opc; - } else if (opc =3D=3D 1 && !is_load) { - /* STGP */ - if (!dc_isar_feature(aa64_mte_insn_reg, s) || index =3D=3D 0) { - unallocated_encoding(s); - return; - } - size =3D 3; - set_tag =3D true; - } else { - size =3D 2 + extract32(opc, 1, 1); - is_signed =3D extract32(opc, 0, 1); - if (!is_load && is_signed) { - unallocated_encoding(s); - return; - } - } - - switch (index) { - case 1: /* post-index */ - postindex =3D true; - wback =3D true; - break; - case 0: - /* signed offset with "non-temporal" hint. Since we don't emulate - * caches we don't care about hints to the cache system about - * data access patterns, and handle this identically to plain - * signed offset. - */ - if (is_signed) { - /* There is no non-temporal-hint version of LDPSW */ - unallocated_encoding(s); - return; - } - postindex =3D false; - break; - case 2: /* signed offset, rn not updated */ - postindex =3D false; - break; - case 3: /* pre-index */ - postindex =3D false; - wback =3D true; - break; - } - - if (is_vector && !fp_access_check(s)) { - return; - } - - offset <<=3D (set_tag ? LOG2_TAG_GRANULE : size); - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - if (!postindex) { + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); + } + + *clean_addr =3D gen_mte_checkN(s, *dirty_addr, is_store, + (a->w || a->rn !=3D 31), 2 << a->sz); +} + +static void op_addr_ldstpair_post(DisasContext *s, arg_ldstpair *a, + TCGv_i64 dirty_addr, uint64_t offset) +{ + if (a->w) { + if (a->p) { + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); + } +} + +static bool trans_STP(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true); + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + do_gpr_st(s, tcg_rt, clean_addr, a->sz, false, 0, false, false); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_gpr_st(s, tcg_rt2, clean_addr, a->sz, false, 0, false, false); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_LDP(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2, tmp; + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false); + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + tmp =3D tcg_temp_new_i64(); + + /* + * Do not modify tcg_rt before recognizing any exception + * from the second load. + */ + do_gpr_ld(s, tmp, clean_addr, a->sz + a->sign * MO_SIGN, + false, false, 0, false, false); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_gpr_ld(s, tcg_rt2, clean_addr, a->sz + a->sign * MO_SIGN, + false, false, 0, false, false); + tcg_gen_mov_i64(tcg_rt, tmp); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_STP_v(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr; + + if (!fp_access_check(s)) { + return true; + } + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true); + do_fp_st(s, a->rt, clean_addr, a->sz); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_fp_st(s, a->rt2, clean_addr, a->sz); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_LDP_v(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr; + + if (!fp_access_check(s)) { + return true; + } + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false); + do_fp_ld(s, a->rt, clean_addr, a->sz); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_fp_ld(s, a->rt2, clean_addr, a->sz); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_STGP(DisasContext *s, arg_ldstpair *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + uint64_t offset =3D a->imm << LOG2_TAG_GRANULE; + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } =20 - if (set_tag) { - if (!s->ata) { - /* - * TODO: We could rely on the stores below, at least for - * system mode, if we arrange to add MO_ALIGN_16. - */ - gen_helper_stg_stub(cpu_env, dirty_addr); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); - } else { - gen_helper_stg(cpu_env, dirty_addr, dirty_addr); - } - } - - clean_addr =3D gen_mte_checkN(s, dirty_addr, !is_load, - (wback || rn !=3D 31) && !set_tag, 2 << si= ze); - - if (is_vector) { - if (is_load) { - do_fp_ld(s, rt, clean_addr, size); - } else { - do_fp_st(s, rt, clean_addr, size); - } - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - if (is_load) { - do_fp_ld(s, rt2, clean_addr, size); - } else { - do_fp_st(s, rt2, clean_addr, size); - } + if (!s->ata) { + /* + * TODO: We could rely on the stores below, at least for + * system mode, if we arrange to add MO_ALIGN_16. + */ + gen_helper_stg_stub(cpu_env, dirty_addr); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); - - if (is_load) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - - /* Do not modify tcg_rt before recognizing any exception - * from the second load. - */ - do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN, - false, false, 0, false, false); - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN, - false, false, 0, false, false); - - tcg_gen_mov_i64(tcg_rt, tmp); - } else { - do_gpr_st(s, tcg_rt, clean_addr, size, - false, 0, false, false); - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_st(s, tcg_rt2, clean_addr, size, - false, 0, false, false); - } + gen_helper_stg(cpu_env, dirty_addr, dirty_addr); } =20 - if (wback) { - if (postindex) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); - } + clean_addr =3D gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz); + + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + do_gpr_st(s, tcg_rt, clean_addr, a->sz, false, 0, false, false); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_gpr_st(s, tcg_rt2, clean_addr, a->sz, false, 0, false, false); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; } =20 /* @@ -4037,10 +4002,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x28: case 0x29: - case 0x2c: case 0x2d: /* Load/store pair (all forms) */ - disas_ldst_pair(s, insn); - break; case 0x38: case 0x39: case 0x3c: case 0x3d: /* Load/store register (all forms) */ disas_ldst_reg(s, insn); --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721285; cv=none; d=zohomail.com; s=zohoarc; b=HyRk5z6YPJ2AK/i+4J54c68kyctB/Kg9i5VxsKDstpOKccJrVtLWXJJVZGtMuS4jy0i+xhFTprsvQyrgBvewfw6Fvf5JB1ljJJDVnWEM27VDGqtY88Al8WnbD/Vw4GK6yUjJXUVir1ZhdkQUnW8uD5RPHUc7vcfJoRagOdg2b88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721285; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0KLmYQ64c8GCMhyYOzgN/W/7tY/GEebqrCmVx7GKA+I=; b=CeRE0WABnQJxk5OgINCkP6IL+UOPns2SAVwWw4vGLy13N4gGRywVXq45cTlMlT35xwyHZGgiKKCZszajMHLnSLbBuOBPKo+N1waDygZvqaJq+c8M2TIjKrutbzc2HAupbqgzGK96XE/bB3XK/ll3X/Pj/r2sD6ij4okvg1n6VNk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721285381352.47566783913067; Fri, 2 Jun 2023 08:54:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574y-0003GE-Io; Fri, 02 Jun 2023 11:52:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574w-0003En-Sh for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:39 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574r-0003UF-EG for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:38 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f606a80d34so21277995e9.0 for ; Fri, 02 Jun 2023 08:52:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721152; x=1688313152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0KLmYQ64c8GCMhyYOzgN/W/7tY/GEebqrCmVx7GKA+I=; b=XfhbR8R9ojg/R0rn11SNDAuMpVuUc0ccglqFEVFdArSWCIS/EJLrZq1517PeZWWaXP lNQ6yzTJMKAKW/siHXEuYvuy2BSv40G7A5qnKjh1eUy5jZfbyLUyPF4ldo8wdqzadPN7 hxouJOkXVKgvJRV5QRj5htpRqVRxz4bbcaGpHc9WBHj8ohkn4xLkP6H1ey6LDMBk7pcL r4X7NmizrRx+DqTlaTiMwNAkBkrlneeDXITDuaaGmr2azAFMzNfsIO4VGGN3VvVzyFrQ z6V99NcKQHrt3HR394Oi6lpHe5ycBTIIlEQWMkIQpzUGr7NIEHvwtAH7K0M/RN2gpge9 zboA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721152; x=1688313152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0KLmYQ64c8GCMhyYOzgN/W/7tY/GEebqrCmVx7GKA+I=; b=QmWOjoAuJIDHZn36xL/Mk0yrSeomSl7ha6CMO4O7JCuXoZjPgVdnzrSc4zcwdTE4Cy vhin1yPrIJKaajHWWs4W2h7kPFWSsjpSjlVuyeHnnp/qhWQCgKYOFHwC9wdGTNnYKMED yGkZrdPaltCPWMkX90P8S/8vtJMTVdUzwOQ+S8HavTSbmy8xGpETAzviJx3i352nFfvT fmidxnkps2VvNVu8FA7ytPRUx+fHtey58CL8GCClqFHvpfqti5ugnUxQfzIKJZD4DExP 8j2fcp6F2pMNHKjTIJnkDsYtl8nAKkSQrkUTmrj3kCm68Mgqtt9yaF5fQnXbtXKdnc2U rQEA== X-Gm-Message-State: AC+VfDxpeHnCFHewh9GFP2uIHp/qS1fGL5NpQcOyRGz+PNTpgYmMNV0b txbu2telxw7MywMzPx8Kcy6AixpFSDbT3lYpLjA= X-Google-Smtp-Source: ACHHUZ4rm+HGTqreIHk9JOOoy+a0jmAB196C7pTdC3QV6i90qUXKsiw3ZBhWJGdEmjMe+A/aMS566Q== X-Received: by 2002:a7b:ce0d:0:b0:3f6:2ee:698e with SMTP id m13-20020a7bce0d000000b003f602ee698emr2047747wmc.7.1685721152034; Fri, 02 Jun 2023 08:52:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/20] target/arm: Convert ld/st reg+imm9 insns to decodetree Date: Fri, 2 Jun 2023 16:52:15 +0100 Message-Id: <20230602155223.2040685-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721286125100001 Content-Type: text/plain; charset="utf-8" Convert the load and store instructions which use a 9-bit immediate offset to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 69 ++++++++++++ target/arm/tcg/translate-a64.c | 198 +++++++++++++-------------------- 2 files changed, 148 insertions(+), 119 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 0a3850fe8d5..4dfb7bbdc2e 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -326,3 +326,72 @@ LDP_v 10 101 1 011 1 ....... ..... ..... ...= .. @ldstpair sz=3D4 sign=3D0 p STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 + +# Load/store register (unscaled immediate) +&ldst_imm rt rn imm sz sign w p unpriv ext +@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D0 +@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D1 +@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D1 w=3D1 +@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D1 = p=3D0 w=3D0 + +STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D1 + +# PRFM : prefetch memory: a no-op for QEMU +NOP 11 111 0 00 10 0 --------- 00 ----- ----- + +STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bd591122628..76e3e7b13bf 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2879,131 +2879,96 @@ static bool trans_STGP(DisasContext *s, arg_ldstpa= ir *a) return true; } =20 -/* - * Load/store (immediate post-indexed) - * Load/store (immediate pre-indexed) - * Load/store (unscaled immediate) - * - * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * - * idx =3D 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeb= ack) - 10 -> unprivileged - * V =3D 0 -> non-vector - * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - */ -static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) +static void op_addr_ldst_imm_pre(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_add= r, + uint64_t offset, bool is_store) { - int rn =3D extract32(insn, 5, 5); - int imm9 =3D sextract32(insn, 12, 9); - int idx =3D extract32(insn, 10, 2); - bool is_signed =3D false; - bool is_store =3D false; - bool is_extended =3D false; - bool is_unpriv =3D (idx =3D=3D 2); - bool iss_valid; - bool post_index; - bool writeback; int memidx; =20 - TCGv_i64 clean_addr, dirty_addr; - - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4 || is_unpriv) { - unallocated_encoding(s); - return; - } - is_store =3D ((opc & 1) =3D=3D 0); - if (!fp_access_check(s)) { - return; - } - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - if (idx !=3D 0) { - unallocated_encoding(s); - return; - } - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - } - - switch (idx) { - case 0: - case 2: - post_index =3D false; - writeback =3D false; - break; - case 1: - post_index =3D true; - writeback =3D true; - break; - case 3: - post_index =3D false; - writeback =3D true; - break; - default: - g_assert_not_reached(); - } - - iss_valid =3D !is_vector && !writeback; - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - if (!post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } + memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, + a->w || a->rn !=3D 31, + a->sz, a->unpriv, memidx); +} =20 - memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); - clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, - writeback || rn !=3D 31, - size, is_unpriv, memidx); - - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, size); - } else { - do_fp_ld(s, rt, clean_addr, size); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - - if (is_store) { - do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, - iss_valid, rt, iss_sf, false); - } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_= SIGN, - is_extended, memidx, - iss_valid, rt, iss_sf, false); +static void op_addr_ldst_imm_post(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 dirty_addr, uint64_t offset) +{ + if (a->w) { + if (a->p) { + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } +} =20 - if (writeback) { - TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); - if (post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); - } - tcg_gen_mov_i64(tcg_rn, dirty_addr); +static bool trans_STR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true); + + tcg_rt =3D cpu_reg(s, a->rt); + + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_st_memidx(s, tcg_rt, clean_addr, a->sz, memidx, + iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false); + + tcg_rt =3D cpu_reg(s, a->rt); + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_ld_memidx(s, tcg_rt, clean_addr, a->sz + a->sign * MO_SIGN, + a->ext, memidx, iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_STR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + + if (!fp_access_check(s)) { + return true; } + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true); + do_fp_st(s, a->rt, clean_addr, a->sz); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + + if (!fp_access_check(s)) { + return true; + } + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false); + do_fp_ld(s, a->rt, clean_addr, a->sz); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; } =20 /* @@ -3467,12 +3432,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t= insn) switch (extract32(insn, 24, 2)) { case 0: if (extract32(insn, 21, 1) =3D=3D 0) { - /* Load/store register (unscaled immediate) - * Load/store immediate pre/post-indexed - * Load/store register unprivileged - */ - disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); - return; + break; } switch (extract32(insn, 10, 2)) { case 0: --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721308; cv=none; d=zohomail.com; s=zohoarc; b=XcoaapAD/4B0UnpgplSwQ2t4ZpmzVay4A0EhHnoaS4NhIbyvn85CavAnVKbnqcUQCCGYLFWmnGkXRr4vieO90yfs21tX9jwlsKnsqBgMZOlK2/E87cG9jJFubTRqRwsR0Dvxabm6BCagldcjmdi23Vn5SdniB+buSQ0d5FEuG9w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721308; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Onk7PmZ4RBQAtbMiPPN1lZWPtyNK/KqMsN/VDDn6saA=; b=e/RSzE2WqmAj2Tq+B+zuauAADBY10jScCnHgKKjyo14+E1jnsCzYeh4xRCUaeTzNMVSgj+d4oh9MfYCUwTU2xcv6imVzBtJMoFqoaO2XBwKgUw1gQ5lxQUDCwbe53+FgSQoMcsVK4qYMPodOHVTKYYV8p9Yu13N3gRNrIJKITyU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721308418381.4882177069379; Fri, 2 Jun 2023 08:55:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574z-0003Gk-7a; Fri, 02 Jun 2023 11:52:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574w-0003E1-EL for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:38 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574r-0003Wl-S5 for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:38 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f70fc4682aso20970075e9.1 for ; Fri, 02 Jun 2023 08:52:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721152; x=1688313152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Onk7PmZ4RBQAtbMiPPN1lZWPtyNK/KqMsN/VDDn6saA=; b=SV17jwX3+/BB7Y6y54mehkElp9jug4n2SlhFh5+eqwvkLtsxvcBXJkETkDalkxc/n1 4PpE+Hua/GI4K6a/kjuzcEYEYwPO6h0fMntNQ5SILtJLzhxo39SHZ8510wAnwa2F3EC1 JwgjpYCf9sjQfRHDT/YkayJq8HESTUmf0uWpCBlaANrPjCsYTIrNiHKPnVkWmk6S+rvJ FenxlSUIjAKT5I0cx7vCVeVwjRk16gdku7NEUUY49yDCXCQR5WI0B9fxH6mFQtQyBGuc 7OU4hMWM6RXs7qg30Jx2QUeFipE/zlp2QJN+jDHT4ZhNFO4hPjhi3k6OMQh+oeGrlhRn G4kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721152; x=1688313152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Onk7PmZ4RBQAtbMiPPN1lZWPtyNK/KqMsN/VDDn6saA=; b=MPGHopeixWG8j0L4ba8V62aP9OxPMYflIZ/uNP7uZMbxENurhzgtF44qqkDifj+LS+ KhIjrOEnaU1CAUkmKmXa1euJhWgiin8WbFNDZ6y1wbX1VUqkENmBPA9LcLza0zmxD7pT zcSs7K/ZxbdvSiWRE8bIjksh/vhehFPwQBMPut4PbFvPRsHTUElqWi/6QBlZzlJTm20+ PC4AnzMlHB3m3ZiQYTmaqhplH9rM5NSUA14+sR+1Tqn+qn41YyUEl866gTtwJpkvVEvs /zlkqDpbG4ZDzVNDl8W8mf3HqrP82MePiNVNd2jxVArkgdvIKjOk3yWZ819Iv6cfk4N3 OA2A== X-Gm-Message-State: AC+VfDzptuMp5Paq3D88gGrkwSLOl3nO2D2dkSWBSeGK+zwdFhYSWxZ+ dwFiAF/XGwL/iu8JwqQFkFig5w== X-Google-Smtp-Source: ACHHUZ4aOSFPOOrt2j+Hzkm9pHAwRCRzzM1isxbIWTp3rUxLMjITEA8xMZNL3NaZeUOzxJR8RIjkOA== X-Received: by 2002:a05:600c:21d0:b0:3f6:389:73b1 with SMTP id x16-20020a05600c21d000b003f6038973b1mr2328167wmj.6.1685721152531; Fri, 02 Jun 2023 08:52:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/20] target/arm: Convert LDR/STR with 12-bit immediate to decodetree Date: Fri, 2 Jun 2023 16:52:16 +0100 Message-Id: <20230602155223.2040685-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721308984100001 Content-Type: text/plain; charset="utf-8" Convert the LDR and STR instructions which use a 12-bit immediate offset to decodetree. We can reuse the existing LDR and STR trans functions for these. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 25 ++++++++ target/arm/tcg/translate-a64.c | 103 +++++---------------------------- 2 files changed, 41 insertions(+), 87 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 4dfb7bbdc2e..c3a6d0b740a 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -395,3 +395,28 @@ STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... = ..... @ldst_imm_pre sign=3D0 STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 + +# Load/store with an unsigned 12 bit immediate, which is scaled by the +# element size. The function gets the sz:imm and returns the scaled immedi= ate. +%uimm_scaled 10:12 sz:3 !function=3Duimm_scaled + +@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=3D0= p=3D0 w=3D0 imm=3D%uimm_scaled + +STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D0 +LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D1 +LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D2 +LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D3 +LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D0 +LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D1 +LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D2 +LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D1 sz=3D0 +LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D1 sz=3D1 + +# PRFM +NOP 11 111 0 01 10 ------------ ----- ----- + +STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 76e3e7b13bf..9607e55cc59 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -56,6 +56,22 @@ enum a64_shift_type { A64_SHIFT_TYPE_ROR =3D 3 }; =20 +/* + * Helpers for extracting complex instruction fields + */ + +/* + * For load/store with an unsigned 12 bit immediate scaled by the element + * size. The input has the immediate field in bits [14:3] and the element + * size in [2:0]. + */ +static int uimm_scaled(DisasContext *s, int x) +{ + unsigned imm =3D x >> 3; + unsigned scale =3D extract32(x, 0, 3); + return imm << scale; +} + /* * Include the generated decoders. */ @@ -3067,90 +3083,6 @@ static void disas_ldst_reg_roffset(DisasContext *s, = uint32_t insn, } } =20 -/* - * Load/store (unsigned immediate) - * - * 31 30 29 27 26 25 24 23 22 21 10 9 5 - * +----+-------+---+-----+-----+------------+-------+------+ - * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | - * +----+-------+---+-----+-----+------------+-------+------+ - * - * For non-vector: - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - * For vector: - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated - * opc<0>: 0 -> store, 1 -> load - * Rn: base address register (inc SP) - * Rt: target register - */ -static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) -{ - int rn =3D extract32(insn, 5, 5); - unsigned int imm12 =3D extract32(insn, 10, 12); - unsigned int offset; - - TCGv_i64 clean_addr, dirty_addr; - - bool is_store; - bool is_signed =3D false; - bool is_extended =3D false; - - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4) { - unallocated_encoding(s); - return; - } - is_store =3D !extract32(opc, 0, 1); - if (!fp_access_check(s)) { - return; - } - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - } - - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - offset =3D imm12 << size; - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); - - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, size); - } else { - do_fp_ld(s, rt, clean_addr, size); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, - true, rt, iss_sf, false); - } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, - is_extended, true, rt, iss_sf, false); - } - } -} - /* Atomic memory operations * * 31 30 27 26 24 22 21 16 15 12 10 5 0 @@ -3446,9 +3378,6 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) return; } break; - case 1: - disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); - return; } unallocated_encoding(s); } --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721244; cv=none; d=zohomail.com; s=zohoarc; b=CfUzZ7HxuXEzsTg4ESbo7/btHaOiisxnzymB4HBTt93grkPTUgERdoinmVDow+Ra9J0DtMhK523YrRsFzRiPJGZ8mmplFRRXfAGvWrU9YxaRRzKXvFB56OEMLK61gBCD5g2vyyUXfcou3JMtav0hpHSsH9BJQReJFb1DTZlY/9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721244; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AJK9ynd718AWUtAFuAFb493t5xX258KsKMcz4WYMoiw=; b=ksH51oqztLLY9QjEW3CSMsAaw95utblb5sVZH5QNoI1XdOI8GH6UuwJGGrheKTXcJZch+u8JgRXsS9KWV3s7nC1701Cfe1qy2/CB9NiyRK+1SGsuKrqrB/2IUPH+waX/hR1ogZrwBZcfTtfXj6sAC5PrX1n65k40/vLlL1CvuBc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721244172265.7048100310892; Fri, 2 Jun 2023 08:54:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q574z-0003Gp-94; Fri, 02 Jun 2023 11:52:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574y-0003Fq-2u for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:40 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574s-0003XG-DJ for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:39 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f6e13940daso22402985e9.0 for ; Fri, 02 Jun 2023 08:52:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721153; x=1688313153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AJK9ynd718AWUtAFuAFb493t5xX258KsKMcz4WYMoiw=; b=t+vrC+4/J/tflF9XKJ9xaNYP4lLpnNcXbo1JAZq8Wgd4iKFS5NSUuN4IqyG8Zq+Yeq IPt04BVb/nyKIXWVsornWVe8HpLViENCTogvTr7YUdj+N9cEqDzEnoHRUHXqqAz8cUHp 7m2t76+2IFOUZvrm3ACivLtOOlNN0ZgM3IhY/ivIv2IZ3JnbEhQMIyrdfNJhc3/4XlqM f9S3nJsNR5VvovIH1BJpVA67mQi2HUYm7lVCjjP7qaSqvndWHU12EBs5aHiXXSIFIP7h qIxl1sAR4+CIYzOM8WtAv38Q+Hcvb6QBP6dMzJhqXRQwlxjtpL8o0LwwjXqjqEH6idzl MdOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721153; x=1688313153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AJK9ynd718AWUtAFuAFb493t5xX258KsKMcz4WYMoiw=; b=McXU5dZ6ZCb+t9KX8XSNIz2o0f5m/tr5Cn72bKjjxv3J+xfhUk7Q+M9cB402JUL37E 2UjoI9OTRbm3rraTeKyaV8/3sotHDWWkSTJ+igIILoW290oyyS5cgQbUuBCA7hEvLLg1 54UzSPXCw1D7hoNeoeegZvdVfcPvMkyRFpLW+YQean7ufaCaBhSHgKDiOcsBzrE6DM6H EboKvdFEiglPDZIp5bEvbSEiYDRh529JNuUwAP1f1W77ohXCkKMssUzw/Q5vFo20vgla GGWjExJ2jJn9GfZq7f1gb+OFt1D5+uGVY2tZw4BO6O8QKVcDTVrOZQgm3NCAWe9e7hn7 5V4Q== X-Gm-Message-State: AC+VfDxA+L8iDlxQn6olaBIicqmKbIAmFAKkFCUcXHui1TzQZAbdotP3 RCipl6g/gX1+B56RbLyz+jB+yRzuJaAyJ9yC0EU= X-Google-Smtp-Source: ACHHUZ5HCGMjVtm7mfnyOcpKQu31G3bdniL0mDYNLPAEsKVluFuXl22RJrAZ50em+WoB2TTd4Ovtsg== X-Received: by 2002:a05:600c:2298:b0:3f5:db0f:4a74 with SMTP id 24-20020a05600c229800b003f5db0f4a74mr2399665wmf.21.1685721152982; Fri, 02 Jun 2023 08:52:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/20] target/arm: Convert LDR/STR reg+reg to decodetree Date: Fri, 2 Jun 2023 16:52:17 +0100 Message-Id: <20230602155223.2040685-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721246296100003 Content-Type: text/plain; charset="utf-8" Convert the LDR and STR instructions which take a register plus register offset to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 22 +++++ target/arm/tcg/translate-a64.c | 163 +++++++++++++++------------------ 2 files changed, 96 insertions(+), 89 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c3a6d0b740a..189a30b1552 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -420,3 +420,25 @@ STR_v_i sz:2 111 1 01 00 ............ ..... ..= ... @ldst_uimm sign=3D0 ext=3D STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 + +# Load/store with register offset +&ldst rm rn rt sign ext sz opt s +@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst +STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D0 +LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D1 +LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D2 +LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D3 +LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D0 +LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D1 +LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D2 +LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D1 sz=3D0 +LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D1 sz=3D1 + +# PRFM +NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- + +STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 +LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 9607e55cc59..c3eb51e99ff 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2987,100 +2987,87 @@ static bool trans_LDR_v_i(DisasContext *s, arg_lds= t_imm *a) return true; } =20 -/* - * Load/store (register offset) - * - * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ - * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ - * - * For non-vector: - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - * For vector: - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated - * opc<0>: 0 -> store, 1 -> load - * V: 1 -> vector/simd - * opt: extend encoding (see DecodeRegExtend) - * S: if S=3D1 then scale (essentially index by sizeof(size)) - * Rt: register to transfer into/out of - * Rn: address register or SP for base - * Rm: offset register or ZR for offset - */ -static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) +static void op_addr_ldst_pre(DisasContext *s, arg_ldst *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr, + bool is_store) { - int rn =3D extract32(insn, 5, 5); - int shift =3D extract32(insn, 12, 1); - int rm =3D extract32(insn, 16, 5); - int opt =3D extract32(insn, 13, 3); - bool is_signed =3D false; - bool is_store =3D false; - bool is_extended =3D false; + TCGv_i64 tcg_rm; =20 - TCGv_i64 tcg_rm, clean_addr, dirty_addr; - - if (extract32(opt, 1, 1) =3D=3D 0) { - unallocated_encoding(s); - return; - } - - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4) { - unallocated_encoding(s); - return; - } - is_store =3D !extract32(opc, 0, 1); - if (!fp_access_check(s)) { - return; - } - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); =20 - tcg_rm =3D read_cpu_reg(s, rm, 1); - ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); + tcg_rm =3D read_cpu_reg(s, a->rm, 1); + ext_and_shift_reg(tcg_rm, tcg_rm, a->opt, a->s ? a->sz : 0); =20 - tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); + tcg_gen_add_i64(*dirty_addr, *dirty_addr, tcg_rm); + *clean_addr =3D gen_mte_check1(s, *dirty_addr, is_store, true, a->sz); +} =20 - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, size); - } else { - do_fp_ld(s, rt, clean_addr, size); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, - true, rt, iss_sf, false); - } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, - is_extended, true, rt, iss_sf, false); - } +static bool trans_LDR(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; } + + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false); + tcg_rt =3D cpu_reg(s, a->rt); + do_gpr_ld(s, tcg_rt, clean_addr, a->sz + a->sign * MO_SIGN, + a->ext, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_STR(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true); + tcg_rt =3D cpu_reg(s, a->rt); + do_gpr_st(s, tcg_rt, clean_addr, a->sz, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_LDR_v(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + if (!fp_access_check(s)) { + return true; + } + + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false); + do_fp_ld(s, a->rt, clean_addr, a->sz); + return true; +} + +static bool trans_STR_v(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + if (!fp_access_check(s)) { + return true; + } + + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true); + do_fp_st(s, a->rt, clean_addr, a->sz); + return true; } =20 /* Atomic memory operations @@ -3357,7 +3344,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) static void disas_ldst_reg(DisasContext *s, uint32_t insn) { int rt =3D extract32(insn, 0, 5); - int opc =3D extract32(insn, 22, 2); bool is_vector =3D extract32(insn, 26, 1); int size =3D extract32(insn, 30, 2); =20 @@ -3371,8 +3357,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) disas_ldst_atomic(s, insn, size, rt, is_vector); return; case 2: - disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); - return; + break; default: disas_ldst_pac(s, insn, size, rt, is_vector); return; --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721357; cv=none; d=zohomail.com; s=zohoarc; b=RHxSmzvQEFB35UQ+a+pNEjdG3huTxMICpMwCNEuZzTlp5tjAKe3ptfPBlwqE39vcuXtXWnV2vNnKj8uxUh0e6jWrm7bcuOWTvJ5ukLfXItiaJy2G3yQfHGGDwus0Y+lMclvLQJdDjAS9zHh22JJdtheqdkS2br5PKv3zuSdT9CE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721357; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a4i0A8Mu1QFnQmDW94246VyJQXPq6h6YfEV1eAsIzvI=; b=BhvEAfGIWFHjjo0jkH1Ajc5RZ+VHU+AeWRtM2Lk/GbaE963aBKqwvj5KrA36VEE/z24+e0hrnLiucEIE7Sk73ISNAbXIQZP25QX6E7D398AuSF2gXMQb9RqylnPV9h5iA21GUMpF904xQ6lKyOYUrbkWOHV9JRaASWVXSWVNwuM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168572135775367.84071545298059; Fri, 2 Jun 2023 08:55:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5750-0003HC-2t; Fri, 02 Jun 2023 11:52:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574y-0003Fu-4A for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:40 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574s-0003Xe-Rl for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:39 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f6042d605dso20943875e9.2 for ; Fri, 02 Jun 2023 08:52:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721153; x=1688313153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=a4i0A8Mu1QFnQmDW94246VyJQXPq6h6YfEV1eAsIzvI=; b=HsgjNAeTHApXLoYtagNnBMbH+mSTSu7kepIQt/yql5udHw3KFSFUCjapUGEZm8QuEO 36K3gR5stEfVeutJCliDGOg0/LlvV6Zp+4LCaYmsywrr4EI2CQMahjtZu3LfHNTvBEKs cPt78hHIKWVbmEqyqqV+FytqxHqyWptdPE3wzF1ySD/igZWwAJUEbS2kA2Q1VNWNpC8N nExbyFqMY8D4oAECQL9pyxcxv92053KJlBJbhUdRLvSLliry6YzBG1m8sXkZyv0PRkvt jD+XiLkR/8UVstFivCZ6JzUgEmEcKX7hisTKkYR/82GH7Mk8v1yumFXxUEgwWlttnYZl DJMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721153; x=1688313153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a4i0A8Mu1QFnQmDW94246VyJQXPq6h6YfEV1eAsIzvI=; b=A9DWjIeL8UnPMfNHjLG2c4YzFw+7OqaiqTmPx1Nbj4KD8rVPr9P6dgESGcIm6rGJFV e463X+SnhfgHEzKkyk7fOFsgJZZ7GNTvhQycFVYwHdI8ngHbmOmeLR/zeOQDbtAv5oec ADQ1PlY1gR9DTk3sGW+JxNbfNoN22Dh3Yz4+sM9pNTZ7TrnPVOsbnNqxCHbeFkxt9gp2 8wZRWOKV22xMaLCDejSnlYWcaJU5i+VG0Z4K6ZUcDVYljxGi8DYIoIH0zP5Mo8BfD2l9 3iUR5+YtXusn2mkUVAEpiodw6WCujs7QxIiFb1vvSoHD1UeK8R+mZF3903/JpTv9eYxo HDGg== X-Gm-Message-State: AC+VfDw9rjAk8cYYBezrq41pDoOdKduVrcLqibwQOXJKFMGcEFfYvAF7 DFVxnqJciTg0nB4uiFcnCma3nANpQhszI08G4N8= X-Google-Smtp-Source: ACHHUZ62nkEPXYguvphz2Tyvvg6lR2erhccBhNTxKmv6tfZjRrMc0fhzf96SjVmSJb5BaoJqn7BmnA== X-Received: by 2002:a7b:ce89:0:b0:3f6:552:8722 with SMTP id q9-20020a7bce89000000b003f605528722mr2203106wmj.18.1685721153405; Fri, 02 Jun 2023 08:52:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/20] target/arm: Convert atomic memory ops to decodetree Date: Fri, 2 Jun 2023 16:52:18 +0100 Message-Id: <20230602155223.2040685-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721358749100003 Content-Type: text/plain; charset="utf-8" Convert the insns in the atomic memory operations group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 15 ++++ target/arm/tcg/translate-a64.c | 148 ++++++++++++--------------------- 2 files changed, 67 insertions(+), 96 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 189a30b1552..69635586718 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -442,3 +442,18 @@ STR_v sz:2 111 1 00 00 1 ..... ... . 10 ....= . ..... @ldst sign=3D0 ext=3D0 STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 + +# Atomic memory operations +&atomic rs rn rt a r sz +@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic +LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic +LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic +LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic +LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic +LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic +LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic +LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic +LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic +SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic + +LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c3eb51e99ff..4e3bebab8e0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3070,111 +3070,31 @@ static bool trans_STR_v(DisasContext *s, arg_ldst = *a) return true; } =20 -/* Atomic memory operations - * - * 31 30 27 26 24 22 21 16 15 12 10 5 0 - * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ - * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | - * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ - * - * Rt: the result register - * Rn: base address or SP - * Rs: the source register for the operation - * V: vector flag (always 0 as of v8.3) - * A: acquire flag - * R: release flag - */ -static void disas_ldst_atomic(DisasContext *s, uint32_t insn, - int size, int rt, bool is_vector) + +static bool do_atomic_ld(DisasContext *s, arg_atomic *a, AtomicThreeOpFn *= fn, + int sign, bool invert) { - int rs =3D extract32(insn, 16, 5); - int rn =3D extract32(insn, 5, 5); - int o3_opc =3D extract32(insn, 12, 4); - bool r =3D extract32(insn, 22, 1); - bool a =3D extract32(insn, 23, 1); - TCGv_i64 tcg_rs, tcg_rt, clean_addr; - AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D s->be_data | size | MO_ALIGN; + MemOp mop =3D s->be_data | a->sz | MO_ALIGN | sign; + TCGv_i64 clean_addr, tcg_rs, tcg_rt; =20 - if (is_vector || !dc_isar_feature(aa64_atomics, s)) { - unallocated_encoding(s); - return; - } - switch (o3_opc) { - case 000: /* LDADD */ - fn =3D tcg_gen_atomic_fetch_add_i64; - break; - case 001: /* LDCLR */ - fn =3D tcg_gen_atomic_fetch_and_i64; - break; - case 002: /* LDEOR */ - fn =3D tcg_gen_atomic_fetch_xor_i64; - break; - case 003: /* LDSET */ - fn =3D tcg_gen_atomic_fetch_or_i64; - break; - case 004: /* LDSMAX */ - fn =3D tcg_gen_atomic_fetch_smax_i64; - mop |=3D MO_SIGN; - break; - case 005: /* LDSMIN */ - fn =3D tcg_gen_atomic_fetch_smin_i64; - mop |=3D MO_SIGN; - break; - case 006: /* LDUMAX */ - fn =3D tcg_gen_atomic_fetch_umax_i64; - break; - case 007: /* LDUMIN */ - fn =3D tcg_gen_atomic_fetch_umin_i64; - break; - case 010: /* SWP */ - fn =3D tcg_gen_atomic_xchg_i64; - break; - case 014: /* LDAPR, LDAPRH, LDAPRB */ - if (!dc_isar_feature(aa64_rcpc_8_3, s) || - rs !=3D 31 || a !=3D 1 || r !=3D 0) { - unallocated_encoding(s); - return; - } - break; - default: - unallocated_encoding(s); - return; - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= size); - - if (o3_opc =3D=3D 014) { - /* - * LDAPR* are a special case because they are a simple load, not a - * fetch-and-do-something op. - * The architectural consistency requirements here are weaker than - * full load-acquire (we only need "load-acquire processor consist= ent"), - * but we choose to implement them as full LDAQ. - */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, - true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - return; - } - - tcg_rs =3D read_cpu_reg(s, rs, true); - tcg_rt =3D cpu_reg(s, rt); - - if (o3_opc =3D=3D 1) { /* LDCLR */ + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, + a->rn !=3D 31, a->sz); + tcg_rs =3D read_cpu_reg(s, a->rs, true); + tcg_rt =3D cpu_reg(s, a->rt); + if (invert) { tcg_gen_not_i64(tcg_rs, tcg_rs); } - - /* The tcg atomic primitives are all full barriers. Therefore we + /* + * The tcg atomic primitives are all full barriers. Therefore we * can ignore the Acquire and Release bits of this instruction. */ fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); =20 if (mop & MO_SIGN) { - switch (size) { + switch (a->sz) { case MO_8: tcg_gen_ext8u_i64(tcg_rt, tcg_rt); break; @@ -3190,6 +3110,44 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, g_assert_not_reached(); } } + return true; +} + +TRANS_FEAT(LDADD, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_add_= i64, 0, false) +TRANS_FEAT(LDCLR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_and_= i64, 0, true) +TRANS_FEAT(LDEOR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_xor_= i64, 0, false) +TRANS_FEAT(LDSET, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_or_i= 64, 0, false) +TRANS_FEAT(LDSMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_sma= x_i64, MO_SIGN, false) +TRANS_FEAT(LDSMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_smi= n_i64, MO_SIGN, false) +TRANS_FEAT(LDUMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_uma= x_i64, 0, false) +TRANS_FEAT(LDUMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_umi= n_i64, 0, false) +TRANS_FEAT(SWP, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_xchg_i64, 0,= false) + +static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a) +{ + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + TCGv_i64 clean_addr; + + if (!dc_isar_feature(aa64_atomics, s) || + !dc_isar_feature(aa64_rcpc_8_3, s)) { + return false; + } + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, + a->rn !=3D 31, a->sz); + /* + * LDAPR* are a special case because they are a simple load, not a + * fetch-and-do-something op. + * The architectural consistency requirements here are weaker than + * full load-acquire (we only need "load-acquire processor consistent"= ), + * but we choose to implement them as full LDAQ. + */ + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, a->sz, false, + true, a->rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; } =20 /* @@ -3354,8 +3312,6 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) } switch (extract32(insn, 10, 2)) { case 0: - disas_ldst_atomic(s, insn, size, rt, is_vector); - return; case 2: break; default: --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721261; cv=none; d=zohomail.com; s=zohoarc; b=hOsc8KpYBXOvk+0ZKJ5UtS/Reu2/6saZtPYCj8q56rLNVXL6r6BElKAboF2a/K0kgXdl8+U8EGXdH1vXZ/ZNCY4URGUnYT3Bwz+GSvWx6yb554/JxWOpoaS0DlFYNtQqbWSaA4z2sS678igZYfDnR9h3GGX56EV7mR3t0NJocg4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721261; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u4r1oCLiGdCB4dNpcQXNpSWSHb5cjgZ/DorGnYp8sLE=; b=AV/+Hc4cxCIwFl9JbmL8gOqGI/wk3q8B9gw+IyHwplsC6W+8Sa+Bw/2VfNCFaBM+Uz2n9ExzKI5tk2pDlU3AzzCksRqqvrMrD+fPGB3Btk6Y3fTTywG7TvJ9J6gDTepI3QZ48sLlKrltiyPD+ZgXdLi6/CyQA4qM5vZOhZlTMKQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168572126158083.41794311978788; Fri, 2 Jun 2023 08:54:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5753-0003Lc-NY; Fri, 02 Jun 2023 11:52:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574z-0003Gq-A6 for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:41 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574t-0003Xq-7S for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:41 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f6ef9a928fso20905395e9.3 for ; Fri, 02 Jun 2023 08:52:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721154; x=1688313154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=u4r1oCLiGdCB4dNpcQXNpSWSHb5cjgZ/DorGnYp8sLE=; b=ny/9EIG5SPmoMa7BNV1fe1qCYpy7AniYzJTVpkeMod4CbndKAygvfEJ5jbMD2a7QRn x5mgnKszQc1G3DievK/v0Q66zm+sSo0SwlM2vSFOCEY4Cf2EajawPSYVDVwKvhEsQbqS S9UgNF6Zy4KEDN9NVTohrnvN+LnBuc4RrLaxGyMwIP+uc/0a3n4fmLnMEAmwIRsTr5cu WVOsQp/E+fH7fvAea7i9m63vO9T/HLpcMHD6NQsKbFOtJUYyp1XPmd3wz1UGdgmlRIb6 QK6f6R0q+WhYBP/gVOJ/HUWutLtpYutUFdXn27C/87PJOvWpf4rbTHoyMKWpJIgUgI93 pxMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721154; x=1688313154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u4r1oCLiGdCB4dNpcQXNpSWSHb5cjgZ/DorGnYp8sLE=; b=lgaUU3/ePC86rCizH2hwCHcxwiwXP4MzjHuQygq12j2tQP5LtIAWpIC1MaAjd/c16M Gh0MXXCy4AXGpnZP0tiG4ky8tWb/VrJYazV43vL4LfnnS8eCImxlxZwYycXJ4Lf1ZGBX 6v9rK1YOzc8zISxn0qvEGvqahjd7ZvflKLLcGewDzH6TtobNPmJbSh4SX01cJfXPPxj8 /1YJlHJT+vDFUcWtYWC+d9nElfGQPiJqrntXaepkZH+HygpaorRd/ppYF3UoNHAakveB Yzze05P375DzEShGUNNTkmtKsAPlurTPXZRlYPtwlQf2r7WTSFN8qWuQXxMkV3XvoShO d40w== X-Gm-Message-State: AC+VfDxDDNiXGFtRYAQs/fNH4dxGguThilkXDBT6Utdr+sfSTQL9z04i C04R4ltBr/4z94ZWrKz4VNMh5ANzfsszoHwiAiQ= X-Google-Smtp-Source: ACHHUZ4GdDg1ZU5D2ZHnKPejK9r4Brus4/G3p88ep7lrISoghcWpHi0jOjwfLso29Q1pFFeJwbEF/A== X-Received: by 2002:a05:600c:217:b0:3f7:5d:4a17 with SMTP id 23-20020a05600c021700b003f7005d4a17mr2131457wmi.4.1685721153845; Fri, 02 Jun 2023 08:52:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/20] target/arm: Convert load (pointer auth) insns to decodetree Date: Fri, 2 Jun 2023 16:52:19 +0100 Message-Id: <20230602155223.2040685-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721262005100001 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store register (pointer authentication) group ot decodetree: LDRAA, LDRAB. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 83 +++++++--------------------------- 2 files changed, 23 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 69635586718..2ea85312bba 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -457,3 +457,10 @@ LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... = ..... @atomic SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic =20 LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 + +# Load/store register (pointer authentication) + +# LDRA immediate is 10 bits signed and scaled, but the bits aren't all con= tiguous +%ldra_imm 22:s1 12:9 !function=3Dtimes_2 + +LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=3D%ldra_= imm diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4e3bebab8e0..10a6fc4efb7 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3150,42 +3150,22 @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR = *a) return true; } =20 -/* - * PAC memory operations - * - * 31 30 27 26 24 22 21 12 11 10 5 0 - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * - * Rt: the result register - * Rn: base address or SP - * V: vector flag (always 0 as of v8.3) - * M: clear for key DA, set for key DB - * W: pre-indexing flag - * S: sign for imm9. - */ -static void disas_ldst_pac(DisasContext *s, uint32_t insn, - int size, int rt, bool is_vector) +static bool trans_LDRA(DisasContext *s, arg_LDRA *a) { - int rn =3D extract32(insn, 5, 5); - bool is_wback =3D extract32(insn, 11, 1); - bool use_key_a =3D !extract32(insn, 23, 1); - int offset; TCGv_i64 clean_addr, dirty_addr, tcg_rt; =20 - if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { - unallocated_encoding(s); - return; + /* Load with pointer authentication */ + if (!dc_isar_feature(aa64_pauth, s)) { + return false; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); =20 if (s->pauth_active) { - if (use_key_a) { + if (!a->m) { gen_helper_autda(dirty_addr, cpu_env, dirty_addr, tcg_constant_i64(0)); } else { @@ -3194,23 +3174,21 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, } } =20 - /* Form the 10-bit signed, scaled offset. */ - offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); - offset =3D sextract32(offset << size, 0, 10 + size); - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, - is_wback || rn !=3D 31, size); + a->w || a->rn !=3D 31, 3); =20 - tcg_rt =3D cpu_reg(s, rt); - do_gpr_ld(s, tcg_rt, clean_addr, size, - /* extend */ false, /* iss_valid */ !is_wback, - /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); + tcg_rt =3D cpu_reg(s, a->rt); + do_gpr_ld(s, tcg_rt, clean_addr, 3, + /* extend */ false, /* iss_valid */ !a->w, + /* iss_srt */ a->rt, /* iss_sf */ true, /* iss_ar */ false); =20 - if (is_wback) { - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + if (a->w) { + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } + return true; } =20 /* @@ -3298,31 +3276,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, u= int32_t insn) } } =20 -/* Load/store register (all forms) */ -static void disas_ldst_reg(DisasContext *s, uint32_t insn) -{ - int rt =3D extract32(insn, 0, 5); - bool is_vector =3D extract32(insn, 26, 1); - int size =3D extract32(insn, 30, 2); - - switch (extract32(insn, 24, 2)) { - case 0: - if (extract32(insn, 21, 1) =3D=3D 0) { - break; - } - switch (extract32(insn, 10, 2)) { - case 0: - case 2: - break; - default: - disas_ldst_pac(s, insn, size, rt, is_vector); - return; - } - break; - } - unallocated_encoding(s); -} - /* AdvSIMD load/store multiple structures * * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 @@ -3832,10 +3785,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x38: case 0x39: - case 0x3c: case 0x3d: /* Load/store register (all forms) */ - disas_ldst_reg(s, insn); - break; case 0x0c: /* AdvSIMD load/store multiple structures */ disas_ldst_multiple_struct(s, insn); break; --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721267; cv=none; d=zohomail.com; s=zohoarc; b=BhS//thfa/WoGrub3VHInFDcm+rlMz60FmLcTHMbd58DmFtlDzvY+JaWq7PUFk6ibfgAxy64gY/VJb9s8JPf6hyqll6zUyr25Z6izW8wiuU4XZGio9m9regxHhc4o2NVveSFoWLuZOvqPt/jGXi6U8gaV2gsnQmpOl7HrL6UTH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721267; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JfVx2Kw/t7FJ/1OcwZhRCEKMkqtcz8J5PlkevWU/G8w=; b=KXqT4wpLL87gOyXEDoOsfBlV9iQ8SA+fPDHUbkOV4IRnDSQ+X4AQHsQS7+bBZzjiyLp+qauK6nTaUS+37h8EGCW9XIopxk63DLcZRTvKWVF6gZXVnQMBrqT3tUeQH1WkH5liF/ARB7izUDsApuG3tpr2sX07fRoCji/80z/EzsI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721267745944.1341046887117; Fri, 2 Jun 2023 08:54:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5752-0003KK-2g; Fri, 02 Jun 2023 11:52:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q574z-0003H0-LV for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:41 -0400 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574u-0003YH-6e for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:41 -0400 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f4b0a0b557so2987333e87.1 for ; Fri, 02 Jun 2023 08:52:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721154; x=1688313154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JfVx2Kw/t7FJ/1OcwZhRCEKMkqtcz8J5PlkevWU/G8w=; b=uCTXQ9Q2byZnGQjGGsmPl+KwDRH3s9xJYPn5+L6dEiAlFZUJeay4mW+wQkkPLll8s+ EAvS8VK88usd3iIveoFJizq4CqGsk5xN1U2pQEJCoR4IlG+0n3zCKVaSBL2ZPCO7Q4sM FHPkj1Cp7/w85B32dKEA6q4j1XJ10DZfMKCSCXRqZ9gbfLU3FsowjB+0+/chQqfXBQMt lIh9BOudovR+09OC882jZiJEYRzePQeyurVrqPSNqviDcOtBDjKG8eFS9fK7bt9fAGzO 7L5Rp4WSisZs4yPB4GMu4eE4qfDPWf1skzM1fgzqEkxb/Z1MX3+6gibW2XcqiF2Hetxk H0Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721154; x=1688313154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JfVx2Kw/t7FJ/1OcwZhRCEKMkqtcz8J5PlkevWU/G8w=; b=TOZQz3J/mz7gVquvWLg2OCmX1qq+/+24lu0w0d+ENnCD3s8kGMGNyqBQ9TOso5B2PU jaO25VDmyGxp2tZqX0XRgLQSb1NKo77Y0XP7uS1rcdaZX01O3U+Q0xPBK6lborXgAXhS A1BwE4WlMNvKfO65UT6AdSKBmMLa2Yb7QcWO0yGRQI73t+oHClhZCIbl3hhxG0eQyb/S lBX/Tpxp5Dd09f3Cy3FDKunwJAtjrfctET0nl1TqgJpixI8tyc+tQoop0kYw5JUYesew AQpxWadX6AtY+CWJzzWhKlEUwfdAEpNb5zKQ1BRtboihWAo/IhMHUjOyv112RNDd76Ht tJPg== X-Gm-Message-State: AC+VfDwUrweK8t4/MpGY/TuhCPLe3tMkvsWR4NqMqs0lXYsCqGAMBjjF fHl8cse7EGypxjF6qe5OtGKavxUT09TZ2H3zCCM= X-Google-Smtp-Source: ACHHUZ5NULUlrg3548WKfIBRaViSEldUBWvLwSvNUzOlYCBoEy9IhjSYtb8go9Ct1Ydteza7V0zR9w== X-Received: by 2002:ac2:4428:0:b0:4f2:5c4b:e69b with SMTP id w8-20020ac24428000000b004f25c4be69bmr2388741lfl.67.1685721154307; Fri, 02 Jun 2023 08:52:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/20] target/arm: Convert LDAPR/STLR (imm) to decodetree Date: Fri, 2 Jun 2023 16:52:20 +0100 Message-Id: <20230602155223.2040685-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721268198100001 Content-Type: text/plain; charset="utf-8" Convert the instructions in the LDAPR/STLR (unscaled immediate) group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 +++ target/arm/tcg/translate-a64.c | 129 +++++++++++---------------------- 2 files changed, 54 insertions(+), 85 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 2ea85312bba..f75c227629b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -464,3 +464,13 @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5= rt:5 %ldra_imm 22:s1 12:9 !function=3Dtimes_2 =20 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=3D%ldra_= imm + +&ldapr_stlr_i rn rt imm sz sign ext +@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i +STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i si= gn=3D0 ext=3D0 +LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i si= gn=3D0 ext=3D0 +LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D0 +LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D1 +LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D2 +LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D0 +LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 10a6fc4efb7..1cfd1cd7037 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2560,22 +2560,12 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, } } =20 -/* Update the Sixty-Four bit (SF) registersize. This logic is derived +/* + * Compute the ISS.SF bit for syndrome information if an exception + * is taken on a load or store. This indicates whether the instruction + * is accessing a 32-bit or 64-bit register. This logic is derived * from the ARMv8 specs for LDR (Shared decode for all encodings). */ -static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) -{ - int opc0 =3D extract32(opc, 0, 1); - int regsize; - - if (is_signed) { - regsize =3D opc0 ? 32 : 64; - } else { - regsize =3D size =3D=3D 3 ? 64 : 32; - } - return regsize =3D=3D 64; -} - static bool ldst_iss_sf(int size, bool sign, bool ext) { =20 @@ -3191,89 +3181,60 @@ static bool trans_LDRA(DisasContext *s, arg_LDRA *a) return true; } =20 -/* - * LDAPR/STLR (unscaled immediate) - * - * 31 30 24 22 21 12 10 5 0 - * +------+-------------+-----+---+--------+-----+----+-----+ - * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | - * +------+-------------+-----+---+--------+-----+----+-----+ - * - * Rt: source or destination register - * Rn: base register - * imm9: unscaled immediate offset - * opc: 00: STLUR*, 01/10/11: various LDAPUR* - * size: size of load/store - */ -static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) +static bool trans_LDAPR_i(DisasContext *s, arg_ldapr_stlr_i *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int offset =3D sextract32(insn, 12, 9); - int opc =3D extract32(insn, 22, 2); - int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr, dirty_addr; - bool is_store =3D false; - bool extend =3D false; - bool iss_sf; - MemOp mop; + MemOp mop =3D a->sz | MO_ALIGN | (a->sign ? MO_SIGN : 0); + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); =20 if (!dc_isar_feature(aa64_rcpc_8_4, s)) { - unallocated_encoding(s); - return; + return false; } =20 /* TODO: ARMv8.4-LSE SCTLR.nAA */ - mop =3D size | MO_ALIGN; =20 - switch (opc) { - case 0: /* STLURB */ - is_store =3D true; - break; - case 1: /* LDAPUR* */ - break; - case 2: /* LDAPURS* 64-bit variant */ - if (size =3D=3D 3) { - unallocated_encoding(s); - return; - } - mop |=3D MO_SIGN; - break; - case 3: /* LDAPURS* 32-bit variant */ - if (size > 1) { - unallocated_encoding(s); - return; - } - mop |=3D MO_SIGN; - extend =3D true; /* zero-extend 32->64 after signed load */ - break; - default: - g_assert_not_reached(); - } - - iss_sf =3D disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) !=3D 0, opc= ); - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); clean_addr =3D clean_data_tbi(s, dirty_addr); =20 - if (is_store) { - /* Store-Release semantics */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, tr= ue); - } else { - /* - * Load-AcquirePC semantics; we implement as the slightly more - * restrictive Load-Acquire. - */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, - extend, true, rt, iss_sf, true); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + /* + * Load-AcquirePC semantics; we implement as the slightly more + * restrictive Load-Acquire. + */ + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, a->ext, true, + a->rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; +} + +static bool trans_STLR_i(DisasContext *s, arg_ldapr_stlr_i *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop =3D a->sz | MO_ALIGN; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { + return false; } + + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); + clean_addr =3D clean_data_tbi(s, dirty_addr); + + /* Store-Release semantics */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, mop, true, a->rt, iss_sf, = true); + return true; } =20 /* AdvSIMD load/store multiple structures @@ -3794,8 +3755,6 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x19: if (extract32(insn, 21, 1) !=3D 0) { disas_ldst_tag(s, insn); - } else if (extract32(insn, 10, 2) =3D=3D 0) { - disas_ldst_ldapr_stlr(s, insn); } else { unallocated_encoding(s); } --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721384; cv=none; d=zohomail.com; s=zohoarc; b=AyN9102OYfaqPJcNA3+9KieYCkHRIKM68AQyB1nrXN8JAPgY+bHaRYEHhzFrk+JvsWBNGB5wwF3aICMMDHiZyOjJjNAdUa9pvE21BuF+BX8LzBZXyR80opIbJtf/jG/NMCibOCm8fcabo9uutARQeYSFfLvvQkpy35p23uZ1NiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721384; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jllionc+JgJjvq4QQ6r5ZoOKBY+t8VVmTtaXZPvRIHM=; b=MqYVoDNWhnNnemcZSNQv5RAC543A2Ogqww1Drs12GSXtHISxtGTBLa9E9KMKDNzVwCnryzA+U7NXi1DjoyO1V2npv2qCJg7pg5Yyw5Ww5oiacJkf2Ez43CJ9uQbW9gd4C20G23FDIyN2swhmGl5ymwn6Hrr5bsUdizuDS/3ay10= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721384453861.0418871887008; Fri, 2 Jun 2023 08:56:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5754-0003MQ-BB; Fri, 02 Jun 2023 11:52:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5750-0003Hx-Q5 for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:42 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574u-0003YQ-Cr for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:42 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f6da07ff00so22234535e9.3 for ; Fri, 02 Jun 2023 08:52:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721155; x=1688313155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jllionc+JgJjvq4QQ6r5ZoOKBY+t8VVmTtaXZPvRIHM=; b=xu/qXTBYSDdiFte0HmxfcszNM5IS5IHOAo7U/071c+5ehPruapgsmuYOEjoTnsxexn JSYBpvUlaBVCmYyTQeSGtrrq1mwUVJ0TAeIhVJSJLTFc46vbo2r5uCjIjOo2ND1YzMNd 87MXp3Sf7K/nFhT3H/1dUNVV1jvfa4JMWdUowmP3+7nSg3ccdFXzAVM4DTPJFn9Q+ftc 2XvBITFw1+xBtIvj2G2k6xeGDfMrhTMNeK5mh9IDkwXb9C5vw7og0OJwgEIzwpMpbc12 R9VDbCbffvDKc30H8pjnh+jq2z3b2bgrw3abgZ6zV6q4j+WzRsiSdoj86CTXQkUPfNKo rQ1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721155; x=1688313155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jllionc+JgJjvq4QQ6r5ZoOKBY+t8VVmTtaXZPvRIHM=; b=foaCcHMnX3u3t25VL8KcTweKSu3Anf/+3AhYkL65Y4VbzbRPyDEaPrZBewcQ/H43nO /XWk7f53J6lhRGtpsQkeQocfy0L4ZL720SdQdcsujseT3eKqJNRbZPIkKXuFtEN/BWzH Fs6HBDad4eQ1EJrjLTZ6nfBbTloGz6aazNXbJA1dWOk1/VGPd5lZcS6EIqZfj4hjX1hm p1NrAmMpTlR2hh8YIVXwsjfsywbwLH8ToYUChOV2FqtaPJhWg4NtwRMBVDMlgw/oI3pJ 27QhS+cEsu8aUECL71ieUrMZZgovd+/f0IcEES5iU5vv+9GHpyl/moizPQ0x8dg2s3Bs UPPw== X-Gm-Message-State: AC+VfDxrOgLXLlcRJGqp4i6KQLiU7771ngMA1HwyAj9GqPSA7EsKEKN4 bu0Lb62I/j3hciwN9D8Y8e++Og== X-Google-Smtp-Source: ACHHUZ5jkQlsl/wNLNcAK3FFd5lEFfwSMNIBLniK1nSszTw50YvgNF2D9bhhzReM++fmEfxGb0xOLg== X-Received: by 2002:a7b:ca46:0:b0:3f1:789d:ad32 with SMTP id m6-20020a7bca46000000b003f1789dad32mr2417412wml.11.1685721154792; Fri, 02 Jun 2023 08:52:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 18/20] target/arm: Convert load/store (multiple structures) to decodetree Date: Fri, 2 Jun 2023 16:52:21 +0100 Message-Id: <20230602155223.2040685-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721386142100001 Content-Type: text/plain; charset="utf-8" Convert the instructions in the ASIMD load/store multiple structures instruction classes to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 20 +++ target/arm/tcg/translate-a64.c | 220 ++++++++++++++++----------------- 2 files changed, 129 insertions(+), 111 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index f75c227629b..12d331b4c2a 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -474,3 +474,23 @@ LDAPR_i 01 011001 10 0 ......... 00 ..... ....= . @ldapr_stlr_i sign=3D1 ext LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D2 LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D0 LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D1 + +# Load/store multiple structures +# The 4-bit opcode in [15:12] encodes repeat count and structure elements +&ldst_mult rm rn rt sz q p rpt selem +@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult +ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D4 +ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt= =3D4 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D3 +ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt= =3D3 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 +ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 + +LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D4 +LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt= =3D4 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D3 +LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt= =3D3 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 +LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1cfd1cd7037..c3b22a74dd5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3237,99 +3237,28 @@ static bool trans_STLR_i(DisasContext *s, arg_ldapr= _stlr_i *a) return true; } =20 -/* AdvSIMD load/store multiple structures - * - * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 - * +---+---+---------------+---+-------------+--------+------+------+-----= -+ - * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt = | - * +---+---+---------------+---+-------------+--------+------+------+-----= -+ - * - * AdvSIMD load/store multiple structures (post-indexed) - * - * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 - * +---+---+---------------+---+---+---------+--------+------+------+-----= -+ - * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt = | - * +---+---+---------------+---+---+---------+--------+------+------+-----= -+ - * - * Rt: first (or only) SIMD&FP register to be transferred - * Rn: base address or SP - * Rm (post-index only): post-index register (when !31) or size dependent = #imm - */ -static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) +static bool trans_LD_mult(DisasContext *s, arg_ldst_mult *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rm =3D extract32(insn, 16, 5); - int size =3D extract32(insn, 10, 2); - int opcode =3D extract32(insn, 12, 4); - bool is_store =3D !extract32(insn, 22, 1); - bool is_postidx =3D extract32(insn, 23, 1); - bool is_q =3D extract32(insn, 30, 1); TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp endian, align, mop; =20 int total; /* total bytes */ int elements; /* elements per vector */ - int rpt; /* num iterations */ - int selem; /* structure elements */ int r; + int size =3D a->sz; =20 - if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { - unallocated_encoding(s); - return; + if (!a->p && a->rm !=3D 0) { + /* For non-postindexed accesses the Rm field must be 0 */ + return false; } - - if (!is_postidx && rm !=3D 0) { - unallocated_encoding(s); - return; + if (size =3D=3D 3 && !a->q && a->selem !=3D 1) { + return false; } - - /* From the shared decode logic */ - switch (opcode) { - case 0x0: - rpt =3D 1; - selem =3D 4; - break; - case 0x2: - rpt =3D 4; - selem =3D 1; - break; - case 0x4: - rpt =3D 1; - selem =3D 3; - break; - case 0x6: - rpt =3D 3; - selem =3D 1; - break; - case 0x7: - rpt =3D 1; - selem =3D 1; - break; - case 0x8: - rpt =3D 1; - selem =3D 2; - break; - case 0xa: - rpt =3D 2; - selem =3D 1; - break; - default: - unallocated_encoding(s); - return; - } - - if (size =3D=3D 3 && !is_q && selem !=3D 1) { - /* reserved */ - unallocated_encoding(s); - return; - } - if (!fp_access_check(s)) { - return; + return true; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 @@ -3339,22 +3268,21 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) endian =3D MO_LE; } =20 - total =3D rpt * selem * (is_q ? 16 : 8); - tcg_rn =3D cpu_reg_sp(s, rn); + total =3D a->rpt * a->selem * (a->q ? 16 : 8); + tcg_rn =3D cpu_reg_sp(s, a->rn); =20 /* * Issue the MTE check vs the logical repeat count, before we * promote consecutive little-endian elements below. */ - clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - total); + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31,= total); =20 /* * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ align =3D MO_ALIGN; - if (selem =3D=3D 1 && endian =3D=3D MO_LE) { + if (a->selem =3D=3D 1 && endian =3D=3D MO_LE) { align =3D pow2_align(size); size =3D 3; } @@ -3363,45 +3291,118 @@ static void disas_ldst_multiple_struct(DisasContex= t *s, uint32_t insn) } mop =3D endian | size | align; =20 - elements =3D (is_q ? 16 : 8) >> size; + elements =3D (a->q ? 16 : 8) >> size; tcg_ebytes =3D tcg_constant_i64(1 << size); - for (r =3D 0; r < rpt; r++) { + for (r =3D 0; r < a->rpt; r++) { int e; for (e =3D 0; e < elements; e++) { int xs; - for (xs =3D 0; xs < selem; xs++) { - int tt =3D (rt + r + xs) % 32; - if (is_store) { - do_vec_st(s, tt, e, clean_addr, mop); - } else { - do_vec_ld(s, tt, e, clean_addr, mop); - } + for (xs =3D 0; xs < a->selem; xs++) { + int tt =3D (a->rt + r + xs) % 32; + do_vec_ld(s, tt, e, clean_addr, mop); tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } } } =20 - if (!is_store) { - /* For non-quad operations, setting a slice of the low - * 64 bits of the register clears the high 64 bits (in - * the ARM ARM pseudocode this is implicit in the fact - * that 'rval' is a 64 bit wide variable). - * For quad operations, we might still need to zero the - * high bits of SVE. - */ - for (r =3D 0; r < rpt * selem; r++) { - int tt =3D (rt + r) % 32; - clear_vec_high(s, is_q, tt); + /* + * For non-quad operations, setting a slice of the low 64 bits of + * the register clears the high 64 bits (in the ARM ARM pseudocode + * this is implicit in the fact that 'rval' is a 64 bit wide + * variable). For quad operations, we might still need to zero + * the high bits of SVE. + */ + for (r =3D 0; r < a->rpt * a->selem; r++) { + int tt =3D (a->rt + r) % 32; + clear_vec_high(s, a->q, tt); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; +} + +static bool trans_ST_mult(DisasContext *s, arg_ldst_mult *a) +{ + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp endian, align, mop; + + int total; /* total bytes */ + int elements; /* elements per vector */ + int r; + int size =3D a->sz; + + if (!a->p && a->rm !=3D 0) { + /* For non-postindexed accesses the Rm field must be 0 */ + return false; + } + if (size =3D=3D 3 && !a->q && a->selem !=3D 1) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + /* For our purposes, bytes are always little-endian. */ + endian =3D s->be_data; + if (size =3D=3D 0) { + endian =3D MO_LE; + } + + total =3D a->rpt * a->selem * (a->q ? 16 : 8); + tcg_rn =3D cpu_reg_sp(s, a->rn); + + /* + * Issue the MTE check vs the logical repeat count, before we + * promote consecutive little-endian elements below. + */ + clean_addr =3D gen_mte_checkN(s, tcg_rn, true, a->p || a->rn !=3D 31, = total); + + /* + * Consecutive little-endian elements from a single register + * can be promoted to a larger little-endian operation. + */ + align =3D MO_ALIGN; + if (a->selem =3D=3D 1 && endian =3D=3D MO_LE) { + align =3D pow2_align(size); + size =3D 3; + } + if (!s->align_mem) { + align =3D 0; + } + mop =3D endian | size | align; + + elements =3D (a->q ? 16 : 8) >> size; + tcg_ebytes =3D tcg_constant_i64(1 << size); + for (r =3D 0; r < a->rpt; r++) { + int e; + for (e =3D 0; e < elements; e++) { + int xs; + for (xs =3D 0; xs < a->selem; xs++) { + int tt =3D (a->rt + r + xs) % 32; + do_vec_st(s, tt, e, clean_addr, mop); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } } } =20 - if (is_postidx) { - if (rm =3D=3D 31) { + if (a->p) { + if (a->rm =3D=3D 31) { tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); } } + return true; } =20 /* AdvSIMD load/store single structure @@ -3746,9 +3747,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x0c: /* AdvSIMD load/store multiple structures */ - disas_ldst_multiple_struct(s, insn); - break; case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721290; cv=none; d=zohomail.com; s=zohoarc; b=Oo6jxw3TPxBN5QK84f5/26Me1ZFrQEYL0a78GLjjWhTmTmLMQEIIF6d3lf9SVfw98k0tZMvGFoOms3eAPOHGy4QOSLUsSZc3HUONRcMjAU02YB8klIiJVBal1z4BK0Z4CsJgimGKJvWUTCx11XLGZA5Ie6YvMjp/h18dshIQyg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721290; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H6fyr2YQkbjchR/WdhRPzKgYunXwMbfvKfnvzphQvVI=; b=ZNSfvefPVOszsbgb4WEpmIdsZMKuPJk78DIMN0sL9bAfS+R17h7Ci2sl+F4H6vrMqkp7bu5UZZVQjco6moqLJjty4s/NfSTtdQOpyNhWLiQpVjXgkpt18uRAjaofobmJjzaQu7tkctf0d+vo+8WMaDY/OLeLh9pgUVbobGPXVeE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721290052569.9844334755845; Fri, 2 Jun 2023 08:54:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5755-0003NF-3a; Fri, 02 Jun 2023 11:52:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5751-0003JD-Dk for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:43 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574u-0003aI-Lg for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:43 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-30ae61354fbso2094567f8f.3 for ; Fri, 02 Jun 2023 08:52:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721155; x=1688313155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=H6fyr2YQkbjchR/WdhRPzKgYunXwMbfvKfnvzphQvVI=; b=W/vArtXJyG0e6B3Up4dANO3h51G1TXeVXaMWevoAQqxh7Qvw1MMDL444rOBuDSsvtG vheDDKzS/KuNW3fefoX/Oqa+EasovsDqeriMdSuHUr38Q3366JIFbAtyO2qYEe9ZP6N5 8DzWwbM3cWRiTa+ILGCtRRJbzFpfTriAsj6RRwMr9cIjFB/10Y+Fj7bngbKZ1WcnRbp4 3NYGznTuwgz5cQDhmOAyqpZViMLm4tn5/4Bchuu0s9cRPJEVv5Izolerm/BIXYiupnNS MCmudjglIFfptCRw5P8P9eHQgu9UL8yH5Wp6DYG9BJXDNgw8go1yVaqZnehvgAgicFQA PxsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721155; x=1688313155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H6fyr2YQkbjchR/WdhRPzKgYunXwMbfvKfnvzphQvVI=; b=IPsJHSqQSzzTrdqPJYpjF0IeBiq6By3We2SQBnb0nPJT0hyR6CDHtLvc5AmQKojY00 IwZvU9lA+yVL//gSlsyR4kYw0IGkx72SuSKaf4l/A7XDRSkSqt0dA9KPcspqlto8MsP6 +EoaRSG2cefgZS7SRzdZzCC348UCyI6QMww6/IFJh+Yz5XqjjuJKn7j05lTjnVRGtm40 mQvImA3hpaLHGTrPzvoRu4QIcA+hALmWRL0sKjTjH6BcA+d4DqOmxPuPQ7k32iS8SU7k 4HjIuaplLd1waFv7O1sRV2vC2gZvkKako2Lv4AVOGCaInuDwJhuyiIz63Jg0zCyEUZqV a2uw== X-Gm-Message-State: AC+VfDwpzbVYn7hnaTmrxNPueDf8YIInQ+FgvST52YgidBeYRiPm7MMw 8q5qk3A/hnTHvI36bSi3ywwIYAvzPu080dLh9lw= X-Google-Smtp-Source: ACHHUZ7sonfJk8H85Xp6KWPmkA2PumaHl/mhqlRvY8S+oKF1MfEY3l8OFqfHYWlgH+UbR5uuo/2/0w== X-Received: by 2002:a5d:628b:0:b0:309:5029:b071 with SMTP id k11-20020a5d628b000000b003095029b071mr268512wru.45.1685721155208; Fri, 02 Jun 2023 08:52:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/20] target/arm: Convert load/store single structure to decodetree Date: Fri, 2 Jun 2023 16:52:22 +0100 Message-Id: <20230602155223.2040685-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721290857100009 Content-Type: text/plain; charset="utf-8" Convert the ASIMD load/store single structure insns to decodetree. Signed-off-by: Peter Maydell --- I note that compared to the old decoder this is rather harder to compare against the pseudocode; the old hand-decode can follow the pseudocode quite closely with its switch on 'scale', whereas here quite a lot of magic is happening in the calculation of 'index'. --- target/arm/tcg/a64.decode | 37 ++++++ target/arm/tcg/translate-a64.c | 228 ++++++++++++++++----------------- 2 files changed, 148 insertions(+), 117 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 12d331b4c2a..48461a0540e 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -494,3 +494,40 @@ LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... .= .... @ldst_mult rpt=3D3 sele LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 + +# Load/store single structure + +%ldst_single_selem 13:1 21:1 !function=3Dplus_1 +# The index is made up from bits Q, S and the size; we may then need to sc= ale +# it down by the size. +%ldst_single_index q:1 s:1 sz:2 +%ldst_single_index_scaled q:1 s:1 sz:2 scale:3 !function=3Duimm_scaled_down +%ldst_single_repl_scale 10:2 + +# We don't care about S in the trans functions (the decode folds it into +# the calculation of index), but we have to list it here so that we can +# handle the S-must-be-0 pattern lines. Similarly we don't care about sz +# once it has been used to calculate index. +&ldst_single rm rn rt sz p q s selem index scale repl + +@ldst_single . q:1 ...... p:1 . . rm:5 ... . .. rn:5 rt:5 \ + &ldst_single index=3D%ldst_single_index_scaled \ + selem=3D%ldst_single_selem repl=3D0 +@ldst_single_repl . q:1 ...... p:1 . . rm:5 ... . sz:2 rn:5 rt:5 \ + &ldst_single index=3D%ldst_single_index \ + scale=3D%ldst_single_repl_scale selem=3D%ldst_single_s= elem repl=3D1 + + +ST_single 0 . 001101 . 0 . ..... 00 . s:1 sz:2 ..... ..... @ldst_sin= gle scale=3D0 +ST_single 0 . 001101 . 0 . ..... 01 . s:1 00 ..... ..... @ldst_singl= e scale=3D1 sz=3D0 +ST_single 0 . 001101 . 0 . ..... 01 . s:1 10 ..... ..... @ldst_singl= e scale=3D1 sz=3D2 +ST_single 0 . 001101 . 0 . ..... 10 . s:1 00 ..... ..... @ldst_singl= e scale=3D2 sz=3D0 +ST_single 0 . 001101 . 0 . ..... 10 . 0 01 ..... ..... @ldst_single = scale=3D3 sz=3D1 s=3D0 + +LD_single 0 . 001101 . 1 . ..... 00 . s:1 sz:2 ..... ..... @ldst_sin= gle scale=3D0 +LD_single 0 . 001101 . 1 . ..... 01 . s:1 00 ..... ..... @ldst_singl= e scale=3D1 sz=3D0 +LD_single 0 . 001101 . 1 . ..... 01 . s:1 10 ..... ..... @ldst_singl= e scale=3D1 sz=3D2 +LD_single 0 . 001101 . 1 . ..... 10 . s:1 00 ..... ..... @ldst_singl= e scale=3D2 sz=3D0 +LD_single 0 . 001101 . 1 . ..... 10 . 0 01 ..... ..... @ldst_single = scale=3D3 sz=3D1 s=3D0 +# Replicating load case +LD_single_repl 0 . 001101 . 1 . ..... 11 . 0 .. ..... ..... @ldst_single_= repl s=3D0 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c3b22a74dd5..128c2b8b4b5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -72,6 +72,17 @@ static int uimm_scaled(DisasContext *s, int x) return imm << scale; } =20 +/* + * For ASIMD load/store single structure: immediate is in bits [31:3], + * and should be scaled down by the scale in bits [2:0]. + */ +static int uimm_scaled_down(DisasContext *s, int x) +{ + unsigned imm =3D x >> 3; + unsigned scale =3D extract32(x, 0, 3); + return imm >> scale; +} + /* * Include the generated decoders. */ @@ -3405,140 +3416,126 @@ static bool trans_ST_mult(DisasContext *s, arg_ld= st_mult *a) return true; } =20 -/* AdvSIMD load/store single structure - * - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt= | - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * - * AdvSIMD load/store single structure (post-indexed) - * - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt= | - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * - * Rt: first (or only) SIMD&FP register to be transferred - * Rn: base address or SP - * Rm (post-index only): post-index register (when !31) or size dependent = #imm - * index =3D encoded in Q:S:size dependent on size - * - * lane_size =3D encoded in R, opc - * transfer width =3D encoded in opc, S, size - */ -static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) +static bool trans_ST_single(DisasContext *s, arg_ldst_single *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rm =3D extract32(insn, 16, 5); - int size =3D extract32(insn, 10, 2); - int S =3D extract32(insn, 12, 1); - int opc =3D extract32(insn, 13, 3); - int R =3D extract32(insn, 21, 1); - int is_load =3D extract32(insn, 22, 1); - int is_postidx =3D extract32(insn, 23, 1); - int is_q =3D extract32(insn, 30, 1); - - int scale =3D extract32(opc, 1, 2); - int selem =3D (extract32(opc, 0, 1) << 1 | R) + 1; - bool replicate =3D false; - int index =3D is_q << 3 | S << 2 | size; - int xs, total; + int xs, total, rt; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp mop; =20 - if (extract32(insn, 31, 1)) { - unallocated_encoding(s); - return; + if (!a->p && a->rm !=3D 0) { + return false; } - if (!is_postidx && rm !=3D 0) { - unallocated_encoding(s); - return; - } - - switch (scale) { - case 3: - if (!is_load || S) { - unallocated_encoding(s); - return; - } - scale =3D size; - replicate =3D true; - break; - case 0: - break; - case 1: - if (extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } - index >>=3D 1; - break; - case 2: - if (extract32(size, 1, 1)) { - unallocated_encoding(s); - return; - } - if (!extract32(size, 0, 1)) { - index >>=3D 2; - } else { - if (S) { - unallocated_encoding(s); - return; - } - index >>=3D 3; - scale =3D 3; - } - break; - default: - g_assert_not_reached(); - } - if (!fp_access_check(s)) { - return; + return true; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - total =3D selem << scale; - tcg_rn =3D cpu_reg_sp(s, rn); + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); =20 - clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, - total); - mop =3D finalize_memop(s, scale); + clean_addr =3D gen_mte_checkN(s, tcg_rn, true, a->p || a->rn !=3D 31, = total); + mop =3D finalize_memop(s, a->scale); =20 - tcg_ebytes =3D tcg_constant_i64(1 << scale); - for (xs =3D 0; xs < selem; xs++) { - if (replicate) { - /* Load and replicate to all elements */ - TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); - - tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop= ); - tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), - (is_q + 1) * 8, vec_full_reg_size(s), - tcg_tmp); - } else { - /* Load/store one element per register */ - if (is_load) { - do_vec_ld(s, rt, index, clean_addr, mop); - } else { - do_vec_st(s, rt, index, clean_addr, mop); - } - } + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + do_vec_st(s, rt, a->index, clean_addr, mop); tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); - rt =3D (rt + 1) % 32; } =20 - if (is_postidx) { - if (rm =3D=3D 31) { + if (a->p) { + if (a->rm =3D=3D 31) { tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); } } + return true; +} + +static bool trans_LD_single(DisasContext *s, arg_ldst_single *a) +{ + int xs, total, rt; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; + + if (!a->p && a->rm !=3D 0) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); + + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31,= total); + mop =3D finalize_memop(s, a->scale); + + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + do_vec_ld(s, rt, a->index, clean_addr, mop); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; +} + +static bool trans_LD_single_repl(DisasContext *s, arg_ldst_single *a) +{ + int xs, total, rt; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; + + if (!a->p && a->rm !=3D 0) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); + + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31,= total); + mop =3D finalize_memop(s, a->scale); + + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + /* Load and replicate to all elements */ + TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop); + tcg_gen_gvec_dup_i64(a->scale, vec_full_reg_offset(s, rt), + (a->q + 1) * 8, vec_full_reg_size(s), tcg_tmp= ); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; } =20 /* @@ -3747,9 +3744,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x0d: /* AdvSIMD load/store single structure */ - disas_ldst_single_struct(s, insn); - break; case 0x19: if (extract32(insn, 21, 1) !=3D 0) { disas_ldst_tag(s, insn); --=20 2.34.1 From nobody Sun Apr 28 15:51:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685721274; cv=none; d=zohomail.com; s=zohoarc; b=E864ps1aexoLo+LWZ82LF2WUeQTXbvG4VlgsRuAd78TWUfuuRUKb9qQp5+4O7+HOVpJb29saO5TXJr3+MkLkwtteWRdld8qvNwr/HyYdJFL8IJA78myiTjstvLAjSqeuQrwJE+mGgwybPfMhjimSG13zyfH6vBnhOfYOrku0FIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685721274; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qVPU8SNdw7l7jU/aq5e0Zs3nkjyb7fPSLLV/sNWv28M=; b=K8naEpeRl/KQn138UdzlsOTVWiSHy7Ho+fxEinzaINZcSWIeecmhpklVQO7ucCNBBxa2rf9S3twwMIi67daDuOXCmZ7UQmKitQn5YaGF3KisFjYL7KqvuZ7fB9czeQR/RSMeOAok+IQ3P4IzSwsk4OorgGz3D3n7OLiycjNwZDM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685721274053771.3162822522896; Fri, 2 Jun 2023 08:54:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5755-0003NY-NJ; Fri, 02 Jun 2023 11:52:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5752-0003KL-21 for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:44 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q574v-0003cp-4p for qemu-devel@nongnu.org; Fri, 02 Jun 2023 11:52:43 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f611ccd06eso21085245e9.0 for ; Fri, 02 Jun 2023 08:52:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685721155; x=1688313155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qVPU8SNdw7l7jU/aq5e0Zs3nkjyb7fPSLLV/sNWv28M=; b=h7uX57yi/zuB2xBn1eF2JbDNi2ryMjtD2F5j/sefokDNT87UD6tdZ9fSaQgQ6cDn6k gCxfMSscQ+7rBc0iAweIjo6eiA2Z0pCjeeqCbQRjnK9JhgMOhpsFBZ3Uwp9E99OMRXGI QYSaVm4cSjuc3BKYXVgcRZ2Q2WgPP9aBwq5+pdhBk4uahWqJGfAz8tFGDbLccEsLi82/ uvPK3rcU7hskWt+qbwMo07wsKdSgoh5YeSVlmF054nEX1O3PdiJb0Y634narJhYo9CJq 3pdQ0aCmW/rLkL3Wjyxas3JLMPxsujb9WjBycTI6LY0hMguUUU/TJeQbES8F4lEffBmd QlkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685721155; x=1688313155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qVPU8SNdw7l7jU/aq5e0Zs3nkjyb7fPSLLV/sNWv28M=; b=GuN7u1DTrz6MkS63FbPVE2Z6GOwgIUpmK0QVwM5F4eBjHmR2pQz7e0WTxBfU3dcx65 E6pFEZ+nEuSMwpI69sX+yP2geKTDnzuFlad7W1IU1If08/RE5qH0M+HpUiaf/qfmD3wg RUf7NN0gSS2NrXf2T4n/qrVKH6/Q+b/rBuAjlW40tz5j+h1lVTrHsjr44cjSaSn0RFKC 46IYTk+TXHgjobVrxCA3iMw8sEOZ+AWWuDyqPwggdnuZv6DtKDIVMSF2F3426XdO0BbP r/5P6ApGpdv3P/bzAyFR/0p+Cat+F1twpxG1MQKdi4I9t8VEToTysVsH4eiLwdAt+M9T c3kw== X-Gm-Message-State: AC+VfDwN9BmN+IMn3Alj2x+7iTveVAocR+zWNK1INzeDlretMWdMf2dH eFg2IC6PUDhiKNLtSP+9FERgjQC3gnU6+j8JGuU= X-Google-Smtp-Source: ACHHUZ5FIfKNRFiuptdA2kPQLEk33aRh+TBapgh5/F+da79r+0cmg2PtA21DbrArMJ/iOLfgO7qn5A== X-Received: by 2002:a1c:f710:0:b0:3f6:d09:5d46 with SMTP id v16-20020a1cf710000000b003f60d095d46mr1938639wmh.20.1685721155713; Fri, 02 Jun 2023 08:52:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 20/20] target/arm: Convert load/store tags insns to decodetree Date: Fri, 2 Jun 2023 16:52:23 +0100 Message-Id: <20230602155223.2040685-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602155223.2040685-1-peter.maydell@linaro.org> References: <20230602155223.2040685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685721274917100013 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store memory tags instruction group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 25 +++ target/arm/tcg/translate-a64.c | 352 ++++++++++++++++----------------- 2 files changed, 195 insertions(+), 182 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 48461a0540e..62ead5554fc 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -531,3 +531,28 @@ LD_single 0 . 001101 . 1 . ..... 10 . s:1 00 ...= .. ..... @ldst_single scal LD_single 0 . 001101 . 1 . ..... 10 . 0 01 ..... ..... @ldst_single = scale=3D3 sz=3D1 s=3D0 # Replicating load case LD_single_repl 0 . 001101 . 1 . ..... 11 . 0 .. ..... ..... @ldst_single_= repl s=3D0 + +%tag_offset 12:s9 !function=3Dscale_by_log2_tag_granule +&ldst_tag rn rt imm p w +@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=3D%tag_= offset +@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=3D0 + +STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 128c2b8b4b5..6ca598291a7 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -83,6 +83,12 @@ static int uimm_scaled_down(DisasContext *s, int x) return imm >> scale; } =20 +/* For load/store memory tags: scale offset by LOG2_TAG_GRANULE */ +static int scale_by_log2_tag_granule(DisasContext *s, int x) +{ + return x << LOG2_TAG_GRANULE; +} + /* * Include the generated decoders. */ @@ -3538,181 +3544,180 @@ static bool trans_LD_single_repl(DisasContext *s,= arg_ldst_single *a) return true; } =20 -/* - * Load/Store memory tags - * - * 31 30 29 24 22 21 12 10 5 0 - * +-----+-------------+-----+---+------+-----+------+------+ - * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | - * +-----+-------------+-----+---+------+-----+------+------+ - */ -static void disas_ldst_tag(DisasContext *s, uint32_t insn) +static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; - int op2 =3D extract32(insn, 10, 2); - int op1 =3D extract32(insn, 22, 2); - bool is_load =3D false, is_pair =3D false, is_zero =3D false, is_mult = =3D false; - int index =3D 0; TCGv_i64 addr, clean_addr, tcg_rt; + int size =3D 4 << s->dcz_blocksize; =20 - /* We checked insn bits [29:24,21] in the caller. */ - if (extract32(insn, 30, 2) !=3D 3) { - goto do_unallocated; + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; } =20 - /* - * @index is a tri-state variable which has 3 states: - * < 0 : post-index, writeback - * =3D 0 : signed offset - * > 0 : pre-index, writeback - */ - switch (op1) { - case 0: - if (op2 !=3D 0) { - /* STG */ - index =3D op2 - 2; - } else { - /* STZGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_zero =3D true; - } - break; - case 1: - if (op2 !=3D 0) { - /* STZG */ - is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDG */ - is_load =3D true; - } - break; - case 2: - if (op2 !=3D 0) { - /* ST2G */ - is_pair =3D true; - index =3D op2 - 2; - } else { - /* STGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D true; - } - break; - case 3: - if (op2 !=3D 0) { - /* STZ2G */ - is_pair =3D is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_load =3D true; - } - break; - - default: - do_unallocated: - unallocated_encoding(s); - return; - } - - if (is_mult - ? !dc_isar_feature(aa64_mte, s) - : !dc_isar_feature(aa64_mte_insn_reg, s)) { - goto do_unallocated; - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - addr =3D read_cpu_reg_sp(s, rn, true); - if (index >=3D 0) { + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); + } + /* + * The non-tags portion of STZGM is mostly like DC_ZVA, + * except the alignment happens before the access. + */ + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_helper_dc_zva(cpu_env, clean_addr); + return true; +} + +static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stgm(cpu_env, addr, tcg_rt); + } else { + MMUAccessType acc =3D MMU_DATA_STORE; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + } + return true; +} + +static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_ldgm(tcg_rt, cpu_env, addr); + } else { + MMUAccessType acc =3D MMU_DATA_LOAD; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + /* The result tags are zeros. */ + tcg_gen_movi_i64(tcg_rt, 0); + } + return true; +} + +static bool trans_LDG(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { /* pre-index or signed offset */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } =20 - if (is_mult) { - tcg_rt =3D cpu_reg(s, rt); + tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); + tcg_rt =3D cpu_reg(s, a->rt); + if (s->ata) { + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + } else { + clean_addr =3D clean_data_tbi(s, addr); + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); + gen_address_with_allocation_tag0(tcg_rt, addr); + } =20 - if (is_zero) { - int size =3D 4 << s->dcz_blocksize; - - if (s->ata) { - gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); - } - /* - * The non-tags portion of STZGM is mostly like DC_ZVA, - * except the alignment happens before the access. - */ - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_helper_dc_zva(cpu_env, clean_addr); - } else if (s->ata) { - if (is_load) { - gen_helper_ldgm(tcg_rt, cpu_env, addr); - } else { - gen_helper_stgm(cpu_env, addr, tcg_rt); - } - } else { - MMUAccessType acc =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; - int size =3D 4 << GMID_EL1_BS; - - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_probe_access(s, clean_addr, acc, size); - - if (is_load) { - /* The result tags are zeros. */ - tcg_gen_movi_i64(tcg_rt, 0); - } + if (a->w) { + /* pre-index or post-index */ + if (a->p) { + /* post-index */ + tcg_gen_addi_i64(addr, addr, a->imm); } - return; + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); + } + return true; +} + +static bool do_STG(DisasContext *s, arg_ldst_tag *a, bool is_zero, bool is= _pair) +{ + TCGv_i64 addr, tcg_rt; + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); } =20 - if (is_load) { - tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); - tcg_rt =3D cpu_reg(s, rt); - if (s->ata) { - gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(addr, addr, a->imm); + } + tcg_rt =3D cpu_reg_sp(s, a->rt); + if (!s->ata) { + /* + * For STG and ST2G, we need to check alignment and probe memory. + * TODO: For STZG and STZ2G, we could rely on the stores below, + * at least for system mode; user-only won't enforce alignment. + */ + if (is_pair) { + gen_helper_st2g_stub(cpu_env, addr); } else { - clean_addr =3D clean_data_tbi(s, addr); - gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); - gen_address_with_allocation_tag0(tcg_rt, addr); + gen_helper_stg_stub(cpu_env, addr); + } + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, addr, tcg_rt); } } else { - tcg_rt =3D cpu_reg_sp(s, rt); - if (!s->ata) { - /* - * For STG and ST2G, we need to check alignment and probe memo= ry. - * TODO: For STZG and STZ2G, we could rely on the stores below, - * at least for system mode; user-only won't enforce alignment. - */ - if (is_pair) { - gen_helper_st2g_stub(cpu_env, addr); - } else { - gen_helper_stg_stub(cpu_env, addr); - } - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (is_pair) { - gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg_parallel(cpu_env, addr, tcg_rt); - } + if (is_pair) { + gen_helper_st2g(cpu_env, addr, tcg_rt); } else { - if (is_pair) { - gen_helper_st2g(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg(cpu_env, addr, tcg_rt); - } + gen_helper_stg(cpu_env, addr, tcg_rt); } } =20 @@ -3730,32 +3735,21 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) } } =20 - if (index !=3D 0) { + if (a->w) { /* pre-index or post-index */ - if (index < 0) { + if (a->p) { /* post-index */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); } + return true; } =20 -/* Loads and stores */ -static void disas_ldst(DisasContext *s, uint32_t insn) -{ - switch (extract32(insn, 24, 6)) { - case 0x19: - if (extract32(insn, 21, 1) !=3D 0) { - disas_ldst_tag(s, insn); - } else { - unallocated_encoding(s); - } - break; - default: - unallocated_encoding(s); - break; - } -} +TRANS_FEAT(STG, aa64_mte_insn_reg, do_STG, a, false, false) +TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true, false) +TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true) +TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true) =20 typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); =20 @@ -13651,12 +13645,6 @@ static bool btype_destination_ok(uint32_t insn, bo= ol bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0x4: - case 0x6: - case 0xc: - case 0xe: /* Loads and stores */ - disas_ldst(s, insn); - break; case 0x5: case 0xd: /* Data processing - register */ disas_data_proc_reg(s, insn); --=20 2.34.1