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b=kbUgkZ8t6BL8YTA44bBn/BQhPNPaL7FSlQLC51TH0ky7SMG059Xi5roQ04r21E6N+EQa e+rgy8HzYLYPdJjyeEa5Y4Si0lyXtiujVU/C8DDF3qoncgVPS8Rg4RuHzHh2CBzH9wQ2 95hStWzudhzJuBq+JQ4bGNqSqwTE1gBq44Kq/eYydrw+18cx4hwZ3JdiblSsddTjoMz7 xu3VGnfsoU1J0AAfV9C24OO9uyFxjFn+AesDgdQ4QhexA7bLL64JbEn8GsGF+rVK2nkS +5nc6DPhqhjHJkfdbAr6ozeU3O7G9+VfRF2BjX7954lLXldUSF/o7smr1m5sjOjBQNQ5 Yg== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/5] pnv/xive2: Add definition for TCTXT Config register Date: Thu, 1 Jun 2023 14:13:27 +0200 Message-Id: <20230601121331.487207-2-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230601121331.487207-1-fbarrat@linux.ibm.com> References: <20230601121331.487207-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: -CQ_yegQDlzlznB041pQC903sbvljzO5 X-Proofpoint-ORIG-GUID: W6sbWzzN4emHeaPDmp-_3n7FR9eW792I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_08,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010107 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1685621673829100001 Add basic read/write support for the TCTXT Config register on P10. qemu doesn't do anything with it yet, but it avoids logging a guest error when skiboot configures the fused-core state: qemu-system-ppc64 -machine powernv10 ... -d guest_errors ... [ 0.131670000,5] XIVE: [ IC 00 ] Initializing XIVE block ID 0... XIVE[0] - TCTXT: invalid read @140 XIVE[0] - TCTXT: invalid write @140 Signed-off-by: Frederic Barrat Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 8 +++++++- hw/intc/pnv_xive2_regs.h | 4 ++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index e688381536..f0817a124f 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1269,6 +1269,9 @@ static uint64_t pnv_xive2_ic_tctxt_read(void *opaque,= hwaddr offset, case TCTXT_EN1_RESET: val =3D xive->tctxt_regs[TCTXT_EN1 >> 3]; break; + case TCTXT_CFG: + val =3D xive->tctxt_regs[reg]; + break; default: xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); } @@ -1280,6 +1283,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hw= addr offset, uint64_t val, unsigned size) { PnvXive2 *xive =3D PNV_XIVE2(opaque); + uint32_t reg =3D offset >> 3; =20 switch (offset) { /* @@ -1301,7 +1305,9 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hw= addr offset, case TCTXT_EN1_RESET: xive->tctxt_regs[TCTXT_EN1 >> 3] &=3D ~val; break; - + case TCTXT_CFG: + xive->tctxt_regs[reg] =3D val; + break; default: xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); return; diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index 0c096e4adb..8f1e0a1fde 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -405,6 +405,10 @@ #define X_TCTXT_EN1_RESET 0x307 #define TCTXT_EN1_RESET 0x038 =20 +/* TCTXT Config register */ +#define X_TCTXT_CFG 0x328 +#define TCTXT_CFG 0x140 + /* * VSD Tables */ --=20 2.40.1 From nobody Sun May 5 09:20:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1685621687; cv=none; d=zohomail.com; s=zohoarc; b=kFAGMmLYhsuoPLVeN+rE9PIXlyT9Ck7MFaVF18yrj/ETY36sRNc4zSIxBXdS+lUW2Ez10NP73shXm5rk2r5Asxh6wpRfyddK+tOhtk3Gf9XbcmPHUPmpv8sXeuaVUVti8NbLsKxxPQGRzRpLqRYnRP0b9/HJlQ9DutOc84E9u9E= ARC-Message-Signature: i=1; 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Thu, 1 Jun 2023 12:13:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pp1; bh=Oboc4Z93T7V7Zawd6MSzuroFswZQPgqdUWimiJPWQ1M=; b=ob/RdRzzhWXBh0lW2qB615oUH7UEZtOhZENm6tD7RZFeSNyGsmuxIr3gHglAXkmRQ25+ fXnKmGdH3Q6Lbl80xzkj+4hewAqd7sMM5PRbUpaNlp3iB+YoGixxoIphfi5x0NeLoq0l NiXzzoVddG9+Qr1qD0deTnyVyTM+XWMs/MtC9ogr1Jj9ad1GeW0j4h+im3l2/WZUTkx+ LcsyK07JedD8QVRY3eMdHNeRCE6AGNrk/YdYi/reSTQJF2+tUvfKjBdT3ZqO40QcUPSw elaH4JLKI9NQxmYAgRGeuSwqLWC0lm79P09V3coKl7Ys/pxNozCBWPIgoJJaDRUAJMsk jw== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/5] pnv/xive2: Add definition for the ESB cache configuration register Date: Thu, 1 Jun 2023 14:13:28 +0200 Message-Id: <20230601121331.487207-3-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230601121331.487207-1-fbarrat@linux.ibm.com> References: <20230601121331.487207-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: _3VOIIR4zYaeEIMskJ-bN4SJy5NeV5IO X-Proofpoint-GUID: AcHZVastytFX3ZSGfPW0lr4ohTeQWdEp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_08,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=929 impostorscore=0 malwarescore=0 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010107 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1685621689057100003 Add basic read/write support for the ESB cache configuration register on P10. We don't model the ESB cache in qemu so reading/writing the register won't do anything, but it avoids logging a guest error when skiboot configures it: qemu-system-ppc64 -machine powernv10 ... -d guest_errors ... XIVE[0] - VC: invalid read @240 XIVE[0] - VC: invalid write @240 Signed-off-by: Frederic Barrat Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 7 +++++++ hw/intc/pnv_xive2_regs.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index f0817a124f..9778c102ff 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -959,6 +959,10 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwa= ddr offset, val =3D xive->vc_regs[reg]; break; =20 + case VC_ESBC_CFG: + val =3D xive->vc_regs[reg]; + break; + /* * EAS cache updates (not modeled) */ @@ -1050,6 +1054,9 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwadd= r offset, /* ESB update */ break; =20 + case VC_ESBC_CFG: + break; + /* * EAS cache updates (not modeled) */ diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index 8f1e0a1fde..7165dc8704 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -232,6 +232,10 @@ #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-= bit */ =20 +/* ESBC configuration */ +#define X_VC_ESBC_CFG 0x148 +#define VC_ESBC_CFG 0x240 + /* EASC flush control register */ #define X_VC_EASC_FLUSH_CTRL 0x160 #define VC_EASC_FLUSH_CTRL 0x300 --=20 2.40.1 From nobody Sun May 5 09:20:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 01 Jun 2023 12:13:35 +0000 Received: from smtpav07.fra02v.mail.ibm.com (smtpav07.fra02v.mail.ibm.com [10.20.54.106]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 351CDWXZ46072534 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 Jun 2023 12:13:32 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A191120043; Thu, 1 Jun 2023 12:13:32 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6070620040; Thu, 1 Jun 2023 12:13:32 +0000 (GMT) Received: from borneo.tlslab.ibm.com (unknown [9.101.4.34]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 1 Jun 2023 12:13:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pp1; bh=dAsS/ojcoado6y/0eFsk8pg4lyZtCpJ32Z8IIcbNrrE=; b=QEvO9nsut3s2A1vrdJ4eP7dsuGAd517qO4BjdRQvlrqdHlZZdATF5i6m4u0i4aIITJHY 18zWgk2eYTtcqIMtCqHJfop2eveoNvK3l3Jgk0h40VW4Op9aDQmYAfawnm17EK99Wj+v EAWcZSFO7YW3vEZ0UYcwEYPHU0ZTbSIsfSmSZXM8GjvsCxqWtcxMSB82eNA8wk67pFYs 5uXd3YIWJG8jRzVN0tHZh0eJ0eDYM7sMuxzvmNcTDQQpmfJ0pOtT56nUxhVABvprVAci EUO29jkACWJmdNuq7o6gUX6VMqRPk57r1BCTXRRSG5dgQE/Erd6qY6lG6TqnSwpZp2IT Bw== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 3/5] pnv/xive2: Allow writes to the Physical Thread Enable registers Date: Thu, 1 Jun 2023 14:13:29 +0200 Message-Id: <20230601121331.487207-4-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230601121331.487207-1-fbarrat@linux.ibm.com> References: <20230601121331.487207-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 2Dv5knej-76wzO6fPM4pEZbsih0ke2SB X-Proofpoint-GUID: Fmtqg0X8dvZGLxiYGNpp0Ei_0evB6SYb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_08,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=719 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 suspectscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010107 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1685621669961100002 Fix what was probably a silly mistake and allow to write the Physical Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET variant so it went unnoticed, but there's no reason to discard a write to the full register, it is Read-Write. Fixes: da71b7e3ed45 ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip") Signed-off-by: Frederic Barrat Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 9778c102ff..5fc4240216 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1298,6 +1298,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hw= addr offset, */ case TCTXT_EN0: /* Physical Thread Enable */ case TCTXT_EN1: /* Physical Thread Enable (fused core) */ + xive->tctxt_regs[reg] =3D val; break; =20 case TCTXT_EN0_SET: --=20 2.40.1 From nobody Sun May 5 09:20:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1685621729; cv=none; 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Thu, 1 Jun 2023 12:13:32 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B138720040; Thu, 1 Jun 2023 12:13:32 +0000 (GMT) Received: from borneo.tlslab.ibm.com (unknown [9.101.4.34]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 1 Jun 2023 12:13:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=43K/NS77euRNwN8uAXX5rAiKbH6iwtPbAQNRraXIros=; b=GrMhM1VWxtmwAspzfU27Wjh07+xrKEz7SLXqKRF66hsp7nZnWJ/C8pcjgYwij4JfSZN9 ID9b3g1RlOYAV7+Cg5/Wl42IEkUYBjyMFxJFj4fILbMsvSj+bYT1iu819GSJXNWLS6yv S01YshQX9pZ4jOwdaEnMZVlgf24TWR2YJ9xeKlOUx1zOqZ+v66qwnGHxEKnq1EfEua6D 7zwtZ9Y/vUSHkTFIZebfW+BlNA20oz0a684SoIpaUx21VUBUifoZjKq+mzo0z28Izr8r qwzqIHPjrtMJ3NbaURxeQb7KHLh0MddXbldG9Xh+6t+2PosaEJCMpg2hl3zgpHLSY7Fe mw== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 4/5] pnv/xive2: Introduce macros to manipulate TIMA addresses Date: Thu, 1 Jun 2023 14:13:30 +0200 Message-Id: <20230601121331.487207-5-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230601121331.487207-1-fbarrat@linux.ibm.com> References: <20230601121331.487207-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4pRKtbCIJ1-8_m4TD8wPMlVqElKFkQJT X-Proofpoint-ORIG-GUID: i8e45toJ-8T7lZU26g2UvmPcubdu2lRh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_08,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 mlxscore=0 bulkscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010107 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1685621730488100002 Content-Type: text/plain; charset="utf-8" TIMA addresses are somewhat special and are split in several bit fields with different meanings. This patch describes it and introduce macros to more easily access the various fields. Signed-off-by: Frederic Barrat Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 14 +++++++------- include/hw/ppc/xive_regs.h | 16 ++++++++++++++++ 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index a986b96843..ebe399bc09 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -249,7 +249,7 @@ static const uint8_t *xive_tm_views[] =3D { static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) { uint8_t page_offset =3D (offset >> TM_SHIFT) & 0x3; - uint8_t reg_offset =3D offset & 0x3F; + uint8_t reg_offset =3D offset & TM_REG_OFFSET; uint8_t reg_mask =3D write ? 0x1 : 0x2; uint64_t mask =3D 0x0; int i; @@ -266,8 +266,8 @@ static uint64_t xive_tm_mask(hwaddr offset, unsigned si= ze, bool write) static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t valu= e, unsigned size) { - uint8_t ring_offset =3D offset & 0x30; - uint8_t reg_offset =3D offset & 0x3F; + uint8_t ring_offset =3D offset & TM_RING_OFFSET; + uint8_t reg_offset =3D offset & TM_REG_OFFSET; uint64_t mask =3D xive_tm_mask(offset, size, true); int i; =20 @@ -296,8 +296,8 @@ static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr of= fset, uint64_t value, =20 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned s= ize) { - uint8_t ring_offset =3D offset & 0x30; - uint8_t reg_offset =3D offset & 0x3F; + uint8_t ring_offset =3D offset & TM_RING_OFFSET; + uint8_t reg_offset =3D offset & TM_REG_OFFSET; uint64_t mask =3D xive_tm_mask(offset, size, false); uint64_t ret; int i; @@ -534,7 +534,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *= tctx, hwaddr offset, /* * First, check for special operations in the 2K region */ - if (offset & 0x800) { + if (offset & TM_SPECIAL_OP) { xto =3D xive_tm_find_op(offset, size, true); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " @@ -573,7 +573,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCT= X *tctx, hwaddr offset, /* * First, check for special operations in the 2K region */ - if (offset & 0x800) { + if (offset & TM_SPECIAL_OP) { xto =3D xive_tm_find_op(offset, size, false); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to T= IMA" diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index b7fde2354e..4a3c9badd3 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -48,6 +48,22 @@ =20 #define TM_SHIFT 16 =20 +/* + * TIMA addresses are 12-bits (4k page). + * The MSB indicates a special op with side effect, which can be + * refined with bit 10 (see below). + * The registers, logically grouped in 4 rings (a quad-word each), are + * defined on the 6 LSBs (offset below 0x40) + * In between, we can add a cache line index from 0...3 (ie, 0, 0x80, + * 0x100, 0x180) to select a specific snooper. Those 'snoop port + * address' bits should be dropped when processing the operations as + * they are all equivalent. + */ +#define TM_ADDRESS_MASK 0xC3F +#define TM_SPECIAL_OP 0x800 +#define TM_RING_OFFSET 0x30 +#define TM_REG_OFFSET 0x3F + /* TM register offsets */ #define TM_QW0_USER 0x000 /* All rings */ #define TM_QW1_OS 0x010 /* Ring 0..2 */ --=20 2.40.1 From nobody Sun May 5 09:20:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1685621708; cv=none; d=zohomail.com; s=zohoarc; b=ZWDX8vt4WwvI7AAXiD9Uu0BnjeGvx/7xRaSJjBVq2QC+9b9Ju0OxwRAnrjPjXD2YahBCjb5+IkowZe4iaMa+6ZpPNWDScTw8sIYYJEYqnrwRWNUaYFtisYW6YDqNYq55eQz73kmZ9398yvfqeWxFFi8OI5z9MApaqK05lKUcLeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 1 Jun 2023 12:13:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=epjw7tIm1w2H+tjkyrmjil5RlzEj8mp136Kpy7A/0+8=; b=rRcreH/FF1zk7Pfa4jq+U7CQorRsZ0Re+BJyia/VoHkdVfnSSMfcdm9jxcKmtukAzzXX yXxD8sMVkiSIuKWLFUjnTxjEyMigFMom37+lIKJyWIGXWb42KEQN1eX+5tORM4mXAbMz dZ6GbG7yqjEeGp2SQ/pyNmIq7aiyOHeZlPL2utSAPS74pmpiYYuU2tXDooxJcs2h67F6 WwhqQa7f7khiR4SXAgWQH907jJrkbtA5TiymRPA6E6aDmyeO1x9vDcGmcS2ha/mFZsWL 9bOiPbhyXSF29epT3Tib1q8MOcAFtD2PwWqvp8hYeplD2ukC6gK1HJzcO6Jce5kRoCtk 9A== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 5/5] pnv/xive2: Handle TIMA access through all ports Date: Thu, 1 Jun 2023 14:13:31 +0200 Message-Id: <20230601121331.487207-6-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230601121331.487207-1-fbarrat@linux.ibm.com> References: <20230601121331.487207-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: qWRv6SasNK-dujMPq-2duIdw9PPvozPx X-Proofpoint-ORIG-GUID: _iutn7G9h48w6PU_oUGL-bZBDx_9Qb52 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_08,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010107 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1685621710168100005 Content-Type: text/plain; charset="utf-8" The Thread Interrupt Management Area (TIMA) can be accessed through 4 ports, targeted by the address. The base address of a TIMA is using port 0 and the other ports are 0x80 apart. Using one port or another can be useful to balance the load on the snoop buses. With skiboot and linux, we currently use port 0, but as it tends to be busy, another hypervisor is using port 1 for TIMA access. The port address bits fall in between the special op indication bits (the 2 MSBs) and the register offset bits (the 6 LSBs). They are "don't care" for the hardware when processing a TIMA operation. This patch filters out those port address bits so that a TIMA operation can be triggered using any port. It is also true for indirect access (through the IC BAR) and it's actually nothing new, it was already the case on P9. Which helps here, as the TIMA handling code is common between P9 (xive) and P10 (xive2). Signed-off-by: Frederic Barrat Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 4 ++++ hw/intc/xive.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 5fc4240216..ec1edeb385 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1666,6 +1666,8 @@ static void pnv_xive2_tm_write(void *opaque, hwaddr o= ffset, bool gen1_tima_os =3D xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; =20 + offset &=3D TM_ADDRESS_MASK; + /* TODO: should we switch the TM ops table instead ? */ if (!gen1_tima_os && offset =3D=3D HV_PUSH_OS_CTX_OFFSET) { xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); @@ -1685,6 +1687,8 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwadd= r offset, unsigned size) bool gen1_tima_os =3D xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; =20 + offset &=3D TM_ADDRESS_MASK; + /* TODO: should we switch the TM ops table instead ? */ if (!gen1_tima_os && offset =3D=3D HV_PULL_OS_CTX_OFFSET) { return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index ebe399bc09..5204c14b87 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -500,7 +500,7 @@ static const XiveTmOp xive_tm_operations[] =3D { static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool = write) { uint8_t page_offset =3D (offset >> TM_SHIFT) & 0x3; - uint32_t op_offset =3D offset & 0xFFF; + uint32_t op_offset =3D offset & TM_ADDRESS_MASK; int i; =20 for (i =3D 0; i < ARRAY_SIZE(xive_tm_operations); i++) { --=20 2.40.1