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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685565503714100002 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 5caf42649a..3dda3a73f8 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s) =20 static uint32_t arm_timer_read(void *opaque, hwaddr offset) { - arm_timer_state *s =3D (arm_timer_state *)opaque; + arm_timer_state *s =3D opaque; =20 switch (offset >> 2) { case 0: /* TimerLoad */ @@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int= reload) static void arm_timer_write(void *opaque, hwaddr offset, uint32_t value) { - arm_timer_state *s =3D (arm_timer_state *)opaque; + arm_timer_state *s =3D opaque; int freq; =20 switch (offset >> 2) { @@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset, =20 static void arm_timer_tick(void *opaque) { - arm_timer_state *s =3D (arm_timer_state *)opaque; + arm_timer_state *s =3D opaque; s->int_level =3D 1; arm_timer_update(s); } @@ -214,7 +214,7 @@ static const uint8_t sp804_ids[] =3D { /* Merge the IRQs from the two component devices. */ static void sp804_set_irq(void *opaque, int irq, int level) { - SP804State *s =3D (SP804State *)opaque; + SP804State *s =3D opaque; =20 s->level[irq] =3D level; qemu_set_irq(s->irq, s->level[0] || s->level[1]); @@ -223,7 +223,7 @@ static void sp804_set_irq(void *opaque, int irq, int le= vel) static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { - SP804State *s =3D (SP804State *)opaque; + SP804State *s =3D opaque; =20 if (offset < 0x20) { return arm_timer_read(s->timer[0], offset); @@ -255,7 +255,7 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - SP804State *s =3D (SP804State *)opaque; + SP804State *s =3D opaque; =20 if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); @@ -349,7 +349,7 @@ struct icp_pit_state { static uint64_t icp_pit_read(void *opaque, hwaddr offset, unsigned size) { - icp_pit_state *s =3D (icp_pit_state *)opaque; + icp_pit_state *s =3D opaque; int n; =20 /* ??? Don't know the PrimeCell ID for this device. */ @@ -365,7 +365,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offse= t, static void icp_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - icp_pit_state *s =3D (icp_pit_state *)opaque; + icp_pit_state *s =3D opaque; int n; =20 n =3D offset >> 8; --=20 2.38.1