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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685565569784100001 Introduce the ARM_TIMER sysbus device. arm_timer_new() is converted as QOM instance init()/finalize() handlers. Note in arm_timer_finalize() we release a ptimer handle which was previously leaked. ArmTimerState is directly embedded into SP804State/IcpPitState, and is initialized as a QOM child. Since the timer frequency belongs to ARM_TIMER, have it hold the QOM property. SP804State/IcpPitState directly access it. Similarly the SP804State/IcpPitState input IRQ becomes the ARM_TIMER sysbus output IRQ. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/arm_timer.c | 109 +++++++++++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 39 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 82123b40c0..a929fbba62 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -17,6 +17,7 @@ #include "qemu/module.h" #include "qemu/log.h" #include "qom/object.h" +#include "qapi/error.h" =20 /* Common timer implementation. */ =20 @@ -29,14 +30,18 @@ #define TIMER_CTRL_PERIODIC (1 << 6) #define TIMER_CTRL_ENABLE (1 << 7) =20 -typedef struct { +#define TYPE_ARM_TIMER "arm-timer" +OBJECT_DECLARE_SIMPLE_TYPE(ArmTimerState, ARM_TIMER) + +struct ArmTimerState { + SysBusDevice parent_obj; ptimer_state *timer; uint32_t control; uint32_t limit; uint32_t freq; int int_level; qemu_irq irq; -} ArmTimerState; +}; =20 /* Check all active timers, and schedule the next timer interrupt. */ =20 @@ -172,23 +177,42 @@ static const VMStateDescription vmstate_arm_timer =3D= { } }; =20 -static void arm_timer_reset(ArmTimerState *s) +static void arm_timer_reset(DeviceState *dev) { + ArmTimerState *s =3D ARM_TIMER(dev); + s->control =3D TIMER_CTRL_IE; } =20 -static ArmTimerState *arm_timer_new(uint32_t freq, qemu_irq irq_out) +static void arm_timer_init(Object *obj) { - ArmTimerState *s; + ArmTimerState *s =3D ARM_TIMER(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 - s =3D g_new0(ArmTimerState, 1); - s->freq =3D freq; - arm_timer_reset(s); - - s->irq =3D irq_out; s->timer =3D ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); - return s; + + sysbus_init_irq(sbd, &s->irq); +} + +static void arm_timer_finalize(Object *obj) +{ + ArmTimerState *s =3D ARM_TIMER(obj); + + ptimer_free(s->timer); +} + +static Property arm_timer_properties[] =3D { + DEFINE_PROP_UINT32("freq", ArmTimerState, freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void arm_timer_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->reset =3D arm_timer_reset; + dc->vmsd =3D &vmstate_arm_timer; + device_class_set_props(dc, arm_timer_properties); } =20 /* @@ -204,11 +228,9 @@ struct SP804State { SysBusDevice parent_obj; =20 MemoryRegion iomem; - ArmTimerState *timer[2]; - uint32_t freq[2]; + ArmTimerState timer[2]; int level[2]; qemu_irq irq; - qemu_irq irq_in[2]; }; =20 static const uint8_t sp804_ids[] =3D { @@ -233,10 +255,10 @@ static uint64_t sp804_read(void *opaque, hwaddr offse= t, SP804State *s =3D opaque; =20 if (offset < 0x20) { - return arm_timer_read(s->timer[0], offset); + return arm_timer_read(&s->timer[0], offset); } if (offset < 0x40) { - return arm_timer_read(s->timer[1], offset - 0x20); + return arm_timer_read(&s->timer[1], offset - 0x20); } =20 /* TimerPeriphID */ @@ -265,12 +287,12 @@ static void sp804_write(void *opaque, hwaddr offset, SP804State *s =3D opaque; =20 if (offset < 0x20) { - arm_timer_write(s->timer[0], offset, value); + arm_timer_write(&s->timer[0], offset, value); return; } =20 if (offset < 0x40) { - arm_timer_write(s->timer[1], offset - 0x20, value); + arm_timer_write(&s->timer[1], offset - 0x20, value); return; } =20 @@ -304,6 +326,12 @@ static void sp804_init(Object *obj) memory_region_init_io(&s->iomem, obj, &sp804_ops, s, "sp804", 0x1000); sysbus_init_mmio(sbd, &s->iomem); + + qdev_init_gpio_in_named(DEVICE(obj), sp804_set_irq, + "timer-in", ARRAY_SIZE(s->timer)); + for (unsigned i =3D 0; i < ARRAY_SIZE(s->timer); i++) { + object_initialize_child(obj, "timer[*]", &s->timer[i], TYPE_ARM_TI= MER); + } } =20 static void sp804_realize(DeviceState *dev, Error **errp) @@ -311,23 +339,17 @@ static void sp804_realize(DeviceState *dev, Error **e= rrp) SP804State *s =3D SP804(dev); =20 for (unsigned i =3D 0; i < ARRAY_SIZE(s->timer); i++) { - s->irq_in[i] =3D qemu_allocate_irq(sp804_set_irq, s, i); - s->timer[i] =3D arm_timer_new(s->freq[i], s->irq_in[i]); - } -} - -static void sp804_unrealize(DeviceState *dev) -{ - SP804State *s =3D SP804(dev); - - for (unsigned i =3D 0; i < ARRAY_SIZE(s->timer); i++) { - qemu_free_irq(s->irq_in[i]); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, + qdev_get_gpio_in_named(dev, "timer-in", i)); } } =20 static Property sp804_properties[] =3D { - DEFINE_PROP_UINT32("freq0", SP804State, freq[0], 1000000), - DEFINE_PROP_UINT32("freq1", SP804State, freq[1], 1000000), + DEFINE_PROP_UINT32("freq0", SP804State, timer[0].freq, 1000000), + DEFINE_PROP_UINT32("freq1", SP804State, timer[1].freq, 1000000), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -336,7 +358,6 @@ static void sp804_class_init(ObjectClass *klass, void *= data) DeviceClass *k =3D DEVICE_CLASS(klass); =20 k->realize =3D sp804_realize; - k->unrealize =3D sp804_unrealize; device_class_set_props(k, sp804_properties); k->vmsd =3D &vmstate_sp804; } @@ -350,8 +371,7 @@ struct IntegratorPitState { SysBusDevice parent_obj; =20 MemoryRegion iomem; - ArmTimerState *timer[3]; - qemu_irq irq_in[3]; + ArmTimerState timer[3]; qemu_irq irq[3]; }; =20 @@ -368,7 +388,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offse= t, return 0; } =20 - return arm_timer_read(s->timer[n], offset & 0xff); + return arm_timer_read(&s->timer[n], offset & 0xff); } =20 static void icp_pit_write(void *opaque, hwaddr offset, @@ -383,7 +403,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, return; } =20 - arm_timer_write(s->timer[n], offset & 0xff, value); + arm_timer_write(&s->timer[n], offset & 0xff, value); } =20 static const MemoryRegionOps icp_pit_ops =3D { @@ -414,7 +434,8 @@ static void icp_pit_init(Object *obj) "timer-in", ARRAY_SIZE(s->timer)); =20 for (unsigned i =3D 0; i < ARRAY_SIZE(s->timer); i++) { - s->timer[i] =3D arm_timer_new(tmr_freq[i], s->irq_in[i]); + object_initialize_child(obj, "timer[*]", &s->timer[i], TYPE_ARM_TI= MER); + qdev_prop_set_uint32(DEVICE(&s->timer[i]), "freq", tmr_freq[i]); sysbus_init_irq(dev, &s->irq[i]); } =20 @@ -430,7 +451,10 @@ static void icp_pit_realize(DeviceState *dev, Error **= errp) IntegratorPitState *s =3D INTEGRATOR_PIT(dev); =20 for (unsigned i =3D 0; i < ARRAY_SIZE(s->timer); i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, qdev_get_gpio_in_named(dev, "timer-in", i)); } } @@ -444,6 +468,13 @@ static void icp_pit_class_init(ObjectClass *klass, voi= d *data) =20 static const TypeInfo arm_timer_types[] =3D { { + .name =3D TYPE_ARM_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ArmTimerState), + .instance_init =3D arm_timer_init, + .instance_finalize =3D arm_timer_finalize, + .class_init =3D arm_timer_class_init, + }, { .name =3D TYPE_INTEGRATOR_PIT, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(IntegratorPitState), --=20 2.38.1